Esempio n. 1
0
/**
  * @brief  Restore peripheral config before entering DEEPSLEEP mode.
  * @param  None
  * @retval None
  */
static void RestoreConfiguration(void)
{
    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
    
    /* SYSCLK, HCLK, PCLK configuration */
    /* Enable HSE */
    RCC_HSEConfig( RCC_HSE_ON );
    
    /* Wait till HSE is ready and if Time out is reached exit */
    HSEStatus = RCC_WaitForHSEStartUp();
    
    if (HSEStatus == (uint32_t)0x01)
    {
    /* HCLK = SYSCLK */
    RCC_AHBConfig(RCC_SYSCLK_DIV1); 
    
    /* PCLK = HCLK */
    RCC_APB1Config(RCC_APB1AHB_DIV1);
        
    /*  PLL configuration:  = HSE *  6 = 48 MHz */
    RCC_HSEPREDVConfig(RCC_HSEPREDV1_DIV1);
    RCC_PLLConfig(RCC_PLLSOURCE_HSEPREDIV, RCC_GCFGR_PLLMF6);
    
    /* Enable PLL */
    RCC_PLL_Enable(ENABLE);
    
    /* PLL as system clock source */
    RCC_CK_SYSConfig(RCC_SYSCLKSOURCE_PLLCLK);
    } 
}
Esempio n. 2
0
void clk_init(void)
{
// disable external oscillator so we can use pins PF0 , PF1 
RCC_HSEConfig(RCC_HSE_OFF);
// this should be enabled already 
RCC_HSI_Enable(ENABLE);
// wait for HSI to stabilize
// this is redundant
while( !RCC_GetBitState(RCC_FLAG_HSISTB) );
// this should be enabled already 
RCC_CK_SYSConfig(RCC_SYSCLKSOURCE_HSI);

RCC_PLLConfig(RCC_PLLSOURCE_HSI_DIV2 , 18);
RCC_PLL_Enable(ENABLE);

// wait for pll to stablilize
// this is redundant
while( !RCC_GetBitState(RCC_FLAG_PLLSTB) );
RCC_CK_SYSConfig(RCC_SYSCLKSOURCE_PLLCLK);

// wait for clock to change to pll
while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)RCC_GCFGR_SCSS_PLL);

RCC_AHBConfig(RCC_SYSCLK_DIV1); // config ahb clock divider
RCC_APB1Config(RCC_APB1AHB_DIV1);
RCC_APB2Config(RCC_APB2AHB_DIV1);
				
}