static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn) {
char str[8][32];
int i;
r_strbuf_init (&op->esil);
r_strbuf_set (&op->esil, "");
if (insn) {
// caching operands
for (i=0; i<insn->detail->mips.op_count && i<8; i++) {
*str[i]=0;
ARG (i);
}
}
if (insn)
switch (insn->id) {
case MIPS_INS_NOP:
r_strbuf_setf (&op->esil, ",");
break;
case MIPS_INS_BREAK:
r_strbuf_setf (&op->esil, "%s,%s,TRAP", ARG (0), ARG (0));
break;
case MIPS_INS_SW:
case MIPS_INS_SWL:
case MIPS_INS_SWR:
r_strbuf_appendf (&op->esil, "%s,%s,=[4]",
ARG (0), ARG (1));
break;
case MIPS_INS_SH:
r_strbuf_appendf (&op->esil, "%s,%s,=[2]",
ARG (0), ARG (1));
break;
case MIPS_INS_SWC1:
case MIPS_INS_SWC2:
r_strbuf_setf (&op->esil, "%s,$", ARG (1));
break;
case MIPS_INS_SB:
r_strbuf_appendf (&op->esil, "%s,%s,=[1]",
ARG (0), ARG (1));
break;
case MIPS_INS_CMP:
case MIPS_INS_CMPU:
case MIPS_INS_CMPGU:
case MIPS_INS_CMPGDU:
case MIPS_INS_CMPI:
r_strbuf_appendf (&op->esil, "%s,%s,==", ARG (1), ARG (0));
break;
case MIPS_INS_SHRAV:
case MIPS_INS_SHRAV_R:
case MIPS_INS_SHRA:
case MIPS_INS_SHRA_R:
case MIPS_INS_SRA:
r_strbuf_appendf (&op->esil, "%s,%s,>>,31,%s,>>,?{,32,%s,-,%s,1,<<,1,-,<<,}{,0,},|,%s,=,",
ARG (2), ARG (1), ARG (1), ARG (2), ARG (2), ARG (0));
break;
case MIPS_INS_SHRL:
// suffix 'S' forces conditional flag to be updated
case MIPS_INS_SRLV:
case MIPS_INS_SRL:
r_strbuf_appendf (&op->esil, "%s,%s,>>,%s,=", ARG (2), ARG (1), ARG (0));
break;
case MIPS_INS_SLLV:
case MIPS_INS_SLL:
r_strbuf_appendf (&op->esil, "%s,%s,<<,%s,=", ARG (2), ARG (1), ARG (0));
break;
case MIPS_INS_BAL:
case MIPS_INS_JAL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "," ES_CALL_D ("%s"), ARG (0));
break;
case MIPS_INS_JALR:
case MIPS_INS_JALRS:
if (OPCOUNT () < 2) {
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "," ES_CALL_D ("%s"), ARG (0));
} else {
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "," ES_CALL_DR ("%s","%s"), ARG (0), ARG (1));
}
}
break;
case MIPS_INS_JALRC: // no delay
if (OPCOUNT () < 2) {
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "," ES_CALL_ND ("%s"), ARG (0));
} else {
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "," ES_CALL_NDR ("%s","%s"), ARG (0), ARG (1));
}
}
break;
case MIPS_INS_JRADDIUSP:
// increment stackpointer in X and jump to %ra
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",%d,sp,+=,"ES_J ("ra"), ARG (0));
break;
case MIPS_INS_JR:
case MIPS_INS_JRC:
case MIPS_INS_J:
case MIPS_INS_B: // ???
// jump to address with conditional
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "," ES_J ("%s"), ARG (0));
break;
case MIPS_INS_BNE: // bne $s, $t, offset
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",%s,%s,==,$z,!,?{,"ES_J ("%s")",}",
ARG (0), ARG (1), ARG (2));
break;
case MIPS_INS_BEQ:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",%s,%s,==,$z,?{,"ES_J ("%s")",}",
ARG (0), ARG (1), ARG (2));
break;
case MIPS_INS_BZ:
case MIPS_INS_BEQZ:
case MIPS_INS_BEQZC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",%s,0,==,$z,?{,"ES_J ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BNEZ:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",%s,0,==,$z,!,?{,"ES_J ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BEQZALC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",%s,0,==,$z,?{,"ES_CALL_ND ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BLEZ:
case MIPS_INS_BLEZC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,%s,==,$z,?{,"ES_J ("%s")",BREAK,},",
ARG (0), ARG (1));
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",1,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGEZ:
case MIPS_INS_BGEZC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGEZAL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_D ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGEZALC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_ND ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGTZALC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,%s,==,$z,?{,BREAK,},", ARG(0));
r_strbuf_appendf (&op->esil, "0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_ND ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BLTZAL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",1,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_D ("%s")",}", ARG(0), ARG(1));
break;
case MIPS_INS_BLTZ:
case MIPS_INS_BLTZC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",1,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGTZ:
case MIPS_INS_BGTZC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,%s,==,$z,?{,BREAK,},", ARG (0));
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BTEQZ:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,t,==,$z,?{,"ES_J ("%s")",}", ARG (0));
break;
case MIPS_INS_BTNEZ:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,t,==,$z,!,?{,"ES_J ("%s")",}", ARG (0));
break;
case MIPS_INS_MOV:
case MIPS_INS_MOVE:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "%s,%s,=", ARG (1), REG (0));
}
break;
case MIPS_INS_MOVZ:
case MIPS_INS_MOVF:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "0,%s,==,$z,?{,%s,%s,=,}",
ARG (2), ARG (1), REG (0));
}
break;
case MIPS_INS_MOVT:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "1,%s,==,$z,?{,%s,%s,=,}",
ARG (2), ARG (1), REG (0));
}
break;
case MIPS_INS_FSUB:
case MIPS_INS_SUB:
case MIPS_INS_SUBU:
case MIPS_INS_DSUB:
case MIPS_INS_DSUBU:
PROTECT_ZERO () {
r_strbuf_appendf(&op->esil, "%s,%s,-,%s,=",
ARG (2), ARG (1), ARG (0));
}
break;
case MIPS_INS_NEG:
case MIPS_INS_NEGU:
r_strbuf_appendf (&op->esil, "%s,0,-,%s,=,",
ARG (1), ARG (0));
break;
/** signed -- sets overflow flag */
case MIPS_INS_ADD:
{
PROTECT_ZERO () {
r_strbuf_appendf(&op->esil, "%s,%s,+,%s,=",
ARG (1), ARG (2), ARG (0));
#if 0
r_strbuf_appendf (&op->esil,
"0,32,%s,%s,+,>>,>,?{,1,TRAP,}{,%s,%s,+,%s,=,}",
ARG(2), ARG(1), ARG(2), ARG(1), ARG(0));
#endif
}
}
break;
case MIPS_INS_ADDI:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "0,32,%s,0xffffffff,&,%s,+,>>,>,?{,1,TRAP,}{,%s,%s,+,%s,=,}",
ARG(2), ARG(1), ARG(2), ARG(1), ARG(0));
}
break;
case MIPS_INS_DADD:
case MIPS_INS_DADDI:
/** unsigned */
case MIPS_INS_ADDU:
case MIPS_INS_ADDIU:
case MIPS_INS_DADDIU:
{
const char *arg0 = ARG(0);
const char *arg1 = ARG(1);
const char *arg2 = ARG(2);
PROTECT_ZERO () {
if (*arg2 == '-') {
r_strbuf_appendf (&op->esil, "%s,%s,-,%s,=",
arg2+1, arg1, arg0);
} else {
r_strbuf_appendf (&op->esil, "%s,%s,+,%s,=",
arg2, arg1, arg0);
}
}
}
break;
case MIPS_INS_LI:
r_strbuf_appendf (&op->esil, "0x%"PFMT64x",%s,=", IMM(1), ARG(0));
break;
case MIPS_INS_LUI:
r_strbuf_appendf (&op->esil, "0x%"PFMT64x"0000,%s,=", IMM(1), ARG(0));
break;
case MIPS_INS_LB:
case MIPS_INS_LBU:
//one of these is wrong
ESIL_LOAD ("1");
break;
case MIPS_INS_LW:
case MIPS_INS_LWC1:
case MIPS_INS_LWC2:
case MIPS_INS_LWL:
case MIPS_INS_LWR:
case MIPS_INS_LWU:
case MIPS_INS_LL:
case MIPS_INS_LLD:
case MIPS_INS_LD:
case MIPS_INS_LDI:
case MIPS_INS_LDL:
case MIPS_INS_LDC1:
case MIPS_INS_LDC2:
ESIL_LOAD ("4");
break;
case MIPS_INS_LWX:
case MIPS_INS_LH:
case MIPS_INS_LHU:
case MIPS_INS_LHX:
ESIL_LOAD ("2");
break;
case MIPS_INS_AND:
case MIPS_INS_ANDI:
{
const char *arg0 = ARG(0);
const char *arg1 = ARG(1);
const char *arg2 = ARG(2);
if (!strcmp (arg0, arg1)) {
r_strbuf_appendf (&op->esil, "%s,%s,&=", arg2, arg1);
} else {
r_strbuf_appendf (&op->esil, "%s,%s,&,%s,=", arg2, arg1, arg0);
}
}
break;
case MIPS_INS_OR:
case MIPS_INS_ORI:
{
const char *arg0 = ARG(0);
const char *arg1 = ARG(1);
const char *arg2 = ARG(2);
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "%s,%s,|,%s,=",
arg2, arg1, arg0);
}
}
break;
case MIPS_INS_XOR:
case MIPS_INS_XORI:
{
const char *arg0 = ARG(0);
const char *arg1 = ARG(1);
const char *arg2 = ARG(2);
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "%s,%s,^,%s,=",
arg2, arg1, arg0);
}
}
break;
case MIPS_INS_NOR:
{
const char *arg0 = ARG(0);
const char *arg1 = ARG(1);
const char *arg2 = ARG(2);
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "%s,%s,|,0xffffffff,^,%s,=",
arg2, arg1, arg0);
}
}
break;
case MIPS_INS_SLT:
case MIPS_INS_SLTI:
if (OPCOUNT () < 3) {
r_strbuf_appendf (&op->esil,
ES_IS_NEGATIVE ("%s")","
ES_IS_NEGATIVE ("%s")","
"==,$z,?{,"
"%s,%s,<,t,=,"
"}{,"
"%s,%s,>=,t,=,"
"}",
ARG (1),
ARG (0),
ARG (1), ARG (0),
ARG (1), ARG (0));
} else {
r_strbuf_appendf (&op->esil,
ES_IS_NEGATIVE ("%s")","
ES_IS_NEGATIVE ("%s")","
"==,$z,?{,"
"%s,%s,<,%s,=,"
"}{,"
"%s,%s,>=,%s,=,"
"}",
ARG (2),
ARG (1),
ARG (2), ARG (1), ARG (0),
ARG (2), ARG (1), ARG (0));
}
break;
case MIPS_INS_SLTU:
case MIPS_INS_SLTIU:
if (OPCOUNT () < 3) {
r_strbuf_appendf (&op->esil, "%s,0xffffffff,&,%s,0xffffffff,&,<,t,=",
ARG (1), ARG (0));
} else {
r_strbuf_appendf (&op->esil, "%s,0xffffffff,&,%s,0xffffffff,&,<,%s,=",
ARG (2), ARG (1), ARG (0));
}
break;
case MIPS_INS_MULT:
case MIPS_INS_MULTU:
r_strbuf_appendf (&op->esil,
"%s,%s,*,0xffffffff,&,lo,=,"
ES_SIGN_EXT64 ("lo")
",32,%s,%s,*,>>,0xffffffff,&,hi,=,"
ES_SIGN_EXT64 ("hi"),
ARG (0), ARG (1), ARG (0), ARG (1));
break;
case MIPS_INS_MFLO:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "lo,%s,=", REG (0));
}
break;
case MIPS_INS_MFHI:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "hi,%s,=", REG (0));
}
break;
case MIPS_INS_MTLO:
r_strbuf_appendf (&op->esil, "%s,lo,=,"ES_SIGN_EXT64 ("lo"), REG (0));
break;
case MIPS_INS_MTHI:
r_strbuf_appendf (&op->esil, "%s,hi,=,"ES_SIGN_EXT64 ("hi"), REG (0));
break;
#if 0
// could not test div
case MIPS_INS_DIV:
case MIPS_INS_DIVU:
case MIPS_INS_DDIV:
case MIPS_INS_DDIVU:
PROTECT_ZERO () {
// 32 bit needs sign extend
r_strbuf_appendf (&op->esil, "%s,%s,/,lo,=,%s,%s,%%,hi,=", REG(1), REG(0), REG(1), REG(0));
}
break;
#endif
default:
return -1;
}
return 0;
}
/*---------------------------------------------------------------------------*/
void
uart_init(uint8_t uart)
{
const uart_regs_t *regs;
if(uart >= UART_INSTANCE_COUNT) {
return;
}
regs = &uart_regs[uart];
if(regs->rx.port < 0 || regs->tx.port < 0) {
return;
}
lpm_register_peripheral(permit_pm1);
/* Enable clock for the UART while Running, in Sleep and Deep Sleep */
REG(SYS_CTRL_RCGCUART) |= regs->sys_ctrl_rcgcuart_uart;
REG(SYS_CTRL_SCGCUART) |= regs->sys_ctrl_scgcuart_uart;
REG(SYS_CTRL_DCGCUART) |= regs->sys_ctrl_dcgcuart_uart;
/* Run on SYS_DIV */
REG(regs->base + UART_CC) = 0;
/*
* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
*
* The value to be written will be on of the IOC_INPUT_SEL_Pxn defines from
* ioc.h. The value can also be calculated as:
*
* (port << 3) + pin
*/
REG(regs->ioc_uartrxd_uart) = (regs->rx.port << 3) + regs->rx.pin;
/*
* Pad Control for the TX pin:
* - Set function to UARTn TX
* - Output Enable
*/
ioc_set_sel(regs->tx.port, regs->tx.pin, regs->ioc_pxx_sel_uart_txd);
ioc_set_over(regs->tx.port, regs->tx.pin, IOC_OVERRIDE_OE);
/* Set RX and TX pins to peripheral mode */
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->tx.port),
GPIO_PIN_MASK(regs->tx.pin));
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rx.port),
GPIO_PIN_MASK(regs->rx.pin));
/*
* UART Interrupt Masks:
* Acknowledge RX and RX Timeout
* Acknowledge Framing, Overrun and Break Errors
*/
REG(regs->base + UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
REG(regs->base + UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
REG(regs->base + UART_IFLS) =
UART_IFLS_RXIFLSEL_1_8 | UART_IFLS_TXIFLSEL_1_2;
/* Make sure the UART is disabled before trying to configure it */
REG(regs->base + UART_CTL) = UART_CTL_VALUE;
/* Baud Rate Generation */
REG(regs->base + UART_IBRD) = regs->ibrd;
REG(regs->base + UART_FBRD) = regs->fbrd;
/* UART Control: 8N1 with FIFOs */
REG(regs->base + UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
/*
* Enable hardware flow control (RTS/CTS) if requested.
* Note that hardware flow control is available only on UART1.
*/
if(regs->cts.port >= 0) {
REG(IOC_UARTCTS_UART1) = ioc_input_sel(regs->cts.port, regs->cts.pin);
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->cts.port), GPIO_PIN_MASK(regs->cts.pin));
ioc_set_over(regs->cts.port, regs->cts.pin, IOC_OVERRIDE_DIS);
REG(UART_1_BASE + UART_CTL) |= UART_CTL_CTSEN;
}
if(regs->rts.port >= 0) {
ioc_set_sel(regs->rts.port, regs->rts.pin, IOC_PXX_SEL_UART1_RTS);
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rts.port), GPIO_PIN_MASK(regs->rts.pin));
ioc_set_over(regs->rts.port, regs->rts.pin, IOC_OVERRIDE_OE);
REG(UART_1_BASE + UART_CTL) |= UART_CTL_RTSEN;
}
/* UART Enable */
REG(regs->base + UART_CTL) |= UART_CTL_UARTEN;
/* Enable UART0 Interrupts */
nvic_interrupt_enable(regs->nvic_int);
}
/**
* Get the current state of the link.
*
* @returns true if link is up.
*/
bool Phy::isLinkUp(PPHY pPhy)
{
return (REG(PSSTAT) & PSSTAT_LINK) != 0;
}
static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn) {
char str[32][32];
r_strbuf_init (&op->esil);
r_strbuf_set (&op->esil, "");
if (insn)
switch (insn->id) {
case MIPS_INS_NOP:
r_strbuf_setf (&op->esil, ",");
break;
case MIPS_INS_SW:
r_strbuf_appendf (&op->esil, "%s,%s,=[4]",
ARG(0), ARG(1));
break;
case MIPS_INS_SWC1:
case MIPS_INS_SWC2:
r_strbuf_setf (&op->esil, "%s,$", ARG(1));
break;
case MIPS_INS_SB:
r_strbuf_appendf (&op->esil, "%s,%s,=[1]",
ARG(0), ARG(1));
break;
case MIPS_INS_CMP:
case MIPS_INS_CMPU:
case MIPS_INS_CMPGU:
case MIPS_INS_CMPGDU:
case MIPS_INS_CMPI:
r_strbuf_appendf (&op->esil, "%s,%s,==", ARG(1), ARG(0));
break;
case MIPS_INS_SHRAV:
case MIPS_INS_SHRAV_R:
case MIPS_INS_SHRA:
case MIPS_INS_SHRA_R:
case MIPS_INS_SRA:
r_strbuf_appendf (&op->esil, "%s,%s,>>,31,%s,>>,?{,32,%s,-,%s,1,<<,1,-,<<,}{,0,},|,%s,=,",
ARG(2), ARG(1), ARG(1), ARG(2), ARG(2), ARG(0));
break;
case MIPS_INS_SHRL:
// suffix 'S' forces conditional flag to be updated
case MIPS_INS_SRLV:
case MIPS_INS_SRL:
r_strbuf_appendf (&op->esil, "%s,%s,>>,%s,=", ARG(2), ARG(1), ARG(0));
break;
case MIPS_INS_SLLV:
case MIPS_INS_SLL:
r_strbuf_appendf (&op->esil, "%s,%s,<<,%s,=", ARG(2), ARG(1), ARG(0));
break;
case MIPS_INS_BAL:
case MIPS_INS_JAL:
case MIPS_INS_JALR:
case MIPS_INS_JALRS:
case MIPS_INS_JALRC:
case MIPS_INS_BLTZAL: // Branch on less than zero and link
r_strbuf_appendf (&op->esil, "pc,8,+,ra,=,%s,pc,=", ARG(0));
break;
case MIPS_INS_JRADDIUSP:
// increment stackpointer in X and jump to %ra
r_strbuf_appendf (&op->esil, "%d,sp,+=,ra,pc,=", ARG(0));
break;
case MIPS_INS_JR:
case MIPS_INS_JRC:
case MIPS_INS_J:
// jump to address with conditional
r_strbuf_appendf (&op->esil, "%s,pc,=", ARG(0));
break;
case MIPS_INS_B: // ???
case MIPS_INS_BZ:
case MIPS_INS_BGTZ:
case MIPS_INS_BGTZC:
case MIPS_INS_BGTZALC:
case MIPS_INS_BGEZ:
case MIPS_INS_BGEZC:
case MIPS_INS_BGEZAL: // Branch on less than zero and link
case MIPS_INS_BGEZALC:
r_strbuf_appendf (&op->esil, "%s,pc,=", ARG(0));
break;
case MIPS_INS_BNE: // bne $s, $t, offset
case MIPS_INS_BNEZ:
r_strbuf_appendf (&op->esil, "%s,%s,==,!,?{,%s,pc,=,}",
ARG(0), ARG(1), ARG(2));
break;
case MIPS_INS_BEQ:
case MIPS_INS_BEQZ:
case MIPS_INS_BEQZC:
case MIPS_INS_BEQZALC:
r_strbuf_appendf (&op->esil, "%s,%s,==,?{,%s,pc,=,}",
ARG(0), ARG(1), ARG(2));
break;
case MIPS_INS_BTEQZ:
case MIPS_INS_BTNEZ:
r_strbuf_appendf (&op->esil, "%s,pc,=", ARG(0));
break;
case MIPS_INS_MOV:
case MIPS_INS_MOVE:
case MIPS_INS_MOVF:
case MIPS_INS_MOVT:
case MIPS_INS_MOVZ:
if (REG(0)[0]!='z'){
r_strbuf_appendf (&op->esil, "%s,%s,=", ARG(1), REG(0));
} else {
r_strbuf_appendf (&op->esil, ",");
}
break;
case MIPS_INS_FSUB:
case MIPS_INS_SUB:
if (REG(0)[0]!='z'){
r_strbuf_appendf(&op->esil, "%s,%s,>,?{,$$,}{,%s,%s,-,%s,=",ARG(2), ARG(1), ARG(1), ARG(2), ARG(0));
} else {
r_strbuf_appendf (&op->esil, ",");
}
break;
case MIPS_INS_SUBU:
case MIPS_INS_NEGU:
case MIPS_INS_DSUB:
case MIPS_INS_DSUBU:
{
const char *arg0 = ARG(0);
const char *arg1 = ARG(1);
const char *arg2 = ARG(2);
r_strbuf_appendf (&op->esil, "%s,%s,-,%s,=",
arg2, arg1, arg0);
}
break;
/** signed -- sets overflow flag */
case MIPS_INS_ADD:
{
if (REG(0)[0]!='z'){
r_strbuf_appendf (&op->esil, "32,%s,%s,+,>>,0,>,?{,$$,}{,%s,%s,+,%s,=,}",
ARG(2), ARG(1), ARG(2), ARG(1), ARG(0));
} else {
r_strbuf_appendf (&op->esil, ",");
}
}
break;
case MIPS_INS_ADDI:
if (REG(0)[0]!='z'){
r_strbuf_appendf (&op->esil, "32,%s,0xffffffff,&,%s,+,>>,0,>,?{,$$,}{,%s,%s,+,%s,=,}",
ARG(2), ARG(1), ARG(2), ARG(1), ARG(0));
} else {
r_strbuf_appendf (&op->esil, ",");
}
break;
case MIPS_INS_DADD:
case MIPS_INS_DADDI:
/** unsigned */
case MIPS_INS_ADDU:
case MIPS_INS_ADDIU:
case MIPS_INS_DADDIU:
{
const char *arg0 = ARG(0);
const char *arg1 = ARG(1);
const char *arg2 = ARG(2);
if (REG(0)[0]!='z'){
r_strbuf_appendf (&op->esil, "%s,%s,+,%s,=",
arg2, arg1, arg0);
} else {
r_strbuf_appendf (&op->esil, ",");
}
}
break;
case MIPS_INS_LI:
r_strbuf_appendf (&op->esil, "0x%"PFMT64x",%s,=", IMM(1), ARG(0));
break;
case MIPS_INS_LUI:
r_strbuf_appendf (&op->esil, "0x%"PFMT64x"0000,%s,=", IMM(1), ARG(0));
break;
case MIPS_INS_LB:
case MIPS_INS_LBU:
//one of these is wrong
r_strbuf_appendf (&op->esil, "%s,[1],%s,=",
ARG(1), REG(0));
break;
case MIPS_INS_LW:
case MIPS_INS_LWC1:
case MIPS_INS_LWC2:
case MIPS_INS_LWL:
case MIPS_INS_LWR:
case MIPS_INS_LWU:
case MIPS_INS_LWX:
case MIPS_INS_LH:
case MIPS_INS_LHX:
case MIPS_INS_LL:
case MIPS_INS_LLD:
case MIPS_INS_LD:
case MIPS_INS_LDI:
case MIPS_INS_LDL:
case MIPS_INS_LDC1:
case MIPS_INS_LDC2:
r_strbuf_appendf (&op->esil, "%s,[4],%s,=",
ARG(1), REG(0));
break;
case MIPS_INS_AND:
case MIPS_INS_ANDI:
{
const char *arg0 = ARG(0);
const char *arg1 = ARG(1);
const char *arg2 = ARG(2);
r_strbuf_appendf (&op->esil, "%s,%s,&,%s,=",
arg2, arg1, arg0);
}
break;
case MIPS_INS_OR:
case MIPS_INS_ORI:
{
const char *arg0 = ARG(0);
const char *arg1 = ARG(1);
const char *arg2 = ARG(2);
if (REG(0)[0]!='z'){
r_strbuf_appendf (&op->esil, "%s,%s,|,%s,=",
arg2, arg1, arg0);
} else {
r_strbuf_appendf (&op->esil, ",");
}
}
break;
case MIPS_INS_XOR:
case MIPS_INS_XORI:
{
const char *arg0 = ARG(0);
const char *arg1 = ARG(1);
const char *arg2 = ARG(2);
if (REG(0)[0]!='z'){
r_strbuf_appendf (&op->esil, "%s,%s,^,%s,=",
arg2, arg1, arg0);
} else {
r_strbuf_appendf (&op->esil, ",");
}
}
break;
case MIPS_INS_NOR:
{
const char *arg0 = ARG(0);
const char *arg1 = ARG(1);
const char *arg2 = ARG(2);
if (REG(0)[0]!='z'){
r_strbuf_appendf (&op->esil, "%s,%s,|,0xffffffff,^,%s,=",
arg2, arg1, arg0);
} else {
r_strbuf_appendf (&op->esil, ",");
}
}
break;
case MIPS_INS_SLTU:
r_strbuf_appendf (&op->esil, "%s,%s,<,%s,=", ARG(1), ARG(2), ARG(0));
break;
case MIPS_INS_SLTIU:
{
r_strbuf_appendf (&op->esil, "%s,0xffffffff,&,%s,0xffffffff,<,?{%s,1,=,}{,%s,0,=,}",
ARG(1), ARG(2), ARG(0), ARG(0));
}
break;
}
return 0;
}
inline void vm_JMP_REG(int32_t param1, int32_t unused param2)
{
/* REG: set PC to the value in REG */
REG(PC) = REG(param1);
}
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
REG(SAR0.UINT32) = (address & 0xfffffffe);
}
static void i2c_reg_reset(i2c_t *obj) {
/* full reset */
REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on
REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on
REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack)
REG(SER.UINT8[0]) = 0x00; // no slave addr enabled
/* set frequency */
REG(MR1.UINT8[0]) |= obj->pclk_bit;
REG(BRL.UINT8[0]) = obj->width_low;
REG(BRH.UINT8[0]) = obj->width_hi;
REG(MR2.UINT8[0]) = 0x07;
REG(MR3.UINT8[0]) = 0x00;
REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT
REG(IER.UINT8[0]) = 0x00; // no interrupt
REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset
}
/*---------------------------------------------------------------------------*/
void
adc_init(void)
{
/* Start conversions only manually */
REG(SOC_ADC_ADCCON1) |= SOC_ADC_ADCCON1_STSEL;
}
/*---------------------------------------------------------------------------*/
int16_t
adc_get(uint8_t channel, uint8_t ref, uint8_t div)
{
uint32_t cctest_tr0, rfcore_xreg_atest;
int16_t res;
/* On-chip temperature sensor */
if(channel == SOC_ADC_ADCCON_CH_TEMP) {
/* Connect the temperature sensor to the ADC */
cctest_tr0 = REG(CCTEST_TR0);
REG(CCTEST_TR0) = cctest_tr0 | CCTEST_TR0_ADCTM;
/* Enable the temperature sensor */
rfcore_xreg_atest = REG(RFCORE_XREG_ATEST);
REG(RFCORE_XREG_ATEST) = (rfcore_xreg_atest & ~RFCORE_XREG_ATEST_ATEST_CTRL) |
RFCORE_XREG_ATEST_ATEST_CTRL_TEMP;
}
/* Start a single extra conversion with the given parameters */
REG(SOC_ADC_ADCCON3) = (REG(SOC_ADC_ADCCON3) &
~(SOC_ADC_ADCCON3_EREF | SOC_ADC_ADCCON3_EDIV | SOC_ADC_ADCCON3_ECH)) |
ref | div | channel;
/* Poll until end of conversion */
while(!(REG(SOC_ADC_ADCCON1) & SOC_ADC_ADCCON1_EOC));
/* Read conversion result, reading SOC_ADC_ADCH last to clear
* SOC_ADC_ADCCON1.EOC */
res = REG(SOC_ADC_ADCL) & 0xfc;
res |= REG(SOC_ADC_ADCH) << 8;
/* On-chip temperature sensor */
if(channel == SOC_ADC_ADCCON_CH_TEMP) {
/* Restore the initial temperature sensor state and connection (better for
* power consumption) */
REG(RFCORE_XREG_ATEST) = rfcore_xreg_atest;
REG(CCTEST_TR0) = cctest_tr0;
}
/* Return conversion result */
return res;
}
/**
* Write a uint32_t value to a memory address
*/
inline void write32(uint32_t address, uint32_t value)
{
REG(address) = value;
}
/**
* Read an uint32_t from a memory address
*/
inline uint32_t read32(uint32_t address)
{
return REG(address);
}
/*
* ======== PMI_readI2C ========
* Read a PMIC register via I2C.
*/
PMI_Status PMI_readI2C(unsigned addr, unsigned reg, unsigned * data)
{
unsigned status;
unsigned busy;
/* wait for any previously sent STOP to auto complete ...*/
do
{
busy = REG(ICMDR) & STP_BIT;
}
while (busy != 0);
/* wait for any in progress bus transaction to complete... */
do
{
busy = REG(ICSTR) & BUSY_BIT;
}
while (busy != 0);
/* set slave address to be the PMIC */
REG(ICSAR) = addr;
/* set transmit byte count (ICCNT) to one byte (i.e., PMIC register ID) */
REG(ICCNT) = 1;
/* set controller mode to be master transmit */
REG(ICMDR) |= (TRX_BIT | MST_BIT);
/* put the PMIC register ID into the transmit data register */
REG(ICDXR) = reg;
/* start the transaction */
REG(ICMDR) |= STT_BIT;
asm(" .global _PMI_waitR1");
asm("_PMI_waitR1:");
/* wait for TX ready status */
do
{
status = REG(ICSTR) & ICXRDY_BIT;
}
while (status == 0);
/* wait for ARDY to indicate new register access is OK */
do
{
status = REG(ICSTR) & ARDY_BIT;
}
while (status == 0);
/* set controller mode to receive */
REG(ICMDR) &= ~TRX_BIT;
/* re-assert master bit, indicate NACK reply to slave data byte */
REG(ICMDR) |= (MST_BIT | NACKMOD_BIT);
/* start the read operation */
REG(ICMDR) |= STT_BIT;
asm(" .global _PMI_waitR2");
asm("_PMI_waitR2:");
/* wait for RX ready status */
do
{
status = REG(ICSTR) & ICRRDY_BIT;
}
while (status == 0);
/* read the received byte */
*data = REG(ICDRR);
/* signal bus STOP */
REG(ICMDR) |= STP_BIT;
return(PMI_OK);
}
/*
* ======== PMI_initI2C ========
*/
PMI_Status PMI_initI2C(void)
{
unsigned busy;
unsigned temp;
/* setup C6748 PINMUX register to select I2C functionality */
temp = REG(PINMUX4);
REG(PINMUX4) = (temp & SELECT_I2C_MASK) | SELECT_I2C_VALUE;
/* put I2C into reset */
REG(ICMDR) &= ~IRS_BIT;
/* write initial config to I2C mode register */
REG(ICMDR) = MASTERCONFIG;
/* setup I2C clock frequency */
REG(ICPSC) = PRESCALEDIVIDE;
/* setup I2C clock divider registers */
REG(ICCLKL) = CLOCKDIVIDE_LO;
REG(ICCLKH) = CLOCKDIVIDE_HI;
/* write back to clear the interrupt status register */
REG(ICSTR) = REG(ICSTR);
/* release the I2C controller from reset */
REG(ICMDR) |= IRS_BIT;
/* wait until busy busy bit is cleared indicating bus is free */
do
{
busy = REG(ICSTR) & BUSY_BIT;
}
while (busy != 0);
return(PMI_OK);
}
/*
* ======== PMI_writeI2C ========
* Write a PMIC register via I2C.
*/
PMI_Status PMI_writeI2C(unsigned addr, unsigned reg, unsigned data)
{
unsigned status;
unsigned busy;
/* wait for any previously sent STOP to auto complete ...*/
do
{
busy = REG(ICMDR) & STP_BIT;
}
while (busy != 0);
/* wait for any previous bus transaction to complete... */
do
{
busy = REG(ICSTR) & BUSY_BIT;
}
while (busy != 0);
/* set slave address to be the PMIC */
REG(ICSAR) = addr;
/* set transmit byte count (ICCNT) to two bytes (register ID + value) */
REG(ICCNT) = 2;
/* set controller mode to master transmit */
REG(ICMDR) |= (TRX_BIT | MST_BIT);
/* put the PMIC register ID into the transmit data register */
REG(ICDXR) = reg;
/* start the transaction */
REG(ICMDR) |= STT_BIT;
asm(" .global _PMI_waitT1");
asm("_PMI_waitT1:");
/* wait for TX ready status */
do
{
status = REG(ICSTR) & ICXRDY_BIT;
}
while (status == 0);
/* put the PMIC register data value into the transmit data register */
REG(ICDXR) = data;
asm(" .global _PMI_waitT2");
asm("_PMI_waitT2:");
/* wait for TX ready status */
do
{
status = REG(ICSTR) & ICXRDY_BIT;
}
while (status == 0);
/* signal bus STOP */
REG(ICMDR) |= STP_BIT;
return(PMI_OK);
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int count = 0;
int status;
int value;
volatile uint32_t work_reg = 0;
if(length <= 0) {
return 0;
}
i2c_set_MR3_ACK(obj);
/* There is a STOP condition for last processing */
if (obj->last_stop_flag != 0) {
status = i2c_start(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_BUS_BUSY;
}
}
obj->last_stop_flag = stop;
/* Send Slave address */
status = i2c_read_address_write(obj, (address | 0x01));
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* wait RDRF */
status = i2c_wait_RDRF(obj);
/* check ACK/NACK */
if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
/* Slave sends NACK */
(void)i2c_set_STOP(obj);
/* dummy read */
value = REG(DRR.UINT32);
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
obj->last_stop_flag = 1;
return I2C_ERROR_NO_SLAVE;
}
/* Read in all except last byte */
if (length > 2) {
/* dummy read */
value = REG(DRR.UINT32);
for (count = 0; count < (length - 1); count++) {
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* Recieve the data */
if (count == (length - 2)) {
value = i2c_do_read(obj, 1);
} else if ((length >= 3) && (count == (length - 3))) {
value = i2c_do_read(obj, 2);
} else {
value = i2c_do_read(obj, 0);
}
data[count] = (char)value;
}
} else if (length == 2) {
/* Set MR3 WATI bit is 1 */
REG(MR3.UINT32) |= MR3_WAIT;
/* dummy read */
value = REG(DRR.UINT32);
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
i2c_set_MR3_NACK(obj);
data[count] = (char)REG(DRR.UINT32);
count++;
} else {
/* length == 1 */
/* Set MR3 WATI bit is 1 */;
REG(MR3.UINT32) |= MR3_WAIT;
i2c_set_MR3_NACK(obj);
/* dummy read */
value = REG(DRR.UINT32);
}
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* If not repeated start, send stop. */
if (stop) {
(void)i2c_set_STOP(obj);
/* RIICnDRR read */
value = (REG(DRR.UINT32) & 0xFF);
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
} else {
(void)i2c_restart(obj);
/* RIICnDRR read */
value = (REG(DRR.UINT32) & 0xFF);
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_START(obj);
/* SR2.START = 0 */
REG(SR2.UINT32) &= ~SR2_START;
}
return length;
}
void
orc_compiler_powerpc_register_rules (OrcTarget *target)
{
OrcRuleSet *rule_set;
rule_set = orc_rule_set_new (orc_opcode_set_get("sys"), target, 0);
#define REG(name) \
orc_rule_register (rule_set, #name , powerpc_rule_ ## name , NULL);
REG(addb);
REG(addssb);
REG(addusb);
REG(andb);
REG(avgsb);
REG(avgub);
REG(cmpeqb);
REG(cmpgtsb);
REG(maxsb);
REG(maxub);
REG(minsb);
REG(minub);
REG(orb);
REG(shlb);
REG(shrsb);
REG(shrub);
REG(subb);
REG(subssb);
REG(subusb);
REG(xorb);
REG(addw);
REG(addssw);
REG(addusw);
REG(andw);
REG(avgsw);
REG(avguw);
REG(cmpeqw);
REG(cmpgtsw);
REG(maxsw);
REG(maxuw);
REG(minsw);
REG(minuw);
REG(orw);
REG(shlw);
REG(shrsw);
REG(shruw);
REG(subw);
REG(subssw);
REG(subusw);
REG(xorw);
REG(addl);
REG(addssl);
REG(addusl);
REG(andl);
REG(avgsl);
REG(avgul);
REG(cmpeql);
REG(cmpgtsl);
REG(maxsl);
REG(maxul);
REG(minsl);
REG(minul);
REG(orl);
REG(shll);
REG(shrsl);
REG(shrul);
REG(subl);
REG(subssl);
REG(subusl);
REG(xorl);
REG(andq);
REG(orq);
REG(xorq);
REG(mullb);
REG(mulhsb);
REG(mulhub);
REG(mullw);
REG(mulhsw);
REG(mulhuw);
REG(convsbw);
REG(convswl);
REG(convubw);
REG(convuwl);
REG(convssswb);
REG(convssslw);
REG(convsuswb);
REG(convsuslw);
REG(convuuswb);
REG(convuuslw);
REG(convwb);
REG(convlw);
REG(mulsbw);
REG(mulubw);
REG(mulswl);
REG(muluwl);
REG(accw);
REG(accl);
REG(accsadubl);
REG(signb);
REG(signw);
REG(signl);
REG(select0wb);
REG(select1wb);
REG(select0lw);
REG(select1lw);
REG(select0ql);
REG(select1ql);
REG(mergebw);
REG(mergewl);
REG(mergelq);
REG(absb);
REG(absw);
REG(absl);
REG(splatw3q);
REG(splatbw);
REG(splatbl);
REG(convslq);
REG(convulq);
REG(convhwb);
REG(convhlw);
REG(convql);
REG(swapw);
REG(swapl);
REG(swapwl);
REG(swapq);
REG(swaplq);
if (0) REG(splitql);
REG(splitlw);
REG(splitwb);
REG(div255w);
REG(addf);
REG(subf);
REG(minf);
REG(maxf);
REG(cmpeqf);
REG(cmplef);
REG(cmpltf);
REG(mulf);
if (0) REG(divf); /* not accurate enough */
REG(convfl);
REG(convlf);
orc_rule_register (rule_set, "loadpb", powerpc_rule_loadpX, (void *)1);
orc_rule_register (rule_set, "loadpw", powerpc_rule_loadpX, (void *)2);
orc_rule_register (rule_set, "loadpl", powerpc_rule_loadpX, (void *)4);
orc_rule_register (rule_set, "loadb", powerpc_rule_loadX, NULL);
orc_rule_register (rule_set, "loadw", powerpc_rule_loadX, NULL);
orc_rule_register (rule_set, "loadl", powerpc_rule_loadX, NULL);
orc_rule_register (rule_set, "loadq", powerpc_rule_loadX, NULL);
orc_rule_register (rule_set, "loadoffb", powerpc_rule_loadoffX, NULL);
orc_rule_register (rule_set, "loadoffw", powerpc_rule_loadoffX, NULL);
orc_rule_register (rule_set, "loadoffl", powerpc_rule_loadoffX, NULL);
orc_rule_register (rule_set, "storeb", powerpc_rule_storeX, NULL);
orc_rule_register (rule_set, "storew", powerpc_rule_storeX, NULL);
orc_rule_register (rule_set, "storel", powerpc_rule_storeX, NULL);
orc_rule_register (rule_set, "storeq", powerpc_rule_storeX, NULL);
orc_rule_register (rule_set, "andnb", powerpc_rule_andnX, NULL);
orc_rule_register (rule_set, "andnw", powerpc_rule_andnX, NULL);
orc_rule_register (rule_set, "andnl", powerpc_rule_andnX, NULL);
orc_rule_register (rule_set, "andnq", powerpc_rule_andnX, NULL);
orc_rule_register (rule_set, "copyb", powerpc_rule_copyX, NULL);
orc_rule_register (rule_set, "copyw", powerpc_rule_copyX, NULL);
orc_rule_register (rule_set, "copyl", powerpc_rule_copyX, NULL);
orc_rule_register (rule_set, "copyq", powerpc_rule_copyX, NULL);
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
int cnt;
int status;
if(length <= 0) {
return 0;
}
/* There is a STOP condition for last processing */
if (obj->last_stop_flag != 0) {
status = i2c_start(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_BUS_BUSY;
}
}
obj->last_stop_flag = stop;
/* Send Slave address */
status = i2c_do_write(obj, address);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* Wait send end */
status = i2c_wait_TEND(obj);
if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
/* Slave sends NACK */
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* Send Write data */
for (cnt=0; cnt<length; cnt++) {
status = i2c_do_write(obj, data[cnt]);
if(status != 0) {
i2c_set_err_noslave(obj);
return cnt;
} else {
/* Wait send end */
status = i2c_wait_TEND(obj);
if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
/* Slave sends NACK */
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
}
}
/* If not repeated start, send stop. */
if (stop) {
(void)i2c_set_STOP(obj);
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
} else {
(void)i2c_restart(obj);
(void)i2c_wait_START(obj);
/* SR2.START = 0 */
REG(SR2.UINT32) &= ~SR2_START;
}
return length;
}
Controller::Controller(PatchLibrary *l,Responder *s){
commandct=0;
server=s;
library=l;
REG("test",0,Test);
REG("startcomps",0,StartComps);
REG("nextcomp",0,NextComp);
REG("compinnm",1,CompInName);
REG("compoutnm",1,CompOutName);
REG("compparam",1,CompParam); // paramidx
REG("compenum",2,CompEnum); // paramidx enumidx
REG("contype",1,ConType); // typeidx
REG("die",0,Die);
REG("clear",0,Clear);
REG("np",1,NewPatch); // patchid
REG("dp",1,DelPatch); // patchid
REG("sra",4,SetRunAlways); // patchid componentid outputidx y/n
REG("nc",3,NewComponent); // patchid componentid type
REG("dc",2,DeleteComponent); // patchid componentid
REG("lc",5,LinkComponent); // patchid incomponentid input outcomponentid output
REG("ui",3,UnlinkComponentInput); // patchid componentid input
REG("uo",3,UnlinkComponentOutput); // patchid componentid output
REG("p",5,ParamSet); // patchid componentid paramid code encval
REG("pss",5,ParamSetStoredString); // patchid componentid paramid code stringno
REG("run",1,RunPatch); // patchid
REG("db",2,DebugComp); // patchid componentid
}
static inline int i2c_status(i2c_t *obj) {
return REG(SR2.UINT8[0]);
}
/* RAM size is stored in CPC0_RGBAN1
*/
u32 pcippc2_sdram_size (void)
{
return in32 (REG (CPC0, RGBAN1));
}
int main(int argc, char *argv[])
{
enum __ptrace_request restart_how;
int last_exit_status = -1;
pid_t *pids = NULL;
long status;
int signal;
pid_t pid;
if (argc <= 1) {
fprintf(stderr, "Usage: %s /path/to/exe [args]\n", argv[0]);
exit(EXIT_FAILURE);
}
pid = fork();
switch(pid) {
case -1:
perror("fork()");
exit(EXIT_FAILURE);
case 0: /* child */
status = ptrace(PTRACE_TRACEME, 0, NULL, NULL);
if (status < 0) {
perror("ptrace(TRACEME)");
exit(EXIT_FAILURE);
}
/* Synchronize with the tracer's event loop. */
kill(getpid(), SIGSTOP);
execvp(argv[1], &argv[1]);
exit(EXIT_FAILURE);
default: /* parent */
break;
}
restart_how = (getenv("PTRACER_BEHAVIOR_1") == NULL
? PTRACE_SYSCALL
: PTRACE_CONT);
pids = calloc(1, sizeof(pid_t));
if (pids == NULL) {
perror("calloc()");
exit(EXIT_FAILURE);
}
signal = 0;
while (1) {
int tracee_status;
pid_t pid;
pid_t sid;
int i;
/* Wait for the next tracee's stop. */
pid = waitpid(-1, &tracee_status, __WALL);
if (pid < 0) {
perror("waitpid()");
if (errno != ECHILD)
exit(EXIT_FAILURE);
break;
}
sid = 0;
for (i = 0; pids[i] != 0; i++) {
if (pid == pids[i]) {
sid = i + 1;
break;
}
}
if (sid == 0) {
pids = realloc(pids, (i + 1 + 1) * sizeof(pid_t));
if (pids == NULL) {
perror("realloc()");
exit(EXIT_FAILURE);
}
pids[i + 1] = 0;
pids[i] = pid;
sid = i + 1;
fprintf(stderr, "sid %d -> pid %d\n", sid, pid);
}
if (WIFEXITED(tracee_status)) {
fprintf(stderr, "sid %d: exited with status %d\n",
sid, WEXITSTATUS(tracee_status));
last_exit_status = WEXITSTATUS(tracee_status);
continue; /* Skip the call to ptrace(SYSCALL). */
}
else if (WIFSIGNALED(tracee_status)) {
fprintf(stderr, "sid %d: terminated with signal %d\n",
sid, WTERMSIG(tracee_status));
continue; /* Skip the call to ptrace(SYSCALL). */
}
else if (WIFCONTINUED(tracee_status)) {
fprintf(stderr, "sid %d: continued\n", sid);
signal = SIGCONT;
}
else if (WIFSTOPPED(tracee_status)) {
struct user_regs_struct regs;
/* Don't use WSTOPSIG() to extract the signal
* since it clears the PTRACE_EVENT_* bits. */
signal = (tracee_status & 0xfff00) >> 8;
switch (signal) {
static bool skip_bare_sigtrap = false;
long ptrace_options;
case SIGTRAP:
fprintf(stderr, "sid %d: SIGTRAP\n", sid);
status = ptrace(PTRACE_GETREGS, pid, NULL, ®s);
if (status < 0) {
fprintf(stderr,
"sigtrap: ?, ?\n");
} else {
fprintf(stderr, "sigtrap: %ld == 0 ? %d\n",
REG(regs, SYSARG_NUM),
REG(regs, SYSARG_RESULT) == 0);
}
/* PTRACER_BEHAVIOR_1 */
if (restart_how != PTRACE_SYSCALL) {
restart_how = PTRACE_SYSCALL;
signal = 0;
break;
}
/* Distinguish some events from others and
* automatically trace each new process with
* the same options.
*
* Note that only the first bare SIGTRAP is
* related to the tracing loop, others SIGTRAP
* carry tracing information because of
* TRACE*FORK/CLONE/EXEC.
*/
if (skip_bare_sigtrap) {
signal = 0;
break;
}
skip_bare_sigtrap = true;
ptrace_options = PTRACE_O_TRACESYSGOOD
| PTRACE_O_TRACEFORK
| PTRACE_O_TRACEVFORK
| PTRACE_O_TRACEVFORKDONE
| PTRACE_O_TRACECLONE
| PTRACE_O_TRACEEXIT;
if (getenv("PTRACER_BEHAVIOR_2") == NULL)
ptrace_options |= PTRACE_O_TRACEEXEC;
status = ptrace(PTRACE_SETOPTIONS, pid, NULL, ptrace_options);
if (status < 0) {
perror("ptrace(PTRACE_SETOPTIONS)");
exit(EXIT_FAILURE);
}
/* Fall through. */
case SIGTRAP | 0x80:
fprintf(stderr, "sid %d: PTRACE_EVENT_SYSGOOD\n", sid);
signal = 0;
status = ptrace(PTRACE_GETREGS, pid, NULL, ®s);
if (status < 0) {
fprintf(stderr,
"syscall(?) = ?\n");
} else {
fprintf(stderr, "syscall(%ld) == 0 ? %d\n",
REG(regs, SYSARG_NUM),
REG(regs, SYSARG_RESULT) == 0);
}
break;
case SIGTRAP | PTRACE_EVENT_VFORK << 8:
fprintf(stderr, "sid %d: PTRACE_EVENT_VFORK\n", sid);
signal = 0;
break;
case SIGTRAP | PTRACE_EVENT_VFORK_DONE << 8:
fprintf(stderr, "sid %d: PTRACE_EVENT_VFORK\n", sid);
signal = 0;
break;
case SIGTRAP | PTRACE_EVENT_FORK << 8:
fprintf(stderr, "sid %d: PTRACE_EVENT_FORK\n", sid);
signal = 0;
break;
case SIGTRAP | PTRACE_EVENT_CLONE << 8:
fprintf(stderr, "sid %d: PTRACE_EVENT_CLONE\n", sid);
signal = 0;
break;
case SIGTRAP | PTRACE_EVENT_EXEC << 8:
fprintf(stderr, "sid %d: PTRACE_EVENT_EXEC\n", sid);
signal = 0;
break;
case SIGTRAP | PTRACE_EVENT_EXIT << 8:
fprintf(stderr, "sid %d: PTRACE_EVENT_EXIT\n", sid);
signal = 0;
break;
case SIGSTOP:
fprintf(stderr, "sid %d: SIGSTOP\n", sid);
signal = 0;
break;
default:
break;
}
}
else {
fprintf(stderr, "sid %d: unknown trace event\n", sid);
signal = 0;
}
/* Restart the tracee and stop it at the next entry or
* exit of a system call. */
status = ptrace(restart_how, pid, NULL, signal);
if (status < 0)
fprintf(stderr, "ptrace(<restart_how>, %d, %d): %s\n", sid, signal, strerror(errno));
}
int board_early_init_f (void)
{
out32 (REG (CPC0, RSTR), 0xC0000000);
iobarrier_rw ();
out32 (REG (CPC0, RSTR), 0xF0000000);
iobarrier_rw ();
out32 (REG (CPC0, UCTL), 0x00F80000);
out32 (REG (CPC0, SIOC0), 0x30000000);
out32 (REG (CPC0, ABCNTL), 0x00000000);
out32 (REG (CPC0, SESR), 0x00000000);
out32 (REG (CPC0, SEAR), 0x00000000);
/* Detect IBM Avignon CPC710 Revision */
if ((in32 (REG (CPC0, UCTL)) & 0x000000F0) == CPC710_TYPE_100P)
out32 (REG (CPC0, PGCHP), 0xA0000040);
else
out32 (REG (CPC0, PGCHP), 0x80800040);
out32 (REG (CPC0, ATAS), 0x709C2508);
iobarrier_rw ();
return 0;
}
inline void vm_JMP_IMM(int32_t param1, int32_t unused param2)
{
/* IMM: set PC to IMM */
REG(PC) = param1;
}
static int tegra20_spdif_show(struct seq_file *s, void *unused)
{
#define REG(r) { r, #r }
static const struct {
int offset;
const char *name;
} regs[] = {
REG(TEGRA20_SPDIF_CTRL),
REG(TEGRA20_SPDIF_STATUS),
REG(TEGRA20_SPDIF_STROBE_CTRL),
REG(TEGRA20_SPDIF_DATA_FIFO_CSR),
REG(TEGRA20_SPDIF_CH_STA_RX_A),
REG(TEGRA20_SPDIF_CH_STA_RX_B),
REG(TEGRA20_SPDIF_CH_STA_RX_C),
REG(TEGRA20_SPDIF_CH_STA_RX_D),
REG(TEGRA20_SPDIF_CH_STA_RX_E),
REG(TEGRA20_SPDIF_CH_STA_RX_F),
REG(TEGRA20_SPDIF_CH_STA_TX_A),
REG(TEGRA20_SPDIF_CH_STA_TX_B),
REG(TEGRA20_SPDIF_CH_STA_TX_C),
REG(TEGRA20_SPDIF_CH_STA_TX_D),
REG(TEGRA20_SPDIF_CH_STA_TX_E),
REG(TEGRA20_SPDIF_CH_STA_TX_F),
};
#undef REG
struct tegra20_spdif *spdif = s->private;
int i;
for (i = 0; i < ARRAY_SIZE(regs); i++) {
u32 val = tegra20_spdif_read(spdif, regs[i].offset);
seq_printf(s, "%s = %08x\n", regs[i].name, val);
}
return 0;
}
VOID ThreadStart(THREADID tid, CONTEXT *ctxt, int flags, VOID *v)
{
for (UINT32 r = 0; r <= 9; r++)
PIN_SetContextReg(ctxt, REG(REG_INST_G0 + r), BaseValue + tid + r);
}
static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) {
/* SR2.NACKF = 0 */
REG(SR2.UINT32) &= ~SR2_NACKF;
/* SR2.STOP = 0 */
REG(SR2.UINT32) &= ~SR2_STOP;
}
/**
* Hardware PHY reset.
*
* Sets all PHY registers to their initial values.
*/
void Phy::hardReset(PPHY pPhy)
{
PhyLog(("PHY#%d Hard reset\n", pPhy->iInstance));
REG(PCTRL) = PCTRL_SPDSELM | PCTRL_DUPMOD | PCTRL_ANEG;
/*
* 100 and 10 FD/HD, MF Preamble Suppression, Auto-Negotiation Complete,
* AUTO NEG AB, EXT CAP
*/
REG(PSTATUS) = (REG(PSTATUS) & ~PSTATUS_LNKSTAT) | 0x7969;
REG(ANA) = 0x01E1;
/* No flow control by our link partner, all speeds */
REG(LPA) = 0x01E0;
REG(ANE) = 0x0000;
REG(NPT) = 0x2001;
REG(LPN) = 0x0000;
REG(GCON) = 0x1E00;
REG(GSTATUS) = 0x0000;
REG(EPSTATUS) = 0x3000;
REG(PSCON) = 0x0068;
REG(PSSTAT) = 0x0000;
REG(PINTE) = 0x0000;
REG(PINTS) = 0x0000;
REG(EPSCON1) = 0x0D60;
REG(PREC) = 0x0000;
REG(EPSCON2) = 0x000C;
REG(R30PS) = 0x0000;
REG(R30AW) = 0x0000;
pPhy->u16State = MDIO_IDLE;
}
static void i2c_set_MR3_ACK(i2c_t *obj) {
/* send a ACK */
REG(MR3.UINT32) |= MR3_ACKWP;
REG(MR3.UINT32) &= ~MR3_ACKBT;
REG(MR3.UINT32) &= ~MR3_ACKWP;
}
static void dce_disable_sram_shut_down(struct dce_hwseq *hws)
{
if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,
DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
}
/**
* rmii_hw_init
*
* DA850/OMAP-L138 EVM can interface to a daughter card for
* additional features. This card has an I2C GPIO Expander TCA6416
* to select the required functions like camera, RMII Ethernet,
* character LCD, video.
*
* Initialization of the expander involves configuring the
* polarity and direction of the ports. P07-P05 are used here.
* These ports are connected to a Mux chip which enables only one
* functionality at a time.
*
* For RMII phy to respond, the MII MDIO clock has to be disabled
* since both the PHY devices have address as zero. The MII MDIO
* clock is controlled via GPIO2[6].
*
* This code is valid for Beta version of the hardware
*/
int rmii_hw_init(void)
{
const struct pinmux_config gpio_pins[] = {
{ pinmux(6), 8, 1 }
};
u_int8_t buf[2];
unsigned int temp;
int ret;
/* PinMux for GPIO */
if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
return 1;
/* I2C Exapnder configuration */
/* Set polarity to non-inverted */
buf[0] = 0x0;
buf[1] = 0x0;
ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
if (ret) {
printf("\nExpander @ 0x%02x write FAILED!!!\n",
CONFIG_SYS_I2C_EXPANDER_ADDR);
return ret;
}
/* Configure P07-P05 as outputs */
buf[0] = 0x1f;
buf[1] = 0xff;
ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
if (ret) {
printf("\nExpander @ 0x%02x write FAILED!!!\n",
CONFIG_SYS_I2C_EXPANDER_ADDR);
}
/* For Ethernet RMII selection
* P07(SelA)=0
* P06(SelB)=1
* P05(SelC)=1
*/
if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
printf("\nExpander @ 0x%02x read FAILED!!!\n",
CONFIG_SYS_I2C_EXPANDER_ADDR);
}
buf[0] &= 0x1f;
buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
printf("\nExpander @ 0x%02x write FAILED!!!\n",
CONFIG_SYS_I2C_EXPANDER_ADDR);
}
/* Set the output as high */
temp = REG(GPIO_BANK2_REG_SET_ADDR);
temp |= (0x01 << 6);
REG(GPIO_BANK2_REG_SET_ADDR) = temp;
/* Set the GPIO direction as output */
temp = REG(GPIO_BANK2_REG_DIR_ADDR);
temp &= ~(0x01 << 6);
REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
return 0;
}
