int psb_poll_mtx_irq(struct drm_psb_private *dev_priv) { int ret = 0; uint32_t mtx_int = 0; REGIO_WRITE_FIELD_LITE(mtx_int, MSVDX_INTERRUPT_STATUS, CR_MTX_IRQ, 1); ret = psb_wait_for_register(dev_priv, MSVDX_INTERRUPT_STATUS, /* Required value */ mtx_int, /* Enabled bits */ mtx_int, 10000, 100); if (ret) { DRM_ERROR("MSVDX: Error Mtx did not return" " int within a resonable time\n"); return ret; } PSB_DEBUG_IRQ("MSVDX: Got MTX Int\n"); /* Got it so clear the bit */ PSB_WMSVDX32(mtx_int, MSVDX_INTERRUPT_CLEAR); return ret; }
void psb_irq_postinstall(struct drm_device *dev) { struct drm_psb_private *dev_priv = (struct drm_psb_private *)dev->dev_private; unsigned long irqflags; spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); PSB_WSGX32(dev_priv->sgx2_irq_mask, PSB_CR_EVENT_HOST_ENABLE2); PSB_WSGX32(dev_priv->sgx_irq_mask, PSB_CR_EVENT_HOST_ENABLE); (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /****MSVDX IRQ Setup...*****/ /* Enable Mtx Interupt to host */ { unsigned long enables = 0; PSB_DEBUG_GENERAL("Setting up MSVDX IRQs.....\n"); REGIO_WRITE_FIELD_LITE(enables, MSVDX_INTERRUPT_STATUS, CR_MTX_IRQ, 1); PSB_WMSVDX32(enables, MSVDX_HOST_INTERRUPT_ENABLE); } dev_priv->irq_enabled = 1; uint32_t hotplug_stat = PSB_RVDC32(PORT_HOTPLUG_ENABLE_REG); PSB_WVDC32(hotplug_stat | SDVOB_HOTPLUG_DETECT_ENABLE, PORT_HOTPLUG_ENABLE_REG); spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); }
void psb_upload_fw (struct drm_psb_private *dev_priv, const uint32_t ui32DataMem, uint32_t ui32RamBankSize, uint32_t ui32Address, const unsigned int uiWords, const uint32_t * const pui32Data) { uint32_t ui32Loop, ui32Ctrl, ui32RamId, ui32Addr, ui32CurrBank = (uint32_t) ~ 0; uint32_t ui32AccessControl; /* Save the access control register... */ ui32AccessControl = PSB_RMSVDX32 (MSVDX_MTX_RAM_ACCESS_CONTROL); /* Wait for MCMSTAT to become be idle 1 */ psb_wait_for_register (dev_priv, MSVDX_MTX_RAM_ACCESS_STATUS, 1, /* Required Value */ 0xffffffff /* Enables */ ); for (ui32Loop = 0; ui32Loop < uiWords; ui32Loop++) { ui32RamId = ui32DataMem + (ui32Address / ui32RamBankSize); if (ui32RamId != ui32CurrBank) { ui32Addr = ui32Address >> 2; ui32Ctrl = 0; REGIO_WRITE_FIELD_LITE (ui32Ctrl, MSVDX_MTX_RAM_ACCESS_CONTROL, MTX_MCMID, ui32RamId); REGIO_WRITE_FIELD_LITE (ui32Ctrl, MSVDX_MTX_RAM_ACCESS_CONTROL, MTX_MCM_ADDR, ui32Addr); REGIO_WRITE_FIELD_LITE (ui32Ctrl, MSVDX_MTX_RAM_ACCESS_CONTROL, MTX_MCMAI, 1); PSB_WMSVDX32 (ui32Ctrl, MSVDX_MTX_RAM_ACCESS_CONTROL); ui32CurrBank = ui32RamId; } ui32Address += 4; PSB_WMSVDX32 (pui32Data[ui32Loop], MSVDX_MTX_RAM_ACCESS_DATA_TRANSFER); /* Wait for MCMSTAT to become be idle 1 */ psb_wait_for_register (dev_priv, MSVDX_MTX_RAM_ACCESS_STATUS, 1, /* Required Value */ 0xffffffff /* Enables */ ); }
static void msvdx_upload_fw(struct drm_psb_private *dev_priv, const uint32_t data_mem, uint32_t ram_bank_size, uint32_t address, const unsigned int words, const uint32_t * const data) { uint32_t loop, ctrl, ram_id, addr, cur_bank = (uint32_t) ~0; uint32_t access_ctrl; PSB_DEBUG_GENERAL("MSVDX: Upload firmware by register interface\n"); /* Save the access control register... */ access_ctrl = PSB_RMSVDX32(MTX_RAM_ACCESS_CONTROL_OFFSET); /* Wait for MCMSTAT to become be idle 1 */ psb_wait_for_register(dev_priv, MTX_RAM_ACCESS_STATUS_OFFSET, 1, /* Required Value */ 0xffffffff, /* Enables */ 2000000, 5); for (loop = 0; loop < words; loop++) { ram_id = data_mem + (address / ram_bank_size); if (ram_id != cur_bank) { addr = address >> 2; ctrl = 0; REGIO_WRITE_FIELD_LITE(ctrl, MTX_RAM_ACCESS_CONTROL, MTX_MCMID, ram_id); REGIO_WRITE_FIELD_LITE(ctrl, MTX_RAM_ACCESS_CONTROL, MTX_MCM_ADDR, addr); REGIO_WRITE_FIELD_LITE(ctrl, MTX_RAM_ACCESS_CONTROL, MTX_MCMAI, 1); PSB_WMSVDX32(ctrl, MTX_RAM_ACCESS_CONTROL_OFFSET); cur_bank = ram_id; } address += 4; PSB_WMSVDX32(data[loop], MTX_RAM_ACCESS_DATA_TRANSFER_OFFSET); /* Wait for MCMSTAT to become be idle 1 */ psb_wait_for_register(dev_priv, MTX_RAM_ACCESS_STATUS_OFFSET, 1, /* Required Value */ 0xffffffff, /* Enables */ 2000000, 5); }
void psb_msvdx_irq_postinstall(struct drm_psb_private *dev_priv) { /* Enable Mtx Interupt to host */ unsigned long enables = 0; PSB_DEBUG_GENERAL("Setting up MSVDX IRQs.....\n"); REGIO_WRITE_FIELD_LITE(enables, MSVDX_INTERRUPT_STATUS, CR_MTX_IRQ, 1); PSB_WMSVDX32(enables, MSVDX_HOST_INTERRUPT_ENABLE); }
void psb_msvdx_irq_preinstall(struct drm_psb_private *dev_priv) { unsigned long mtx_int = 0; dev_priv->vdc_irq_mask |= _PSB_IRQ_MSVDX_FLAG; /*Clear MTX interrupt */ REGIO_WRITE_FIELD_LITE(mtx_int, MSVDX_INTERRUPT_STATUS, CR_MTX_IRQ, 1); PSB_WMSVDX32(mtx_int, MSVDX_INTERRUPT_CLEAR); }
void psb_write_mtx_core_reg(struct drm_psb_private *dev_priv, const uint32_t core_reg, const uint32_t val) { uint32_t reg = 0; /* Put data in MTX_RW_DATA */ PSB_WMSVDX32(val, MSVDX_MTX_REGISTER_READ_WRITE_DATA); /* DREADY is set to 0 and request a write */ reg = core_reg; REGIO_WRITE_FIELD_LITE(reg, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST, MTX_RNW, 0); REGIO_WRITE_FIELD_LITE(reg, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST, MTX_DREADY, 0); PSB_WMSVDX32(reg, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST); psb_wait_for_register(dev_priv, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK); }
void psb_write_mtx_core_reg (struct drm_psb_private *dev_priv, const uint32_t ui32CoreRegister, const uint32_t ui32Val) { uint32_t ui32Reg = 0; /* Put data in MTX_RW_DATA */ PSB_WMSVDX32 (ui32Val, MSVDX_MTX_REGISTER_READ_WRITE_DATA); /* DREADY is set to 0 and request a write */ ui32Reg = ui32CoreRegister; REGIO_WRITE_FIELD_LITE (ui32Reg, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST, MTX_RNW, 0); REGIO_WRITE_FIELD_LITE (ui32Reg, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST, MTX_DREADY, 0); PSB_WMSVDX32 (ui32Reg, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST); psb_wait_for_register (dev_priv, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST, MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK, /* Required Value */ MSVDX_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK); }
static void tng__JPEG_set_ent_dec(context_JPEG_p ctx) { psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; uint32_t reg_value; psb_cmdbuf_reg_start_block(cmdbuf, 0); reg_value = 0; REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_ENTDEC_FE_CONTROL, ENTDEC_FE_MODE, 0 ); psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC, CR_VEC_ENTDEC_FE_CONTROL ), reg_value); psb_cmdbuf_reg_end_block(cmdbuf); psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET( MSVDX_VEC, CR_VEC_ENTDEC_BE_CONTROL )); reg_value = 0; REGIO_WRITE_FIELD(reg_value, MSVDX_VEC, CR_VEC_ENTDEC_BE_CONTROL, ENTDEC_BE_MODE, 0); psb_cmdbuf_rendec_write(cmdbuf, reg_value); psb_cmdbuf_rendec_end(cmdbuf); }
void psb_irq_preinstall(struct drm_device *dev) { struct drm_psb_private *dev_priv = (struct drm_psb_private *)dev->dev_private; spin_lock(&dev_priv->irqmask_lock); PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); PSB_WVDC32(0x00000000, PSB_INT_MASK_R); PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R); PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE); (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); dev_priv->sgx_irq_mask = _PSB_CE_PIXELBE_END_RENDER | _PSB_CE_DPM_3D_MEM_FREE | _PSB_CE_TA_FINISHED | _PSB_CE_DPM_REACHED_MEM_THRESH | _PSB_CE_DPM_OUT_OF_MEMORY_GBL | _PSB_CE_DPM_OUT_OF_MEMORY_MT | _PSB_CE_TA_TERMINATE | _PSB_CE_SW_EVENT; dev_priv->sgx2_irq_mask = _PSB_CE2_BIF_REQUESTER_FAULT; dev_priv->vdc_irq_mask = _PSB_IRQ_SGX_FLAG | _PSB_IRQ_MSVDX_FLAG | _PSB_HOTPLUG_INTERRUPT_ENABLE; if (!drm_psb_disable_vsync || drm_psb_detear) dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG | _PSB_VSYNC_PIPEB_FLAG; /*Clear MTX interrupt */ { unsigned long mtx_int = 0; REGIO_WRITE_FIELD_LITE(mtx_int, MSVDX_INTERRUPT_STATUS, CR_MTX_IRQ, 1); PSB_WMSVDX32(mtx_int, MSVDX_INTERRUPT_CLEAR); } spin_unlock(&dev_priv->irqmask_lock); }
/* Programme the Alt output if there is a rotation*/ void vld_dec_setup_alternative_frame(object_context_p obj_context) { uint32_t cmd = 0; psb_cmdbuf_p cmdbuf = obj_context->cmdbuf; context_DEC_p ctx = (context_DEC_p) obj_context->format_data; psb_surface_p src_surface = obj_context->current_render_target->psb_surface; psb_surface_p out_loop_surface = obj_context->current_render_target->out_loop_surface; int ved_scaling = (CONTEXT_SCALING(obj_context) && !ctx->yuv_ctx); /* In VPP ctx, current_render_target is rotated surface */ if (ctx->yuv_ctx && (VAEntrypointVideoProc == obj_context->entry_point)) { drv_debug_msg(VIDEO_DEBUG_GENERAL, "Setup second-pass rotation\n"); out_loop_surface = src_surface; src_surface = ctx->yuv_ctx->src_surface; } if (CONTEXT_ALTERNATIVE_OUTPUT(obj_context) || obj_context->entry_point == VAEntrypointVideoProc) { if (ved_scaling) { out_loop_surface = obj_context->current_render_target->scaling_surface; #ifndef BAYTRAIL tng_ved_write_scale_reg(obj_context); REGIO_WRITE_FIELD_LITE(cmd, MSVDX_CMDS,ALTERNATIVE_OUTPUT_PICTURE_ROTATION, SCALE_INPUT_SIZE_SEL, 1); REGIO_WRITE_FIELD_LITE(cmd, MSVDX_CMDS,ALTERNATIVE_OUTPUT_PICTURE_ROTATION, SCALE_ENABLE, 1); #endif } if (out_loop_surface == NULL) { drv_debug_msg(VIDEO_DEBUG_GENERAL, "out-loop surface is NULL, abort msvdx alternative output\n"); return; } if (GET_SURFACE_INFO_rotate(out_loop_surface) != obj_context->msvdx_rotate && !ved_scaling) drv_debug_msg(VIDEO_DEBUG_WARNING, "Display rotate mode does not match surface rotate mode!\n"); /* CRendecBlock RendecBlk( mCtrlAlloc , RENDEC_REGISTER_OFFSET(MSVDX_CMDS, VC1_LUMA_RANGE_MAPPING_BASE_ADDRESS) ); */ psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, VC1_LUMA_RANGE_MAPPING_BASE_ADDRESS)); psb_cmdbuf_rendec_write_address(cmdbuf, &out_loop_surface->buf, out_loop_surface->buf.buffer_ofs); psb_cmdbuf_rendec_write_address(cmdbuf, &out_loop_surface->buf, out_loop_surface->buf.buffer_ofs + out_loop_surface->chroma_offset); psb_cmdbuf_rendec_end(cmdbuf); REGIO_WRITE_FIELD_LITE(cmd, MSVDX_CMDS, ALTERNATIVE_OUTPUT_PICTURE_ROTATION , ALT_PICTURE_ENABLE, 1); REGIO_WRITE_FIELD_LITE(cmd, MSVDX_CMDS, ALTERNATIVE_OUTPUT_PICTURE_ROTATION , ROTATION_ROW_STRIDE, out_loop_surface->stride_mode); REGIO_WRITE_FIELD_LITE(cmd, MSVDX_CMDS, ALTERNATIVE_OUTPUT_PICTURE_ROTATION , RECON_WRITE_DISABLE, 0); /* FIXME Always generate Rec */ REGIO_WRITE_FIELD_LITE(cmd, MSVDX_CMDS, ALTERNATIVE_OUTPUT_PICTURE_ROTATION , ROTATION_MODE, GET_SURFACE_INFO_rotate(out_loop_surface)); RELOC(*ctx->p_range_mapping_base0, out_loop_surface->buf.buffer_ofs, &out_loop_surface->buf); RELOC(*ctx->p_range_mapping_base1, out_loop_surface->buf.buffer_ofs + out_loop_surface->chroma_offset, &out_loop_surface->buf); } if (obj_context->profile == VAProfileVP8Version0_3 || obj_context->profile == VAProfileJPEGBaseline || ctx->yuv_ctx) { psb_cmdbuf_rendec_start(cmdbuf, (REG_MSVDX_CMD_OFFSET + MSVDX_CMDS_AUX_LINE_BUFFER_BASE_ADDRESS_OFFSET)); psb_cmdbuf_rendec_write_address(cmdbuf, &ctx->aux_line_buffer_vld, ctx->aux_line_buffer_vld.buffer_ofs); psb_cmdbuf_rendec_end(cmdbuf); REGIO_WRITE_FIELD_LITE(cmd, MSVDX_CMDS, ALTERNATIVE_OUTPUT_PICTURE_ROTATION, USE_AUX_LINE_BUF, 1); if (ctx->yuv_ctx) REGIO_WRITE_FIELD_LITE(cmd, MSVDX_CMDS, ALTERNATIVE_OUTPUT_PICTURE_ROTATION , RECON_WRITE_DISABLE, 1); } /* Set the rotation registers */ psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, ALTERNATIVE_OUTPUT_PICTURE_ROTATION)); psb_cmdbuf_rendec_write(cmdbuf, cmd); *ctx->alt_output_flags = cmd; cmd = 0; REGIO_WRITE_FIELD_LITE(cmd, MSVDX_CMDS, EXTENDED_ROW_STRIDE, EXT_ROW_STRIDE, src_surface->stride / 64); psb_cmdbuf_rendec_write(cmdbuf, cmd); psb_cmdbuf_rendec_end(cmdbuf); }
static void msvdx_upload_fw(struct drm_psb_private *dev_priv, uint32_t address, const unsigned int words, int fw_sel) { uint32_t reg_val = 0; uint32_t cmd; uint32_t uCountReg, offset, mmu_ptd; uint32_t size = (words * 4); /* byte count */ uint32_t dma_channel = 0; /* Setup a Simple DMA for Ch0 */ struct msvdx_private *msvdx_priv = dev_priv->msvdx_private; PSB_DEBUG_GENERAL("MSVDX: Upload firmware by DMA\n"); msvdx_get_mtx_control_from_dash(dev_priv); /* dma transfers to/from the mtx have to be 32-bit aligned and in multiples of 32 bits */ PSB_WMSVDX32(address, MTX_SYSC_CDMAA_OFFSET); REGIO_WRITE_FIELD_LITE(reg_val, MTX_SYSC_CDMAC, BURSTSIZE, 4); /* burst size in multiples of 64 bits (allowed values are 2 or 4) */ REGIO_WRITE_FIELD_LITE(reg_val, MTX_SYSC_CDMAC, RNW, 0); /* false means write to mtx mem, true means read from mtx mem */ REGIO_WRITE_FIELD_LITE(reg_val, MTX_SYSC_CDMAC, ENABLE, 1); /* begin transfer */ REGIO_WRITE_FIELD_LITE(reg_val, MTX_SYSC_CDMAC, LENGTH, words); /* This specifies the transfer size of the DMA operation in terms of 32-bit words */ PSB_WMSVDX32(reg_val, MTX_SYSC_CDMAC_OFFSET); /* toggle channel 0 usage between mtx and other msvdx peripherals */ { reg_val = PSB_RMSVDX32(MSVDX_CONTROL_OFFSET); REGIO_WRITE_FIELD(reg_val, MSVDX_CONTROL, DMAC_CH0_SELECT, 0); PSB_WMSVDX32(reg_val, MSVDX_CONTROL_OFFSET); } /* Clear the DMAC Stats */ PSB_WMSVDX32(0 , DMAC_DMAC_IRQ_STAT_OFFSET + dma_channel); offset = msvdx_priv->fw->offset; if (fw_sel) offset += ((msvdx_priv->mtx_mem_size + 8192) & ~0xfff); /* use bank 0 */ cmd = 0; PSB_WMSVDX32(cmd, MSVDX_MMU_BANK_INDEX_OFFSET); /* Write PTD to mmu base 0*/ mmu_ptd = psb_get_default_pd_addr(dev_priv->mmu); PSB_WMSVDX32(mmu_ptd, MSVDX_MMU_DIR_LIST_BASE_OFFSET + 0); /* Invalidate */ reg_val = PSB_RMSVDX32(MSVDX_MMU_CONTROL0_OFFSET); reg_val &= ~0xf; REGIO_WRITE_FIELD(reg_val, MSVDX_MMU_CONTROL0, MMU_INVALDC, 1); PSB_WMSVDX32(reg_val, MSVDX_MMU_CONTROL0_OFFSET); PSB_WMSVDX32(offset, DMAC_DMAC_SETUP_OFFSET + dma_channel); /* Only use a single dma - assert that this is valid */ if ((size / 4) >= (1 << 15)) { DRM_ERROR("psb: DMA size beyond limited, aboart firmware uploading\n"); return; } uCountReg = PSB_DMAC_VALUE_COUNT(PSB_DMAC_BSWAP_NO_SWAP, 0, /* 32 bits */ PSB_DMAC_DIR_MEM_TO_PERIPH, 0, (size / 4)); /* Set the number of bytes to dma*/ PSB_WMSVDX32(uCountReg, DMAC_DMAC_COUNT_OFFSET + dma_channel); cmd = PSB_DMAC_VALUE_PERIPH_PARAM(PSB_DMAC_ACC_DEL_0, PSB_DMAC_INCR_OFF, PSB_DMAC_BURST_2); PSB_WMSVDX32(cmd, DMAC_DMAC_PERIPH_OFFSET + dma_channel); /* Set destination port for dma */ cmd = 0; REGIO_WRITE_FIELD(cmd, DMAC_DMAC_PERIPHERAL_ADDR, ADDR, MTX_SYSC_CDMAT_OFFSET); PSB_WMSVDX32(cmd, DMAC_DMAC_PERIPHERAL_ADDR_OFFSET + dma_channel); /* Finally, rewrite the count register with the enable bit set*/ PSB_WMSVDX32(uCountReg | DMAC_DMAC_COUNT_EN_MASK, DMAC_DMAC_COUNT_OFFSET + dma_channel); /* Wait for all to be done */ if (psb_wait_for_register(dev_priv, DMAC_DMAC_IRQ_STAT_OFFSET + dma_channel, DMAC_DMAC_IRQ_STAT_TRANSFER_FIN_MASK, DMAC_DMAC_IRQ_STAT_TRANSFER_FIN_MASK, 2000000, 5)) { psb_setup_fw_dump(dev_priv, dma_channel); msvdx_release_mtx_control_from_dash(dev_priv); return; } /* Assert that the MTX DMA port is all done aswell */ if (psb_wait_for_register(dev_priv, MTX_SYSC_CDMAS0_OFFSET, 1, 1, 2000000, 5)) { msvdx_release_mtx_control_from_dash(dev_priv); return; } msvdx_release_mtx_control_from_dash(dev_priv); PSB_DEBUG_GENERAL("MSVDX: Upload done\n"); }
static void tng__JPEG_set_register(context_JPEG_p ctx, VASliceParameterBufferJPEGBaseline *slice_param) { psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; uint32_t reg_value; const uint32_t num_MCUs = ctx->MCU_width * ctx->MCU_height; const uint32_t num_MCUs_dec = slice_param->restart_interval ? min(slice_param->restart_interval, num_MCUs) : num_MCUs; psb_cmdbuf_reg_start_block(cmdbuf, 0); // CR_VEC_JPEG_FE_COMPONENTS reg_value = 0; REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_COMPONENTS, MAX_V, ctx->max_scalingV); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_COMPONENTS, MAX_H, ctx->max_scalingH); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_COMPONENTS, FE_COMPONENTS, slice_param->num_components); psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_COMPONENTS ), reg_value); // CR_VEC_JPEG_FE_HEIGHT reg_value = 0; REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_HEIGHT, FE_HEIGHT_MINUS1, ctx->coded_picture_height - 1); psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_HEIGHT ), reg_value); // CR_VEC_JPEG_FE_RESTART_POS reg_value = 0; psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_RESTART_POS), reg_value); // CR_VEC_JPEG_FE_WIDTH reg_value = 0; REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_WIDTH, FE_WIDTH_MINUS1, ctx->coded_picture_width - 1 ); psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_WIDTH), reg_value); // CR_VEC_JPEG_FE_ENTROPY_CODING reg_value = 0; REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_ENTROPY_CODING, NUM_MCUS_LESS1, num_MCUs_dec - 1); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_ENTROPY_CODING, TA3, slice_param->components[3].ac_table_selector); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_ENTROPY_CODING, TD3, slice_param->components[3].dc_table_selector); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_ENTROPY_CODING, TA2, slice_param->components[2].ac_table_selector); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_ENTROPY_CODING, TD2, slice_param->components[2].dc_table_selector); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_ENTROPY_CODING, TA1, slice_param->components[1].ac_table_selector); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_ENTROPY_CODING, TD1, slice_param->components[1].dc_table_selector ); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_ENTROPY_CODING, TA0, slice_param->components[0].ac_table_selector); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_ENTROPY_CODING, TD0, slice_param->components[0].dc_table_selector); psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_ENTROPY_CODING ), reg_value); // CR_VEC_JPEG_FE_SCALING reg_value = 0; REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_SCALING, FE_V3, ctx->pic_params->components[3].v_sampling_factor); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_SCALING, FE_H3, ctx->pic_params->components[3].h_sampling_factor ); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_SCALING, FE_V2, ctx->pic_params->components[2].v_sampling_factor); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_SCALING, FE_H2, ctx->pic_params->components[2].h_sampling_factor ); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_SCALING, FE_V1, ctx->pic_params->components[1].v_sampling_factor ); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_SCALING, FE_H1, ctx->pic_params->components[1].h_sampling_factor ); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_SCALING, FE_V0, ctx->pic_params->components[0].v_sampling_factor ); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_SCALING, FE_H0, ctx->pic_params->components[0].h_sampling_factor ); psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC_JPEG, CR_VEC_JPEG_FE_SCALING ), reg_value); psb_cmdbuf_reg_end_block(cmdbuf); psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET( MSVDX_VEC_JPEG, CR_VEC_JPEG_BE_HEIGHT )); // CR_VEC_JPEG_BE_HEIGHT reg_value = 0; REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_BE_HEIGHT, BE_HEIGHT_MINUS1, ctx->coded_picture_height - 1); psb_cmdbuf_rendec_write(cmdbuf, reg_value); // CR_VEC_JPEG_BE_WIDTH reg_value = 0; REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_BE_WIDTH, BE_WIDTH_MINUS1, ctx->coded_picture_width - 1); psb_cmdbuf_rendec_write(cmdbuf, reg_value); // CR_VEC_JPEG_BE_QUANTISATION reg_value = 0; REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_BE_QUANTISATION, TQ3, ctx->pic_params->components[3].quantiser_table_selector); REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_BE_QUANTISATION, TQ2, ctx->pic_params->components[2].quantiser_table_selector); REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_BE_QUANTISATION, TQ1, ctx->pic_params->components[1].quantiser_table_selector); REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_BE_QUANTISATION, TQ0, ctx->pic_params->components[0].quantiser_table_selector ); psb_cmdbuf_rendec_write(cmdbuf, reg_value); // CR_VEC_JPEG_BE_CONTROL reg_value = 0; REGIO_WRITE_FIELD( reg_value, MSVDX_VEC_JPEG, CR_VEC_JPEG_BE_CONTROL, RGB, 0 ); psb_cmdbuf_rendec_write(cmdbuf, reg_value); psb_cmdbuf_rendec_end(cmdbuf); }
static void tng__JPEG_write_huffman_tables(context_JPEG_p ctx) { uint32_t reg_value; psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; // VLC Table // Write a LLDMA Cmd to transfer VLD Table data psb_cmdbuf_dma_write_cmdbuf(cmdbuf, &ctx->vlc_packed_table, 0, ctx->vlctable_buffer_size, 0, DMA_TYPE_VLC_TABLE); // Write Table addresses psb_cmdbuf_reg_start_block(cmdbuf, 0); reg_value = 0; uint32_t table_address = 0; REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR0, VLC_TABLE_ADDR0, table_address ); table_address += ctx->table_stats[0][0].size; REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR0, VLC_TABLE_ADDR1, table_address ); psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR0 ), reg_value); reg_value = 0; table_address += ctx->table_stats[0][1].size; REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR2, VLC_TABLE_ADDR4, table_address ); table_address += ctx->table_stats[1][0].size; REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR2, VLC_TABLE_ADDR5, table_address ); psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR2 ), reg_value); psb_cmdbuf_reg_end_block(cmdbuf); // Write Initial Widths psb_cmdbuf_reg_start_block(cmdbuf, 0); reg_value = 0; REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_INITIAL_WIDTH0, VLC_TABLE_INITIAL_WIDTH0, ctx->table_stats[0][0].initial_width ); REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_INITIAL_WIDTH0, VLC_TABLE_INITIAL_WIDTH1, ctx->table_stats[0][1].initial_width ); REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_INITIAL_WIDTH0, VLC_TABLE_INITIAL_WIDTH4, ctx->table_stats[1][0].initial_width ); REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_INITIAL_WIDTH0, VLC_TABLE_INITIAL_WIDTH5, ctx->table_stats[1][1].initial_width ); psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC, CR_VEC_VLC_TABLE_INITIAL_WIDTH0 ), reg_value); psb_cmdbuf_reg_end_block(cmdbuf); // Write Initial Opcodes psb_cmdbuf_reg_start_block(cmdbuf, 0); reg_value = 0; REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_INITIAL_OPCODE0, VLC_TABLE_INITIAL_OPCODE0, ctx->table_stats[0][0].initial_opcode ); REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_INITIAL_OPCODE0, VLC_TABLE_INITIAL_OPCODE1, ctx->table_stats[0][1].initial_opcode ); REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_INITIAL_OPCODE0, VLC_TABLE_INITIAL_OPCODE4, ctx->table_stats[1][0].initial_opcode ); REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_INITIAL_OPCODE0, VLC_TABLE_INITIAL_OPCODE5, ctx->table_stats[1][1].initial_opcode ); psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC, CR_VEC_VLC_TABLE_INITIAL_OPCODE0 ), reg_value); psb_cmdbuf_reg_end_block(cmdbuf); }
static void tng__yuv_processor_process(context_DEC_p dec_ctx) { context_yuv_processor_p ctx = dec_ctx->yuv_ctx; psb_cmdbuf_p cmdbuf = dec_ctx->obj_context->cmdbuf; /* psb_surface_p target_surface = dec_ctx->obj_context->current_render_target->psb_surface; */ psb_surface_p src_surface = ctx->src_surface; psb_buffer_p buffer; uint32_t reg_value; psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, DISPLAY_PICTURE_SIZE)); reg_value = 0; REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, DISPLAY_PICTURE_SIZE, DISPLAY_PICTURE_HEIGHT, (ctx->display_height) - 1); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, DISPLAY_PICTURE_SIZE, DISPLAY_PICTURE_WIDTH, (ctx->display_width) - 1); psb_cmdbuf_rendec_write(cmdbuf, reg_value); reg_value = 0; REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, CODED_PICTURE_SIZE, CODED_PICTURE_HEIGHT, (ctx->coded_height) - 1); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, CODED_PICTURE_SIZE, CODED_PICTURE_WIDTH, (ctx->coded_width) - 1); psb_cmdbuf_rendec_write(cmdbuf, reg_value); psb_cmdbuf_rendec_end(cmdbuf); /*TODO add stride and else there*/ reg_value = 0; REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, OPERATING_MODE, CODEC_MODE, 3); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, OPERATING_MODE, ASYNC_MODE, 1); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, OPERATING_MODE, CODEC_PROFILE, 1); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, OPERATING_MODE, CHROMA_FORMAT, 1); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, OPERATING_MODE, ROW_STRIDE, src_surface->stride_mode); psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET( MSVDX_CMDS, OPERATING_MODE )); psb_cmdbuf_rendec_write(cmdbuf, reg_value); psb_cmdbuf_rendec_end(cmdbuf); psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, REFERENCE_PICTURE_BASE_ADDRESSES)); buffer = &src_surface->buf; psb_cmdbuf_rendec_write_address(cmdbuf, buffer, buffer->buffer_ofs); psb_cmdbuf_rendec_write_address(cmdbuf, buffer, buffer->buffer_ofs + src_surface->chroma_offset); psb_cmdbuf_rendec_end(cmdbuf); reg_value = 0; REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, SLICE_PARAMS, CONSTRAINED_INTRA_PRED, 0 ); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, SLICE_PARAMS, MODE_CONFIG, 0 ); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, SLICE_PARAMS, DISABLE_DEBLOCK_FILTER_IDC, 1 ); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, SLICE_PARAMS, SLICE_ALPHA_CO_OFFSET_DIV2, 0 ); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, SLICE_PARAMS, SLICE_BETA_OFFSET_DIV2, 0 ); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, SLICE_PARAMS, SLICE_FIELD_TYPE, 2 ); REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, SLICE_PARAMS, SLICE_CODE_TYPE, 1 ); // P *dec_ctx->p_slice_params = reg_value; psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET( MSVDX_CMDS, SLICE_PARAMS ) ); psb_cmdbuf_rendec_write(cmdbuf, reg_value); psb_cmdbuf_rendec_end(cmdbuf); vld_dec_setup_alternative_frame(dec_ctx->obj_context); *cmdbuf->cmd_idx++ = CMD_DEBLOCK | CMD_DEBLOCK_TYPE_SKIP; *cmdbuf->cmd_idx++ = 0; *cmdbuf->cmd_idx++ = ctx->coded_width / 16; *cmdbuf->cmd_idx++ = ctx->coded_height / 16; *cmdbuf->cmd_idx++ = 0; *cmdbuf->cmd_idx++ = 0; }