int32_t dcam_stop(void)
{
enum dcam_drv_rtn rtn = DCAM_RTN_SUCCESS;
int ret = 0;
/* CAP_EB */
if (DCAM_CAPTURE_MODE_MULTIPLE == s_dcam_mod.dcam_mode) {
REG_AWR(DCAM_PATH_CFG, ~BIT_0);
_dcam_wait_for_stop();
if (atomic_read(&s_resize_flag)) {
s_resize_wait = 1;
/* resize started , wait for it going to the end*/
DCAM_TRACE("DCAM DRV: dcam_stop, wait: %d \n", s_done_sema.count);
ret= down_interruptible(&s_done_sema);
if (ret) {
printk("DCAM DRV:dcam_stop down err %d.\n",ret);
}
}
}
free_irq(DCAM_IRQ, &g_dcam_irq);
DCAM_TRACE("DCAM DRV: dcam_stop, exit from wait: %d \n", s_done_sema.count);
/* PATH1_EB */
REG_AWR(DCAM_CFG, ~BIT_0);
if (s_dcam_mod.dcam_path2.valide) {
/* PATH2_EB */
REG_AWR(DCAM_CFG, ~BIT_1);
}
/* reset all*/
dcam_reset(DCAM_RST_ALL);
#if 0
if (s_dcam_mod.dcam_path1.valide) {
/* PATH1_EB */
REG_AWR(DCAM_CFG, ~BIT_0);
/* path1 reset */
dcam_reset(DCAM_RST_PATH1);
}
if (s_dcam_mod.dcam_path2.valide) {
/* PATH2_EB */
REG_AWR(DCAM_CFG, ~BIT_1);
/* path2 reset */
dcam_reset(DCAM_RST_PATH2);
}
#endif
_dcam_frm_clear();
printk("DCAM E \n");
return -rtn;
}
int32_t dcam_pause(void)
{
enum dcam_drv_rtn rtn = DCAM_RTN_SUCCESS;
REG_AWR(DCAM_PATH_CFG, ~BIT_0);
printk("DCAM P \n");
return -rtn;
}
static void rot_k_set_img_size(ROT_SIZE_T * size)
{
REG_AWR(REG_ROTATION_IMG_SIZE, 0xFF000000);
REG_OWR(REG_ROTATION_IMG_SIZE,
(size->h & 0xFFF) | ((size->w & 0xFFF) << 12));
REG_WR(REG_ROTATION_ORIGWIDTH, size->w & 0xFFF);
return;
}
int32_t dcam_reset(enum dcam_rst_mode reset_mode)
{
enum dcam_drv_rtn rtn = DCAM_RTN_SUCCESS;
uint32_t time_out = 0;
if (atomic_read(&s_dcam_users)) {
/* firstly, stop AXI writing */
REG_OWR(DCAM_BURST_GAP, BIT_18);
}
/* then wait for AHB busy cleared */
while (++time_out < DCAM_AXI_STOP_TIMEOUT) {
if (0 == (REG_RD(DCAM_AHBM_STS) & BIT_0))
break;
}
if (time_out >= DCAM_AXI_STOP_TIMEOUT)
return DCAM_RTN_TIMEOUT;
/* do reset action */
switch (reset_mode) {
case DCAM_RST_PATH1:
sci_glb_set(DCAM_RST, PATH1_RST_BIT);
sci_glb_set(DCAM_RST, CCIR_RST_BIT);
sci_glb_clr(DCAM_RST, PATH1_RST_BIT);
sci_glb_clr(DCAM_RST, CCIR_RST_BIT);
/*
REG_OWR(DCAM_RST, DCAM_MOD_RST_BIT);
REG_OWR(DCAM_RST, CCIR_RST_BIT);
REG_AWR(DCAM_RST, ~DCAM_MOD_RST_BIT);
REG_AWR(DCAM_RST, ~CCIR_RST_BIT);
*/
DCAM_TRACE("DCAM DRV: reset path1 \n");
break;
case DCAM_RST_PATH2:
sci_glb_set(DCAM_RST, PATH2_RST_BIT);
sci_glb_clr(DCAM_RST, PATH2_RST_BIT);
DCAM_TRACE("DCAM DRV: reset path2 \n");
break;
case DCAM_RST_ALL:
sci_glb_set(DCAM_RST, DCAM_MOD_RST_BIT);
sci_glb_set(DCAM_RST, CCIR_RST_BIT);
sci_glb_clr(DCAM_RST, DCAM_MOD_RST_BIT);
sci_glb_clr(DCAM_RST, CCIR_RST_BIT);
DCAM_TRACE("DCAM DRV: reset all \n");
break;
default:
rtn = DCAM_RTN_PARA_ERR;
break;
}
if (atomic_read(&s_dcam_users)) {
/* the end, enable AXI writing */
REG_AWR(DCAM_BURST_GAP, ~BIT_18);
}
return -rtn;
}
static void rot_k_cfg(void)
{
// rot eb
REG_OWR(AHB_GLOBAL_REG_CTL0, BIT(14)); //ROTATION_DRV_ONE
// rot soft reset
REG_OWR(AHB_GLOBAL_REG_SOFTRST, BIT(10));
REG_AWR(AHB_GLOBAL_REG_SOFTRST, ~BIT(10));
}
static void rot_k_set_UV_mode(ROT_UV_MODE_E uv_mode)
{
REG_AWR(REG_ROTATION_CTRL, (~BIT(0)));
REG_OWR(REG_ROTATION_CTRL, (uv_mode & 0x1));
return;
}
static void rot_k_set_dir(ROT_ANGLE_E angle)
{
REG_AWR(REG_ROTATION_CTRL, ~(0x3 << 1));
REG_OWR(REG_ROTATION_CTRL, (angle & 0x3) << 1);
return;
}
static void rot_k_set_pixel_mode(ROT_PIXEL_FORMAT_E pixel_format)
{
REG_AWR(REG_ROTATION_IMG_SIZE, ~(0x3 << 24));
REG_OWR(REG_ROTATION_IMG_SIZE, pixel_format << 24);
return;
}
static void rot_k_software_reset(void)
{
// rot soft reset
REG_OWR(AHB_GLOBAL_REG_SOFTRST, BIT(10));
REG_AWR(AHB_GLOBAL_REG_SOFTRST, ~BIT(10));
}
static void rot_k_disable(void)
{
// rot eb
REG_AWR(AHB_GLOBAL_REG_CTL0, ~BIT(14)); //ROTATION_DRV_ONE
}
