int epdc_ctrl_init(void *lcdbase)
{
/*
* We rely on lcdbase being a physical address, i.e., either MMU off,
* or 1-to-1 mapping. Might want to add some virt2phys here.
*/
if (!lcdbase)
return -1;
eink_color_fg = 0xFF;
eink_color_bg = 0xFF;
/* Reset */
REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
while (!(REG_RD(EPDC_BASE, EPDC_CTRL) & EPDC_CTRL_CLKGATE))
;
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
/* Enable clock gating (clear to enable) */
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
while (REG_RD(EPDC_BASE, EPDC_CTRL) &
(EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
;
debug("resolution %dx%d, bpp %d\n", (int)panel_info.vl_col,
(int)panel_info.vl_row, NBITS(panel_info.vl_bpix));
/* Set framebuffer pointer */
REG_WR(EPDC_BASE, EPDC_UPD_ADDR, (u32)lcdbase);
#if 0
/* Set Working Buffer pointer */
REG_WR(EPDC_BASE, EPDC_WB_ADDR, panel_info.epdc_data.working_buf_addr);
/* Set Waveform Buffer pointer */
REG_WR(EPDC_BASE, EPDC_WVADDR, panel_info.epdc_data.waveform_buf_addr);
#endif
/* Set waveform and working buffer, they will be changed later */
REG_WR(EPDC_BASE, EPDC_WVADDR, (unsigned long)CONFIG_TEMP_INIT_WAVEFORM_ADDR);
REG_WR(EPDC_BASE, EPDC_WB_ADDR, (unsigned long)CONFIG_WORKING_BUF_ADDR);
#if 0
/* Get waveform data address and offset */
int data_offs = setup_waveform_file();
if(data_offs == -1) {
printf("Can't load waveform data!\n");
return -1;
}
#endif
/* Initialize EPDC, passing pointer to EPDC registers */
epdc_init_settings();
epdc_initialized = 1;
return;
}
void lcd_ctrl_init(void *lcdbase)
{
/*
* We rely on lcdbase being a physical address, i.e., either MMU off,
* or 1-to-1 mapping. Might want to add some virt2phys here.
*/
if (!lcdbase)
return;
lcd_color_fg = 0xFF;
lcd_color_bg = 0xFF;
/* Reset */
REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
while (!(REG_RD(EPDC_BASE, EPDC_CTRL) & EPDC_CTRL_CLKGATE))
;
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
/* Enable clock gating (clear to enable) */
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
while (REG_RD(EPDC_BASE, EPDC_CTRL) &
(EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
;
debug("resolution %dx%d, bpp %d\n", (int)panel_info.vl_col,
(int)panel_info.vl_row, NBITS(panel_info.vl_bpix));
/* Set framebuffer pointer */
REG_WR(EPDC_BASE, EPDC_UPD_ADDR, (u32)lcdbase);
/* Set Working Buffer pointer */
REG_WR(EPDC_BASE, EPDC_WB_ADDR, panel_info.epdc_data.working_buf_addr);
/* Get waveform data address and offset */
if (setup_waveform_file()) {
printf("Can't load waveform data!\n");
return;
}
/* Set Waveform Buffer pointer */
REG_WR(EPDC_BASE, EPDC_WVADDR,
panel_info.epdc_data.waveform_buf_addr);
/* Initialize EPDC, passing pointer to EPDC registers */
epdc_init_settings();
return;
}
void epd_enable(void)
{
char temp = TEMP_USE_DEFAULT;
debug("epd_enable\n");
//epdc_power_on();
/* Draw data to display */
//draw_mode0();
/* Enable clock gating (clear to enable) */
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
while (REG_RD(EPDC_BASE, EPDC_CTRL) &
(EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
;
REG_WR(EPDC_BASE, EPDC_TEMP, TEMP_USE_DEFAULT);
temp = read_temperature();
// temp = do_read_temperature_via_i2c();
temp_set_index(temp);
/* Set Waveform Bufferr register to real waveform address */
REG_WR(EPDC_BASE, EPDC_WVADDR, panel_info.epdc_data.waveform_buf_addr);
debug("epdc_irq's value %08x\nEPDC_IRQ_CLR's value %08x\n",REG_RD(EPDC_BASE, EPDC_IRQ), REG_RD(EPDC_BASE, EPDC_IRQ_CLR));
debug("EPDC LUT STATUS %08x\n",REG_RD(EPDC_BASE,EPDC_STATUS_LUTS));
draw_splash_screen();
debug("epdc_irq's value %08x\nEPDC_IRQ_CLR's value %08x\n",REG_RD(EPDC_BASE, EPDC_IRQ), REG_RD(EPDC_BASE, EPDC_IRQ_CLR));
debug("EPDC LUT STATUS %08x\n",REG_RD(EPDC_BASE,EPDC_STATUS_LUTS));
}
static void set_clocks(void)
{
u32 ssp_source_clk, ssp_clk;
u32 ssp_div = 1;
u32 val = 0;
/*
* Configure 480Mhz IO clock
*/
/* Ungate IO_CLK and set divider */
REG_CLR(CLKCTRL_BASE + CLKCTRL_FRAC, FRAC_CLKGATEIO);
REG_CLR(CLKCTRL_BASE + CLKCTRL_FRAC, 0x3f << FRAC_IOFRAC);
REG_SET(CLKCTRL_BASE + CLKCTRL_FRAC, IO_DIVIDER << FRAC_IOFRAC);
/*
* Set SSP CLK to desired value
*/
/* Calculate SSP_CLK divider relatively to 480Mhz IO_CLK*/
ssp_source_clk = 480 * MHz;
ssp_clk = CONFIG_SSP_CLK;
ssp_div = (ssp_source_clk + ssp_clk - 1) / ssp_clk;
/* Enable SSP clock */
val = REG_RD(CLKCTRL_BASE + CLKCTRL_SSP);
val &= ~SSP_CLKGATE;
REG_WR(CLKCTRL_BASE + CLKCTRL_SSP, val);
/* Wait while clock is gated */
while (REG_RD(CLKCTRL_BASE + CLKCTRL_SSP) & SSP_CLKGATE)
;
/* Set SSP clock divider */
val &= ~(0x1ff << SSP_DIV);
val |= ssp_div << SSP_DIV;
REG_WR(CLKCTRL_BASE + CLKCTRL_SSP, val);
/* Wait until new divider value is set */
while (REG_RD(CLKCTRL_BASE + CLKCTRL_SSP) & SSP_BUSY)
;
/* Set SSP clock source to IO_CLK */
REG_SET(CLKCTRL_BASE + CLKCTRL_CLKSEQ, CLKSEQ_BYPASS_SSP);
REG_CLR(CLKCTRL_BASE + CLKCTRL_CLKSEQ, CLKSEQ_BYPASS_SSP);
}
int timer_init(void)
{
u32 val;
/*
* Reset Timers and Rotary Encoder module
*/
/* Clear SFTRST */
REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31);
while (REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 31))
;
/* Clear CLKGATE */
REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30);
/* Set SFTRST and wait until CLKGATE is set */
REG_SET(TIMROT_BASE + ROTCTRL, 1 << 31);
while (!(REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 30)))
;
/* Clear SFTRST and CLKGATE */
REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31);
REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30);
/*
* Now initialize timer
*/
/* Set fixed_count to 0 */
REG_WR(TIMROT_BASE + TIMCOUNT, 0);
/* set UPDATE bit and 1Khz frequency */
REG_WR(TIMROT_BASE + TIMCTRL,
TIMCTRL_RELOAD | TIMCTRL_UPDATE | TIMCTRL_SELECT_1KHZ);
/* Set fixed_count to maximal value */
REG_WR(TIMROT_BASE + TIMCOUNT, TIMER_LOAD_VAL);
/* init the timestamp and lastdec value */
reset_timer_masked();
return 0;
}
////////////////////////////////////////////////////////////////////////////////
// UserEarlyConfig()函数在启动代码中执行，这时还没有RTOS存在。
////////////////////////////////////////////////////////////////////////////////
bool_t UserEarlyConfig(void)
{
// 尽早初始化中断控制模块使之可用。
if(!ICOLL_Init()){
return FALSE;
}
// 将所有USART的时钟源设置为PLL (BUG：UART只能用12MHZ晶振作时钟源)。
outl(1, REG_SET(HW_UARTCLKSEL));
outl(1, REG_CLR(HW_UARTCLKUEN));
outl(1, REG_SET(HW_UARTCLKUEN));
return TRUE;
}
static void set_pinmux(void)
{
#if defined(CONFIG_SPI_SSP1)
/* Configure SSP1 pins for ENC28j60: 8maA */
REG_CLR(PINCTRL_BASE + PINCTRL_MUXSEL(4), 0x00003fff);
REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(8), 0X03333333);
REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(8), 0x01111111);
REG_CLR(PINCTRL_BASE + PINCTRL_PULL(2), 0x0000003f);
#endif
#if defined(CONFIG_SPI_SSP2)
/* Configure SSP2 pins for ENC28j60: 8maA */
REG_CLR(PINCTRL_BASE + PINCTRL_MUXSEL(0), 0x00000fc3);
REG_SET(PINCTRL_BASE + PINCTRL_MUXSEL(0), 0x00000a82);
REG_CLR(PINCTRL_BASE + PINCTRL_MUXSEL(1), 0x00030300);
REG_SET(PINCTRL_BASE + PINCTRL_MUXSEL(1), 0x00020200);
REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(0), 0X00333003);
REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(0), 0x00111001);
REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(2), 0x00030000);
REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(2), 0x00010000);
REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(3), 0x00000003);
REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(3), 0x00000001);
REG_CLR(PINCTRL_BASE + PINCTRL_PULL(0), 0x00100039);
#endif
}
void HW_SetPinMux(rt_uint8_t port, rt_uint8_t pin, rt_uint8_t mux_type)
{
rt_uint32_t addr = HW_IOCON(port, pin);
rt_uint32_t val = inl(addr); // read origin value
val &= ~7UL; // clear MUX field
val |= mux_type; // set MUX field with new value
outl(val ,addr); // Set new value
}
void HW_GpioSetDir(rt_uint8_t port, rt_uint8_t pin, rt_uint8_t isOut)
{
rt_uint32_t addr = HW_GPIO_DATA_BASE | ((port>>2)<<16) | 0x8000;
rt_uint32_t val;
addr = isOut? REG_SET(addr) : REG_CLR(addr);
val = (1 << ((port%4)*8+pin));
outl(val, addr);
}
void HW_GpioSetVal(rt_uint8_t port, rt_uint8_t pin)
{
rt_uint32_t addr, val;
addr = REG_SET(HW_GPIO_DATA_BASE | ((port>>2)<<16));
val = (1 << ((port%4)*8+pin));
outl(val, addr);
}
void HW_GpioClrVal(rt_uint8_t port, rt_uint8_t pin)
{
rt_uint32_t addr, val;
