static void usb2_phy_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script usb2_phy_script[] = { /* USB3PHYInit() */ REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, 0x4700), /* Per port phy settings, set in devicetree.cb */ REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0, config->usb2_per_port_lane0), REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_RCOMP_HS_PULLUP0, config->usb2_per_port_rcomp_hs_pullup0), REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE1, config->usb2_per_port_lane1), REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_RCOMP_HS_PULLUP1, config->usb2_per_port_rcomp_hs_pullup1), REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE2, config->usb2_per_port_lane2), REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_RCOMP_HS_PULLUP2, config->usb2_per_port_rcomp_hs_pullup2), REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE3, config->usb2_per_port_lane3), REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_RCOMP_HS_PULLUP3, config->usb2_per_port_rcomp_hs_pullup3), REG_SCRIPT_END }; reg_script_run(usb2_phy_script); }
static void xhci_init(struct device *dev) { struct soc_intel_braswell_config *config = dev->chip_info; if (config && config->usb_comp_bg) { struct reg_script ops[] = { REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, config->usb_comp_bg), REG_SCRIPT_END }; printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n", config->usb_comp_bg); reg_script_run(ops); } }
REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA944, 0xFFFF0000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA948, 0x00220000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA94C, 0x43000000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA950, 0x00000800), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA954, 0x00000000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA960, 0x00000000), /* SET3 */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa3c, 0x00000000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa54, 0x00000000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa60, 0x00000000), /* Enable PowerMeter Counters */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA248, 0x00000058), /* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */ /* SDP Profile 4 == 0x11940, others 0xcf08 */ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08), /* GfxPause */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388), /* Dynamic EU Control Settings */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa080, 0x00000004), /* Lock ECO Bit Settings */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x80000000), /* DOP Clock Gating */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x00000001), /* MBCunit will send the VCR (Fuse) writes as NP-W */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x907c, 0xfffeffff, 0x00010000),
* * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <stdint.h> #include <bootstate.h> #include <console/console.h> #include <reg_script.h> #include <soc/iosf.h> static const struct reg_script dptf_init_settings[] = { /* SocThermInit */ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTMC, 0x00030708), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 0x00000000), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_XXPROCHOT, 0x00061029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM0, 0x00001029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM1, 0x00001029), /* ratio 11 = 1466mhz for mid and entry celeron */ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000B00), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_ENERGY_CREDIT, 0x00000002), REG_SCRIPT_END, };
*/ #include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <reg_script.h> #include <soc/iosf.h> #include <soc/nvs.h> #include <soc/ramstage.h> static const struct reg_script scc_start_dll[] = { /* Configure master DLL. */ REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4964, 0x00078000), /* Configure Swing,FSM for Master DLL */ REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00000133), /* Run+Local Reset on Master DLL */ REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00001933), REG_SCRIPT_END, }; static const struct reg_script scc_after_dll[] = { /* Configure Write Path */ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4954, ~0x7fff, 0x35ad), REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4958, ~0x7fff, 0x35ad), REG_IOSF_RMW(IOSF_PORT_SCORE, 0x495c, ~0x7fff, 0x35ad), /* Configure Read Path */ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x43e4, ~0x7fff, 0x35ad), REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4324, ~0x7fff, 0x35ad),
#include <device/pci_ids.h> #include <reg_script.h> #include <soc/intel/common/hda_verb.h> #include <soc/iomap.h> #include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> static const struct reg_script init_ops[] = { /* Enable no snoop traffic. */ REG_PCI_OR16(0x78, 1 << 11), /* Configure HDMI codec connection. */ REG_PCI_OR32(0xc4, 1 << 1), REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00), /* Configure internal settings. */ REG_PCI_OR32(0xc0, 0x7 << 21), REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)), REG_PCI_WRITE32(0xc8, 0x82a30000), REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0), /* Disable docking. */ REG_PCI_RMW8(0x4d, ~(1 << 7), 0), REG_SCRIPT_END, }; static const uint32_t hdmi_codec_verb_table[] = { /* coreboot specific header */ 0x80862882, /* vid did for hdmi codec */ 0x00000000, /* subsystem id */