static void init_usart(void) {
/* Configure the usart */
REG_STORE(AT91C_PMC_PCER, (1 << OPTION_GET(NUMBER,dev_id)));
REG_STORE(AT91C_PIOA_PDR, BTM_BT_RX_PIN | BTM_BT_TX_PIN |
BTM_BT_SCK_PIN | BTM_BT_RTS_PIN | BTM_BT_CTS_PIN);
REG_STORE(AT91C_PIOA_ASR, BTM_BT_RX_PIN | BTM_BT_TX_PIN |
BTM_BT_SCK_PIN | BTM_BT_RTS_PIN | BTM_BT_CTS_PIN);
REG_STORE(&(us_dev_regs->US_PTCR), (AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS));
REG_STORE(&(us_dev_regs->US_CR), AT91C_US_RXDIS | AT91C_US_TXDIS);
REG_STORE(&(us_dev_regs->US_CR), AT91C_US_RSTSTA | AT91C_US_RSTRX | AT91C_US_RSTTX);
REG_STORE(&(us_dev_regs->US_CR), AT91C_US_STTTO);
REG_STORE(&(us_dev_regs->US_MR), AT91C_US_USMODE_HWHSH
| AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE
| AT91C_US_NBSTOP_1_BIT);
REG_STORE(&(us_dev_regs->US_BRGR), SYS_CLOCK / (16 * BTM_BT_BAUD_RATE));
REG_STORE(&(us_dev_regs->US_IDR), ~0);
REG_STORE(&(us_dev_regs->US_RCR), 0);
REG_STORE(&(us_dev_regs->US_TCR), 0);
REG_STORE(&(us_dev_regs->US_RNPR), 0);
REG_STORE(&(us_dev_regs->US_TNPR), 0);
REG_LOAD(&(us_dev_regs->US_RHR));
REG_LOAD(&(us_dev_regs->US_CSR));
REG_STORE(&(us_dev_regs->US_CR), AT91C_US_RXEN | AT91C_US_TXEN);
REG_STORE(&(us_dev_regs->US_PTCR), AT91C_PDC_RXTEN | AT91C_PDC_TXTEN);
REG_STORE(&(us_dev_regs->US_IER), AT91C_US_ENDRX);
}
static int gic_init(void) {
uint32_t tmp = REG_LOAD(GICD_CTLR);
REG_STORE(GICD_CTLR, tmp | 0x1);
tmp = REG_LOAD(GICC_CTLR);
REG_STORE(GICC_CTLR, tmp | 0x1);
/* Set priority filter level */
REG_STORE(GICC_PMR, 0xFF);
tmp = REG_LOAD(GICD_TYPER);
printk("\n"
"\t\tNumber of SPI: %d\n"
"\t\tNumber of supported CPU interfaces: %d\n"
"\t\tSecutity Extension %s implemented\n",
GICD_TYPER_ITLINES(tmp) * 32,
1 + GICD_TYPER_CPUNR(tmp),
GICD_TYPER_SECEXT(tmp) ? "" : "not ");
if (tmp & (1 << 10)) {
printk("\t\tNumber of LSPI: %d", GICD_TYPER_LSPI(tmp));
} else {
printk("\t\tLSPI not implemented");
}
printk("\n\t");
return 0;
}
static void init_usart(void) {
/* Configure the usart */
REG_STORE(AT91C_PMC_PCER, (1 << CONFIG_NXT_BT_US_DEV_ID));
REG_STORE(AT91C_PIOA_PDR, RX_PIN | TX_PIN |
SCK_PIN | RTS_PIN | CTS_PIN);
REG_STORE(AT91C_PIOA_ASR, RX_PIN | TX_PIN |
SCK_PIN | RTS_PIN | CTS_PIN);
REG_STORE(&(us_dev_regs->US_PTCR), (AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS));
REG_STORE(&(us_dev_regs->US_CR), AT91C_US_RSTSTA | AT91C_US_RSTRX | AT91C_US_RSTTX);
REG_STORE(&(us_dev_regs->US_CR), AT91C_US_STTTO);
REG_STORE(&(us_dev_regs->US_RTOR), 10000);
REG_STORE(&(us_dev_regs->US_MR), (AT91C_US_USMODE_HWHSH & ~AT91C_US_SYNC)
| AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE
| AT91C_US_NBSTOP_1_BIT | AT91C_US_OVER);
REG_STORE(&(us_dev_regs->US_IDR), ~0);
REG_STORE(&(us_dev_regs->US_IER), AT91C_US_ENDRX);
REG_STORE(&(us_dev_regs->US_BRGR), CONFIG_SYS_CLOCK / (8 * NXT_BT_BAUD_RATE));
REG_STORE(&(us_dev_regs->US_RCR), 0);
REG_STORE(&(us_dev_regs->US_TCR), 0);
REG_STORE(&(us_dev_regs->US_RNPR), 0);
REG_STORE(&(us_dev_regs->US_TNPR), 0);
REG_LOAD(&(us_dev_regs->US_RHR));
REG_LOAD(&(us_dev_regs->US_CSR));
REG_STORE(&(us_dev_regs->US_CR), AT91C_US_RXEN | AT91C_US_TXEN);
REG_STORE(&(us_dev_regs->US_PTCR), AT91C_PDC_RXTEN | AT91C_PDC_TXTEN);
}
size_t bluetooth_write(uint8_t *buff, size_t len) {
while (!(REG_LOAD(&(us_dev_regs->US_CSR)) & AT91C_US_ENDTX)) {
}
REG_STORE(&(us_dev_regs->US_TPR), (uint32_t) buff);
REG_STORE(&(us_dev_regs->US_TCR), len);
return len;
}
static int apbuart_putc(struct uart *dev, int ch) {
while (!(UART_STAT_TE & REG_LOAD(&dev_regs->status))) {
}
REG_STORE(&dev_regs->data, (uint32_t) ch);
return 0;
}
static int stm32_uart_putc(struct uart *dev, int ch) {
struct uart_stm32 *uart = (struct uart_stm32 *) dev->base_addr;
while (!(REG_LOAD(&uart->sr) & USART_FLAG_TXE)) { }
REG_STORE(&uart->dr, ch);
return 0;
}
static int this_config(struct time_dev_conf * conf) {
uint32_t tmp;
uint8_t prescaler = 1;
REG_STORE(PTIMER_LOAD, LOAD_VALUE);
tmp = REG_LOAD(PTIMER_CONTROL);
tmp |= PTIMER_ENABLE | PTIMER_AUTO_RELOAD | PTIMER_IRQ_ENABLE;
tmp |= prescaler << PTIMER_PRESCALER_SHIFT;
REG_STORE(PTIMER_CONTROL, tmp);
return 0;
}
static irq_return_t nxt_bt_us_handler(unsigned int irq_nr, void *data) {
if (!data_pack) {
return IRQ_HANDLED;
}
if (REG_LOAD(&(us_dev_regs->US_CSR)) & AT91C_US_ENDTX) {
struct pnet_pack *_pack = data_pack;
data_pack = NULL;
if (0 != netif_rx(_pack)) {
pnet_pack_destroy(_pack);
}
}
return IRQ_HANDLED;
}
static int ti81xx_start(struct usb_hcd *hcd) {
struct ti81xx_usb *tiusb = hcd2ti(hcd);
int ret;
assert(tiusb == (void *) 0x47401000);
ret = irq_attach(TI8168_USB0_IRQ, ti81xx_irq, 0, hcd, "ti8168 usb0 irq");
if (0 != ret) {
return ret;
}
REG_ORIN(&tiusb->ctrl, TI81_USB_CTRL_RST);
while((REG_LOAD(&tiusb->ctrl) & TI81_USB_CTRL_RST));
REG_STORE(&tiusb->phy_utmi, TI81_USB_PHYUTMI_DEFAULT);
{
uint32_t regval = REG_LOAD(&tiusb->mode);
regval &= ~TI81_USB_MODE_IDDIG;
regval |= 0x80;
REG_STORE(&tiusb->mode, regval);
}
REG_ORIN(0x48140620, 0x00000003);
REG_ORIN(0x48140624, 0xf);
REG_STORE(&tiusb->irq_set0, 0xffffffff);
REG_STORE(&tiusb->irq_set1, TI81_USB_IRQ_STAT1_ALL_BUT_SOF);
REG8_STORE(&tiusb->m_devctl, TI81_USB_DEVCTL_SESSION);
REG8_STORE(&tiusb->m_intrusbe, 0xff);
ti81xx_endp_fifo_init(tiusb);
return 0;
}
/* timer handler
* we scan PIN_BT4 for changing and if it changed bt state switch to disconnect
* mode.
*/
static void nxt_bt_timer_handler(struct sys_timer *timer, void *param) {
static int bt_last_state; //TODO init state? //inited with 0, ok
int bt_state = REG_LOAD(AT91C_ADC_CDR6) > 0x200 ? 1 : 0;
if (bt_last_state != bt_state) {
struct pnet_pack *pack = pnet_pack_create(NULL, 1, PNET_PACK_TYPE_SINGLE);
assert(pack);
pack->node = &this_ctrl;
*((uint8_t *) pnet_pack_get_data(pack)) = bt_state;
if (0 != pnet_entry(pack)) {
pnet_pack_destroy(pack);
}
bt_last_state = bt_state;
}
REG_STORE(AT91C_ADC_CR, AT91C_ADC_START);
}
void irqctrl_enable(unsigned int irq) {
int n = irq / BITS_PER_REGISTER;
int m = irq % BITS_PER_REGISTER;
uint32_t tmp;
/* Writing zeroes to this register has no
* effect, so we just write single "1" */
REG_STORE(GICD_ISENABLER(n), 1 << m);
/* N-N irq model: all CPUs receive this IRQ */
REG_STORE(GICD_ICFGR(n), 1 << m);
/* All CPUs do listen to this IRQ */
n = irq / 4;
m = irq % 4;
tmp = REG_LOAD(GICD_ITARGETSR(n));
tmp |= 0xFF << (8 * m);
REG_STORE(GICD_ITARGETSR(n), tmp);
}
void interrupt_handle(void) {
unsigned int irq = REG_LOAD(GICC_IAR);
if (irq == SPURIOUS_IRQ)
return;
/* TODO check if IRQ number is correct */
assert(!critical_inside(CRITICAL_IRQ_LOCK));
irqctrl_disable(irq);
irqctrl_eoi(irq);
critical_enter(CRITICAL_IRQ_HANDLER);
{
ipl_enable();
irq_dispatch(irq);
ipl_disable();
}
irqctrl_enable(irq);
critical_leave(CRITICAL_IRQ_HANDLER);
critical_dispatch_pending();
}
static int stm32_uart_hasrx(struct uart *dev) {
struct uart_stm32 *uart = (struct uart_stm32 *) dev->base_addr;
return (REG_LOAD(&uart->sr) & USART_FLAG_RXNE);
}
static int apbuart_getc(struct uart *dev) {
return REG_LOAD(&dev_regs->data);
}
static cycle_t this_read(void) {
return LOAD_VALUE - REG_LOAD(PTIMER_COUNTER);
}
static int stm32_uart_getc(struct uart *dev) {
struct uart_stm32 *uart = (struct uart_stm32 *) dev->base_addr;
return REG_LOAD(&uart->dr);
}
static int apbuart_has_symbol(struct uart *dev) {
return (UART_STAT_DR & REG_LOAD(&dev_regs->status));
}
pin_mask_t pin_get_input_changed(void) {
return (int) REG_LOAD(AT91C_PIOA_ISR);
}
pin_mask_t pin_get_input(pin_mask_t mask) {
return mask & ((int) REG_LOAD(AT91C_PIOA_PDSR));
}
