static void set_display_intf(struct mdp5_kms *mdp5_kms, struct mdp5_interface *intf) { unsigned long flags; u32 intf_sel; spin_lock_irqsave(&mdp5_kms->resource_lock, flags); intf_sel = mdp5_read(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0)); switch (intf->num) { case 0: intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF0__MASK; intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF0(intf->type); break; case 1: intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF1__MASK; intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF1(intf->type); break; case 2: intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF2__MASK; intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF2(intf->type); break; case 3: intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF3__MASK; intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF3(intf->type); break; default: BUG(); break; } mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), intf_sel); spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); }
static int mdp5_hw_init(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); struct drm_device *dev = mdp5_kms->dev; unsigned long flags; pm_runtime_get_sync(dev->dev); /* Magic unknown register writes: * * W VBIF:0x004 00000001 (mdss_mdp.c:839) * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) * * Downstream fbdev driver gets these register offsets/values * from DT.. not really sure what these registers are or if * different values for different boards/SoC's, etc. I guess * they are the golden registers. * * Not setting these does not seem to cause any problem. But * we may be getting lucky with the bootloader initializing * them for us. OTOH, if we can always count on the bootloader * setting the golden registers, then perhaps we don't need to * care. */ spin_lock_irqsave(&mdp5_kms->resource_lock, flags); mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), 0); spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); mdp5_ctlm_hw_reset(mdp5_kms->ctlm); pm_runtime_put_sync(dev->dev); return 0; }