unsigned int spc_dump_reg()
{
SPCMSG("SPC Reg Dump Start !\n");
SPCMSG("(+0x500)SMI_SEN = 0x%x \n", COM_ReadReg32(REG_SMI_SEN ));
SPCMSG("(+0x520)SMI_SRAM_RANGE0= 0x%x \n", COM_ReadReg32(REG_SMI_ISPSYS_SRAM_RANG(0)));
SPCMSG("(+0x524)SMI_SRAM_RANGE1= 0x%x \n", COM_ReadReg32(REG_SMI_ISPSYS_SRAM_RANG(1)));
SPCMSG("(+0x528)SMI_SRAM_RANGE2= 0x%x \n", COM_ReadReg32(REG_SMI_ISPSYS_SRAM_RANG(2)));
SPCMSG("(+0x52C)SMI_SRAM_RANGE3= 0x%x \n", COM_ReadReg32(REG_SMI_ISPSYS_SRAM_RANG(3)));
SPCMSG("(+0x530)SMI_SRNG_ACTL0 = 0x%x \n", COM_ReadReg32(REG_SMI_ISPSYS_SRNG_ACTL(0)));
SPCMSG("(+0x534)SMI_SRNG_ACTL1 = 0x%x \n", COM_ReadReg32(REG_SMI_ISPSYS_SRNG_ACTL(1) ));
SPCMSG("(+0x538)SMI_SRNG_ACTL2 = 0x%x \n", COM_ReadReg32(REG_SMI_ISPSYS_SRNG_ACTL(2) ));
SPCMSG("(+0x53C)SMI_SRNG_ACTL3 = 0x%x \n", COM_ReadReg32(REG_SMI_ISPSYS_SRNG_ACTL(3) ));
SPCMSG("(+0x540)SMI_SRNG_ACTL4 = 0x%x \n", COM_ReadReg32(REG_SMI_ISPSYS_SRNG_ACTL(4) ));
SPCMSG("(+0x550)SMI_D_VIO_CON0 = 0x%x \n", COM_ReadReg32(REG_ISPSYS_D_VIO_CON(0)));
SPCMSG("(+0x554)SMI_D_VIO_CON1 = 0x%x \n", COM_ReadReg32(REG_ISPSYS_D_VIO_CON(1)));
SPCMSG("(+0x558)SMI_D_VIO_CON2 = 0x%x \n", COM_ReadReg32(REG_ISPSYS_D_VIO_CON(2) ));
SPCMSG("(+0x558)SMI_D_VIO_CON3 = 0x%x \n", COM_ReadReg32(REG_ISPSYS_D_VIO_CON(3) ));
SPCMSG("(+0x560)SMI_D_VIO_STA0 = 0x%x \n", COM_ReadReg32(REG_ISPSYS_D_VIO_STA(0) ));
SPCMSG("(+0x564)SMI_D_VIO_STA1 = 0x%x \n", COM_ReadReg32(REG_ISPSYS_D_VIO_STA(1) ));
SPCMSG("(+0x568)SMI_D_VIO_STA2 = 0x%x \n", COM_ReadReg32(REG_ISPSYS_D_VIO_STA(2) ));
SPCMSG("(+0x568)SMI_D_VIO_STA2 = 0x%x \n", COM_ReadReg32(REG_ISPSYS_D_VIO_STA(3) ));
SPCMSG("(+0x570)SMI_VIO_DBG0 = 0x%x \n", COM_ReadReg32(REG_ISPSYS_VIO_DBG0 ));
SPCMSG("(+0x570)SMI_VIO_DBG1 = 0x%x \n", COM_ReadReg32(REG_ISPSYS_VIO_DBG1 ));
SPCMSG("(+0x5C0)SMI_SECUR_CON0 = 0x%x \n", COM_ReadReg32(REG_SMI_SECUR_CON(0) ));
SPCMSG("(+0x5C4)SMI_SECUR_CON1 = 0x%x \n", COM_ReadReg32(REG_SMI_SECUR_CON(1) ));
SPCMSG("(+0x5C8)SMI_SECUR_CON2 = 0x%x \n", COM_ReadReg32(REG_SMI_SECUR_CON(2) ));
SPCMSG("(+0x5CC)SMI_SECUR_CON3 = 0x%x \n", COM_ReadReg32(REG_SMI_SECUR_CON(3) ));
SPCMSG("(+0x5D0)SMI_SECUR_CON4 = 0x%x \n", COM_ReadReg32(REG_SMI_SECUR_CON(4) ));
SPCMSG("(+0x5D4)SMI_SECUR_CON5 = 0x%x \n", COM_ReadReg32(REG_SMI_SECUR_CON(5) ));
SPCMSG("(+0x5D8)SMI_SECUR_CON6 = 0x%x \n", COM_ReadReg32(REG_SMI_SECUR_CON(6) ));
SPCMSG("(+0x5DC)SMI_SECUR_CON7 = 0x%x \n", COM_ReadReg32(REG_SMI_SECUR_CON(7) ));
SPCMSG("SPC Reg Dump End !\n");
return 0;
}
/*****************************************************************************
* FUNCTION
* larb_reg_backup
* DESCRIPTION
* Backup register for system suspend.
* PARAMETERS
* param1 : [IN] const int larb
* larb index.
* RETURNS
* None.
****************************************************************************/
static void larb_reg_backup(const int larb)
{
unsigned int* pReg = pLarbRegBackUp[larb];
int i;
unsigned int larb_base = gLarbBaseAddr[larb];
//SMI registers
for(i=0; i<2; i++)
*(pReg++) = COM_ReadReg32(REG_SMI_SECUR_CON(i));
*(pReg++) = M4U_ReadReg32(larb_base, SMI_LARB_CON);
for(i=0; i<MAU_ENTRY_NR; i++)
{
*(pReg++) = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_START(i));
*(pReg++) = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_END(i));
*(pReg++) = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_GID(i));
}
}
/*****************************************************************************
* FUNCTION
* larb_reg_restore
* DESCRIPTION
* Restore register for system resume.
* PARAMETERS
* param1 : [IN] const int larb
* larb index.
* RETURNS
* None.
****************************************************************************/
static void larb_reg_restore(const int larb)
{
unsigned int* pReg = pLarbRegBackUp[larb];
int i;
unsigned int regval;
unsigned int larb_base = gLarbBaseAddr[larb];
//SMI registers
for(i=0; i<2; i++)
COM_WriteReg32(REG_SMI_SECUR_CON(i), *(pReg++) );
//warning: larb_con is controlled by set/clr
regval = *(pReg++);
M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval));
M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval));
for(i=0; i<MAU_ENTRY_NR; i++)
{
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++));
}
}
