static int idtg2_em_handler(struct rio_dev *rdev, UINT8 portnum) { UINT32 regval, em_perrdet, em_ltlerrdet; #ifdef DEBUG_SRIO char achBuffer[80]; #endif rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet); if (em_ltlerrdet) { /* Service Logical/Transport Layer Error(s) */ if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) { /* Implementation specific error reported */ rio_read_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, ®val); #ifdef DEBUG_SRIO sprintf(achBuffer,"RIO: %s Implementation Specific LTL errors" \ " 0x%x @(0x%x)\n", rio_name(rdev), em_ltlerrdet, regval); sysDebugWriteString(achBuffer); #endif /* Clear implementation specific address capture CSR */ rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0); } } rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet); if (em_perrdet) { /* Service Port-Level Error(s) */ if (em_perrdet & REM_PED_IMPL_SPEC) { /* Implementation Specific port error reported */ /* Get IS errors reported */ rio_read_config_32(rdev, IDT_PORT_ISERR_DET(portnum), ®val); #ifdef DEBUG_SRIO sprintf(achBuffer,"RIO: %s Implementation Specific Port" \ " errors 0x%x\n", rio_name(rdev), regval); sysDebugWriteString(achBuffer); #endif /* Clear all implementation specific events */ rio_write_config_32(rdev, IDT_PORT_ISERR_DET(portnum), 0); } } return 0; }
/* * This routine performs device-specific initialization only. * All standard EM configuration should be performed at upper level. */ static int idtg3_em_init(struct rio_dev *rdev) { int i, tmp; u32 rval; pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount); /* Disable assertion of interrupt signal */ rio_write_config_32(rdev, RIO_EM_DEV_INT_EN, 0); /* Disable port-write event notifications during initialization */ rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PW_TX_CTRL, RIO_EM_PW_TX_CTRL_PW_DIS); /* Configure Port-Write notifications for hot-swap events */ tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo); for (i = 0; i < tmp; i++) { rio_read_config_32(rdev, RIO_DEV_PORT_N_ERR_STS_CSR(rdev, i), &rval); if (rval & RIO_PORT_N_ERR_STS_PORT_UA) continue; /* Clear events signaled before enabling notification */ rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PN_ERR_DETECT(i), 0); /* Enable event notifications */ rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PN_ERRRATE_EN(i), RIO_EM_PN_ERRRATE_EN_OK2U | RIO_EM_PN_ERRRATE_EN_U2OK); /* Enable port-write generation on events */ rio_write_config_32(rdev, RIO_PLM_SPx_PW_EN(i), RIO_PLM_SPx_PW_EN_OK2U | RIO_PLM_SPx_PW_EN_LINIT); } /* Set Port-Write destination port */ tmp = RIO_GET_PORT_NUM(rdev->swpinfo); rio_write_config_32(rdev, RIO_PW_ROUTE, 1 << tmp); /* Enable sending port-write event notifications */ rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PW_TX_CTRL, 0); /* set TVAL = ~50us */ rio_write_config_32(rdev, rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); return 0; }
static int idtg2_em_handler(struct rio_dev *rdev, u8 portnum) { struct rio_mport *mport = rdev->net->hport; u16 destid = rdev->rswitch->destid; u8 hopcount = rdev->rswitch->hopcount; u32 regval, em_perrdet, em_ltlerrdet; rio_mport_read_config_32(mport, destid, hopcount, rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet); if (em_ltlerrdet) { /* Service Logical/Transport Layer Error(s) */ if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) { /* Implementation specific error reported */ rio_mport_read_config_32(mport, destid, hopcount, IDT_ISLTL_ADDRESS_CAP, ®val); pr_debug("RIO: %s Implementation Specific LTL errors" \ " 0x%x @(0x%x)\n", rio_name(rdev), em_ltlerrdet, regval); /* Clear implementation specific address capture CSR */ rio_mport_write_config_32(mport, destid, hopcount, IDT_ISLTL_ADDRESS_CAP, 0); } } rio_mport_read_config_32(mport, destid, hopcount, rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet); if (em_perrdet) { /* Service Port-Level Error(s) */ if (em_perrdet & REM_PED_IMPL_SPEC) { /* Implementation Specific port error reported */ /* Get IS errors reported */ rio_mport_read_config_32(mport, destid, hopcount, IDT_PORT_ISERR_DET(portnum), ®val); pr_debug("RIO: %s Implementation Specific Port" \ " errors 0x%x\n", rio_name(rdev), regval); /* Clear all implementation specific events */ rio_mport_write_config_32(mport, destid, hopcount, IDT_PORT_ISERR_DET(portnum), 0); } } return 0; }
static int idtg2_em_handler(struct rio_dev *rdev, u8 portnum) { u32 regval, em_perrdet, em_ltlerrdet; rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet); if (em_ltlerrdet) { if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) { rio_read_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, ®val); pr_debug("RIO: %s Implementation Specific LTL errors" \ " 0x%x @(0x%x)\n", rio_name(rdev), em_ltlerrdet, regval); rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0); } } rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet); if (em_perrdet) { if (em_perrdet & REM_PED_IMPL_SPEC) { rio_read_config_32(rdev, IDT_PORT_ISERR_DET(portnum), ®val); pr_debug("RIO: %s Implementation Specific Port" \ " errors 0x%x\n", rio_name(rdev), regval); rio_write_config_32(rdev, IDT_PORT_ISERR_DET(portnum), 0); } } return 0; }