void rockchip_timer_freeze(int freeze ) { unsigned long flags; local_irq_save( flags ); if( freeze ) { clock_event_freeze_count = RK_TIMER_READVALUE(TIMER_CLKSRC); RK_TIMER_DISABLE(TIMER_CLKSRC); RK_TIMER_DISABLE(TIMER_CLKEVT); } else { RK_TIMER_SETCOUNT(TIMER_CLKSRC,clock_event_freeze_count); RK_TIMER_ENABLE(TIMER_CLKSRC); RK_TIMER_ENABLE(TIMER_CLKEVT); } clock_source_freezed = freeze; local_irq_restore(flags); }
int rockchip_usertimer_start(unsigned long usecs, int (*callback)(void)) { g_user_callback = callback; RK_TIMER_DISABLE(TIMER_CLKUSB); RK_TIMER_SETCOUNT(TIMER_CLKUSB, usecs*rockchip_apb_clk); RK_TIMER_ENABLE(TIMER_CLKUSB); return 0; }
int rockchip_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { RK_TIMER_DISABLE(TIMER_CLKEVT); RK_TIMER_SETCOUNT(TIMER_CLKEVT,cycles*rockchip_apb_clk); RK_TIMER_ENABLE(TIMER_CLKEVT); return 0; /* 0: OK */ }
static int rk29_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { do { RK_TIMER_DISABLE(TIMER_CLKEVT); RK_TIMER_SETCOUNT(TIMER_CLKEVT, cycles); RK_TIMER_ENABLE(TIMER_CLKEVT); } while (RK_TIMER_READVALUE(TIMER_CLKEVT) > cycles); return 0; }
static int rk30_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { do { RK_TIMER_DISABLE(TIMER_CLKEVT); RK_TIMER_SETCOUNT(TIMER_CLKEVT, cycles); RK_TIMER_ENABLE(TIMER_CLKEVT); } while (rk30_timer_read_current_value(TIMER_CLKEVT) > cycles); return 0; }
void rochchip_init_timer3( void ) { if( setup_irq(IRQ_NR_TIMER3,&timer3_irqa) ) { printk("request irq timer3 failed\n"); BUG(); } RK_TIMER_DISABLE(TIMER_CLKUSB); RK_TIMER_SETCOUNT(TIMER_CLKUSB, 150*1000 ); RK_TIMER_INT_ENABLE( TIMER_CLKUSB ); RK_TIMER_SETMODE_USER( TIMER_CLKUSB ); RK_TIMER_ENABLE(TIMER_CLKUSB); }
static void __init rockchip_timer_init(void) { int res; struct rockchip_clock *clock = &rockchip_clocks; struct clock_event_device *ce = &clock->clockevent; struct clocksource *cs = &clock->clocksource; /* * init at machine_rk28_mapio for udelay early use. * must after __rockchip_scu_init_hw to use rockchip_clk_get_apb. */ //rockchip_timer_clock_source_init( rockchip_clk_get_apb() ); cs->mult = clocksource_hz2mult(TIMER_SCR_CLK , cs->shift); res = clocksource_register(cs); if (res) BUG(); /* have bug */ RK_TIMER_ENABLE(TIMER_CLKSRC); // start clk source. clk_source_inited = 1; ce->mult = div_sc( TIMER_MIN_PCLK , NSEC_PER_SEC, ce->shift); ce->max_delta_ns = clockevent_delta2ns( TIMER_CLKEVT_CYCLE , ce); #ifdef CONFIG_HIGH_RES_TIMERS ce->min_delta_ns = NSEC_PER_SEC/HZ; #else ce->min_delta_ns = clockevent_delta2ns(2, ce); #endif ce->cpumask = cpumask_of_cpu(0); clockevents_register_device(ce); #if !CHIP_RK281X /* 20100623,NO NEED to use irq(debug).*/ res = setup_irq(clock->irq_source.irq, &clock->irq_source); if (res) BUG(); /* have bug */ #endif rochchip_init_timer3(); res = setup_irq(clock->irq_event.irq, &clock->irq_event); if (res) BUG(); /* have bug */ res = setup_irq(clock->irq_user.irq, &clock->irq_user); if (res) BUG(); /* have bug */ }
static void rk29_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { switch (mode) { case CLOCK_EVT_MODE_PERIODIC: do { RK_TIMER_DISABLE(TIMER_CLKEVT); RK_TIMER_SETCOUNT(TIMER_CLKEVT, 24000000/HZ - 1); RK_TIMER_ENABLE(TIMER_CLKEVT); } while (RK_TIMER_READVALUE(TIMER_CLKEVT) > (24000000/HZ - 1)); break; case CLOCK_EVT_MODE_RESUME: case CLOCK_EVT_MODE_ONESHOT: break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: RK_TIMER_DISABLE(TIMER_CLKEVT); break; } }
/* * 20091120,HSL@RK,disable irq for enable timer and set count . * */ void rockchip_timer_clocksource_suspend_resume(int suspend ) { unsigned long flags; local_irq_save( flags ); RK_TIMER_DISABLE(TIMER_CLKEVT); #if 0 if( suspend ) { RK_TIMER_SETCOUNT(TIMER_CLKEVT,RK_CHECK_VBUS_COUNT*rockchip_apb_clk); RK_TIMER_ENABLE(TIMER_CLKEVT); } else { int cyl = RK_TIMER_GETCOUNT(TIMER_CLKEVT) - RK_TIMER_READVALUE(TIMER_CLKEVT); rktimer_update_suspend_ms( CHECK_VBUS_MS*cyl / RK_TIMER_GETCOUNT(TIMER_CLKEVT) ); } S_INFO("r/s timer,load cnt=0x%x,clk_source_suspend=%ld\n" , RK_TIMER_GETCOUNT(TIMER_CLKEVT), clk_source_suspend_second); #endif local_irq_restore(flags); }
void rockchip_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { // struct rockchip_clock *clock = container_of(evt, struct rockchip_clock, clockevent); switch (mode) { case CLOCK_EVT_MODE_RESUME: RK_TIMER_ENABLE(TIMER_CLKEVT); break; case CLOCK_EVT_MODE_PERIODIC: break; case CLOCK_EVT_MODE_ONESHOT: //RK_TIMER_DISABLE(TIMER_CLKEVT); //RK_TIMER_INT_ENABLE( TIMER_CLKEVT ); //RK_TIMER_SETMODE_USER( TIMER_CLKEVT ); //RK_TIMER_ENABLE(TIMER_CLKEVT); break; case CLOCK_EVT_MODE_UNUSED: break; case CLOCK_EVT_MODE_SHUTDOWN: RK_TIMER_DISABLE(TIMER_CLKEVT); break; } }