static int hashGetHash(wolfssl_TI_Hash *hash, byte* result, word32 algo, word32 hsize) { uint32_t h[16] ; #ifndef TI_DUMMY_BUILD wolfSSL_TI_lockCCM() ; ROM_SHAMD5Reset(SHAMD5_BASE); ROM_SHAMD5ConfigSet(SHAMD5_BASE, algo); ROM_SHAMD5DataProcess(SHAMD5_BASE, (uint32_t *)hash->msg, hash->used, h); wolfSSL_TI_unlockCCM() ; #else (void) hash ; (void) algo ; #endif XMEMCPY(result, h, hsize) ; return 0 ; }
//***************************************************************************** // // Generate a hash for the given data. // //***************************************************************************** void SHA1HashGenerate(uint32_t *pui32Data, uint32_t ui32DataLength, uint32_t *pui32HashResult, bool bUseDMA) { // // Perform a soft reset of the SHA module. // ROM_SHAMD5Reset(SHAMD5_BASE); // // Clear the flags // g_bContextReadyFlag = false; g_bInputReadyFlag = false; g_bDataInDMADoneFlag = false; g_bContextOutDMADoneFlag = false; // // Enable interrupts. // ROM_SHAMD5IntEnable(SHAMD5_BASE, (SHAMD5_INT_CONTEXT_READY | SHAMD5_INT_PARTHASH_READY | SHAMD5_INT_INPUT_READY | SHAMD5_INT_OUTPUT_READY)); // // Wait for the context ready flag. // while(!g_bContextReadyFlag) { } // // Configure the SHA/MD5 module. // ROM_SHAMD5ConfigSet(SHAMD5_BASE, SHAMD5_ALGO_SHA1); // // Use DMA to write the data into the SHA/MD5 module. // if(bUseDMA) { // // Enable DMA done interrupts. // ROM_SHAMD5IntEnable(SHAMD5_BASE, (SHAMD5_INT_DMA_CONTEXT_IN | SHAMD5_INT_DMA_DATA_IN | SHAMD5_INT_DMA_CONTEXT_OUT)); if(ui32DataLength != 0) { // // Setup the DMA module to copy data in. // ROM_uDMAChannelAssign(UDMA_CH5_SHAMD50DIN); ROM_uDMAChannelAttributeDisable(UDMA_CH5_SHAMD50DIN, UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK); ROM_uDMAChannelControlSet(UDMA_CH5_SHAMD50DIN | UDMA_PRI_SELECT, UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_NONE | UDMA_ARB_16 | UDMA_DST_PROT_PRIV); ROM_uDMAChannelTransferSet(UDMA_CH5_SHAMD50DIN | UDMA_PRI_SELECT, UDMA_MODE_BASIC, (void *)pui32Data, (void *)(SHAMD5_BASE + SHAMD5_O_DATA_0_IN), ui32DataLength / 4); ROM_uDMAChannelEnable(UDMA_CH5_SHAMD50DIN); UARTprintf("Data in DMA request enabled.\n"); } // // Setup the DMA module to copy the hash out. // ROM_uDMAChannelAssign(UDMA_CH6_SHAMD50COUT); ROM_uDMAChannelAttributeDisable(UDMA_CH6_SHAMD50COUT, UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK); ROM_uDMAChannelControlSet(UDMA_CH6_SHAMD50COUT | UDMA_PRI_SELECT, UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_8 | UDMA_SRC_PROT_PRIV); ROM_uDMAChannelTransferSet(UDMA_CH6_SHAMD50COUT | UDMA_PRI_SELECT, UDMA_MODE_BASIC, (void *)(SHAMD5_BASE + SHAMD5_O_IDIGEST_A), (void *)pui32HashResult, 5); ROM_uDMAChannelEnable(UDMA_CH6_SHAMD50COUT); UARTprintf("Context out DMA request enabled.\n"); // // Enable DMA in the SHA/MD5 module. // ROM_SHAMD5DMAEnable(SHAMD5_BASE); // // Write the length. // ROM_SHAMD5HashLengthSet(SHAMD5_BASE, ui32DataLength); if(ui32DataLength != 0) { // // Wait for the DMA done interrupt. // while(!g_bDataInDMADoneFlag) { } } // // Wait for the next DMA done interrupt. // while(!g_bContextOutDMADoneFlag) { } // // Disable DMA requests. // ROM_SHAMD5DMADisable(SHAMD5_BASE); } // // Perform hash computation by copying the data with the CPU. // else { // // Perform the hashing operation // ROM_SHAMD5DataProcess(SHAMD5_BASE, pui32Data, ui32DataLength, pui32HashResult); } }