void pdlibSPI_ConfigureSPIInterface(unsigned char ucSSI) { g_SSI = ucSSI; #ifdef PART_LM4F120H5QR if(g_SSI < 6) { /* Enable clock for SSI */ ROM_SysCtlPeripheralEnable(g_SSIModule[ucSSI][SSIPERIPH]); /* Disable SSI module */ ROM_SSIDisable(g_SSIModule[ucSSI][SSIBASE]); /* Enable Clock for GPIO port used */ ROM_SysCtlPeripheralEnable(g_GPIOConfigure[ucSSI][GPIOPERIPH]); /* Configure GPIO pins */ ROM_GPIOPinConfigure(g_GPIOConfigure[ucSSI][SSICLK]); ROM_GPIOPinConfigure(g_GPIOConfigure[ucSSI][SSIFSS]); ROM_GPIOPinConfigure(g_GPIOConfigure[ucSSI][SSIRX]); ROM_GPIOPinConfigure(g_GPIOConfigure[ucSSI][SSITX]); ROM_GPIOPinTypeSSI(g_GPIOConfigure[ucSSI][GPIOBASE], g_GPIOConfigure[ucSSI][GPIOPINS]); /* Configure SSI */ ROM_SSIClockSourceSet(g_SSIModule[ucSSI][SSIBASE], SSI_CLOCK_SYSTEM); ROM_SSIConfigSetExpClk(g_SSIModule[ucSSI][SSIBASE], SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 500000, 8); ROM_SSIEnable(g_SSIModule[ucSSI][SSIBASE]); /* Clear initial data */ while(ROM_SSIDataGetNonBlocking(g_SSIModule[ucSSI][SSIBASE], (unsigned long*)&g_plRxData[0])); /* HWREG(g_SSIModule[ucSSI][SSIBASE] + SSI_O_CPSR) = 8; HWREG(g_SSIModule[ucSSI][SSIBASE] + SSI_O_CR0) &= ~(SSI_CR0_SPO | SSI_CR0_SPH); HWREG(g_SSIModule[ucSSI][SSIBASE] + SSI_O_CR0) |= 0x00; */ } #endif }
void SPIClass::begin(uint8_t ssPin) { unsigned long initialData = 0; if(SSIModule == NOT_ACTIVE) { SSIModule = BOOST_PACK_SPI; } ROM_SysCtlPeripheralEnable(g_ulSSIPeriph[SSIModule]); ROM_SSIDisable(SSIBASE); ROM_GPIOPinConfigure(g_ulSSIConfig[SSIModule][0]); ROM_GPIOPinConfigure(g_ulSSIConfig[SSIModule][1]); ROM_GPIOPinConfigure(g_ulSSIConfig[SSIModule][2]); ROM_GPIOPinConfigure(g_ulSSIConfig[SSIModule][3]); ROM_GPIOPinTypeSSI(g_ulSSIPort[SSIModule], g_ulSSIPins[SSIModule]); /* Polarity Phase Mode 0 0 SSI_FRF_MOTO_MODE_0 0 1 SSI_FRF_MOTO_MODE_1 1 0 SSI_FRF_MOTO_MODE_2 1 1 SSI_FRF_MOTO_MODE_3 */ slaveSelect = ssPin; pinMode(slaveSelect, OUTPUT); /* * Default to * System Clock, SPI_MODE_0, MASTER, * 4MHz bit rate, and 8 bit data */ ROM_SSIClockSourceSet(SSIBASE, SSI_CLOCK_SYSTEM); ROM_SSIConfigSetExpClk(SSIBASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 4000000, 8); ROM_SSIEnable(SSIBASE); //clear out any initial data that might be present in the RX FIFO while(ROM_SSIDataGetNonBlocking(SSIBASE, &initialData)); }
void SPIClass::end() { ROM_SSIDisable(SSIBASE); }
void SSI3DMASlaveClass::end() { ROM_SSIDisable(SSI3_BASE); }
void SPIClass::end(uint8_t ssPin) { ROM_SSIDisable(SSIBASE); }