/**
* @brief Configure CPU clock.
* @param None
* @retval None
*/
void ClockConfigure ( void )
{
/* Enable HSE (High Speed External) clock */
RST_CLK_HSEconfig(RST_CLK_HSE_ON);
if (RST_CLK_HSEstatus() == ERROR) {
while (1);
}
/* Configures the CPU_PLL clock source */
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSEdiv1, RST_CLK_CPU_PLLmul10);
/* Enables the CPU_PLL */
RST_CLK_CPU_PLLcmd(ENABLE);
if (RST_CLK_CPU_PLLstatus() == ERROR) {
while (1);
}
/* Enables the RST_CLK_PCLK_EEPROM */
RST_CLK_PCLKcmd(RST_CLK_PCLK_EEPROM, ENABLE);
/* Sets the code latency value */
EEPROM_SetLatency(EEPROM_Latency_3);
/* Select the CPU_PLL output as input for CPU_C3_SEL */
RST_CLK_CPU_PLLuse(ENABLE);
/* Set CPUClk Prescaler */
RST_CLK_CPUclkPrescaler(RST_CLK_CPUclkDIV1);
/* Select the CPU clock source */
RST_CLK_CPUclkSelection(RST_CLK_CPUclkCPU_C3);
}
/* Frequencies setup */
void Setup_CPU_Clock(void)
{
/* Enable HSE */
RST_CLK_HSEconfig(RST_CLK_HSE_ON);
if (RST_CLK_HSEstatus() != SUCCESS)
{
/* Trap */
while (1)
{
}
}
/* CPU_C1_SEL = HSE */
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSEdiv1, RST_CLK_CPU_PLLmul10);
RST_CLK_CPU_PLLcmd(ENABLE);
if (RST_CLK_CPU_PLLstatus() != SUCCESS)
{
/* Trap */
while (1)
{
}
}
/* CPU_C3_SEL = CPU_C2_SEL */
RST_CLK_CPUclkPrescaler(RST_CLK_CPUclkDIV1);
/* CPU_C2_SEL = PLL */
RST_CLK_CPU_PLLuse(ENABLE);
/* HCLK_SEL = CPU_C3_SEL */
RST_CLK_CPUclkSelection(RST_CLK_CPUclkCPU_C3);
}
void BRD_Clock_Init_HSE_PLL(uint32_t PLL_Mul_sub1) // 128 MHz
{
// Сброс настроек системы тактирования
RST_CLK_DeInit();
// Инициализация генератора на внешнем кварцевом резонаторе (HSE)
RST_CLK_HSEconfig (RST_CLK_HSE_ON);
while (RST_CLK_HSEstatus() != SUCCESS);
// Инициализация блока PLL
// Включение использования PLL
RST_CLK_CPU_PLLcmd (ENABLE);
// Настройка источника и коэффициента умножения PLL
// (CPU_C1_SEL = HSE)
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSEdiv1, PLL_Mul_sub1);
while (RST_CLK_CPU_PLLstatus() != SUCCESS);
// Подключение PLL к системе тактирования
// (CPU_C2_SEL = PLLCPUo)
RST_CLK_CPU_PLLuse (ENABLE);
// Настройка коэффициента деления блока CPU_C3_SEL
// (CPU_C3_SEL = CPU_C2)
RST_CLK_CPUclkPrescaler (RST_CLK_CPUclkDIV1);
// Использование процессором сигнала CPU_C3
// (HCLK = CPU_C3)
RST_CLK_CPUclkSelection (RST_CLK_CPUclkCPU_C3);
// Update System Clock
BRD_CPU_CLK = HSE_Value * (PLL_Mul_sub1 + 1);
}
//==================================================================================
void PLL_init(void)
{
RST_CLK_HSEconfig(RST_CLK_HSE_ON);
while(RST_CLK_HSEstatus() == ERROR);
RST_CLK_CPUclkSelection(RST_CLK_CPUclkCPU_C3);
MDR_RST_CLK->CPU_CLOCK |= 2;
RST_CLK_HSIcmd(DISABLE);
}
void BRD_Clock_Init_HSE_PLL(uint32_t PLL_Mul_sub1)
{
uint32_t freqCPU;
RST_CLK_DeInit();
/* Enable HSE (High Speed External) clock */
RST_CLK_HSEconfig(RST_CLK_HSE_ON);
while (RST_CLK_HSEstatus() != SUCCESS);
// /* Configures the CPU_PLL clock source */
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSEdiv1, PLL_Mul_sub1);
/* Enables the CPU_PLL */
RST_CLK_CPU_PLLcmd(ENABLE);
while (RST_CLK_CPU_PLLstatus() == ERROR);
/* Enables the RST_CLK_PCLK_EEPROM */
RST_CLK_PCLKcmd(RST_CLK_PCLK_EEPROM, ENABLE);
/* Sets the code latency value */
freqCPU = HSE_Value * (PLL_Mul_sub1 + 1);
if (freqCPU < 25E+6)
EEPROM_SetLatency(EEPROM_Latency_0);
else if (freqCPU < 50E+6)
EEPROM_SetLatency(EEPROM_Latency_1);
else if (freqCPU < 75E+6)
EEPROM_SetLatency(EEPROM_Latency_2);
else if (freqCPU < 100E+6)
EEPROM_SetLatency(EEPROM_Latency_3);
else if (freqCPU < 125E+6)
EEPROM_SetLatency(EEPROM_Latency_4);
else //if (PLL_Mul * HSE_Value <= 150E+6)
EEPROM_SetLatency(EEPROM_Latency_5);
// Additional Supply Power
if (freqCPU < 40E+6)
SetSelectRI(RI_till_40MHz);
else if (freqCPU < 80E+6)
SetSelectRI(RI_till_80MHz);
else
SetSelectRI(RI_over_80MHz);
/* Select the CPU_PLL output as input for CPU_C3_SEL */
RST_CLK_CPU_PLLuse(ENABLE);
/* Set CPUClk Prescaler */
RST_CLK_CPUclkPrescaler(RST_CLK_CPUclkDIV1);
/* Select the CPU clock source */
RST_CLK_CPUclkSelection(RST_CLK_CPUclkCPU_C3);
// Update System Clock
BRD_CPU_CLK = freqCPU;
}
void BRD_Clock_Init_HSE_dir(void)
{
RST_CLK_DeInit();
/* Enable HSE (High Speed External) clock */
RST_CLK_HSEconfig(RST_CLK_HSE_ON);
while (RST_CLK_HSEstatus() != SUCCESS);
RST_CLK_CPU_PLLuse(DISABLE);
RST_CLK_CPUclkPrescaler(RST_CLK_CPUclkDIV1);
/* Select the CPU clock source */
RST_CLK_CPUclkSelection(RST_CLK_CPUclkCPU_C3);
// Update System Clock
BRD_CPU_CLK = HSE_Value;
}
//-----------------------------------------------------------------//
// Setup clocks
// CPU core clock (HCLK) = 32 MHz clock from 4 MHz HSE
// ADC clock = 4 MHz clock from 4 MHz HSE
//-----------------------------------------------------------------//
void Setup_CPU_Clock(void)
{
// Enable HSE
RST_CLK_HSEconfig(RST_CLK_HSE_ON);
if (RST_CLK_HSEstatus() != SUCCESS)
{
while (1) {} // Trap
}
//-------------------------------//
// Setup CPU PLL and CPU_C1_SEL
// CPU_C1 = HSE, PLL = x8
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSEdiv1, RST_CLK_CPU_PLLmul8);
RST_CLK_CPU_PLLcmd(ENABLE);
if (RST_CLK_CPU_PLLstatus() != SUCCESS)
{
while (1) {} // Trap
}
// Setup CPU_C2 and CPU_C3
// CPU_C3 = CPU_C2
RST_CLK_CPUclkPrescaler(RST_CLK_CPUclkDIV1);
// CPU_C2 = CPU PLL output
RST_CLK_CPU_PLLuse(ENABLE);
// Switch to CPU_C3
// HCLK = CPU_C3
RST_CLK_CPUclkSelection(RST_CLK_CPUclkCPU_C3);
//-------------------------------//
// Setup ADC clock
// ADC_C2 = CPU_C1
RST_CLK_ADCclkSelection(RST_CLK_ADCclkCPU_C1);
// ADC_C3 = ADC_C2
RST_CLK_ADCclkPrescaler(RST_CLK_ADCclkDIV1);
// Enable ADC_CLK
RST_CLK_ADCclkEnable(ENABLE);
// Update system clock variable
SystemCoreClockUpdate();
// Enable clock on all ports (macro are defined in systemfunc.h)
RST_CLK_PCLKcmd(ALL_PORTS_CLK, ENABLE);
// Enable clock on peripheral blocks used in design
RST_CLK_PCLKcmd(PERIPHERALS_CLK ,ENABLE);
}
void prvSetupHardware( void )
{
PORT_InitTypeDef PORT_InitStructure;
UART_InitTypeDef UART_InitStructure;
//SSP_InitTypeDef SPI_InitStructure;
TIMER_CntInitTypeDef sTIM_CntInit;
// TIMER_ChnInitTypeDef sTIM_ChnInit;
//CLK
/* Enable HSE clock oscillator */
RST_CLK_HSEconfig(RST_CLK_HSE_ON);
while(RST_CLK_HSEstatus() == ERROR);
RST_CLK_CPUclkSelection(RST_CLK_CPUclkCPU_C3);
MDR_RST_CLK -> CPU_CLOCK |= 2;//CPU_C1 set HSE
RST_CLK_HSIcmd(DISABLE);
/* Enable the RTCHSE clock on all ports */
RST_CLK_PCLKcmd(ALL_PORTS_CLK, ENABLE);
PORT_StructInit(&PORT_InitStructure);//reset struct
/************************ LCD Initialization *************************/
/* Configure PORTA pins for data transfer to/from LCD */
PORT_InitStructure.PORT_Pin = LCD_DATA_BUS_8;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_PORT;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_SLOW;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_Init(MDR_PORTA, &PORT_InitStructure);
/* Configure PORTE pin4 and pin5 for LCD crystals control */
PORT_InitStructure.PORT_Pin = KS0108_CS1 | KS0108_CS2 | KS0108_RS;
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_Init(MDR_PORTE, &PORT_InitStructure);
PORT_Init(MDR_PORTE, &PORT_InitStructure);
PORT_InitStructure.PORT_Pin = KS0108_EN | KS0108_RW | KS0108_RES;
PORT_Init(MDR_PORTC, &PORT_InitStructure);
PORT_SetBits(MDR_PORTA, LCD_DATA_BUS_8);
PORT_SetBits(MDR_PORTE, KS0108_CS1 | KS0108_CS2 | KS0108_RS);
PORT_SetBits(MDR_PORTC, KS0108_EN | KS0108_RW | KS0108_RES);
//Timer1
// TIMER1
RST_CLK_PCLKcmd(RST_CLK_PCLK_TIMER1,ENABLE);
/* Reset all TIMER1 settings */
TIMER_DeInit(MDR_TIMER1);
TIMER_BRGInit(MDR_TIMER1,TIMER_HCLKdiv1);
/* TIM1 configuration ------------------------------------------------*/
/* Initializes the TIMERx Counter ------------------------------------*/
sTIM_CntInit.TIMER_IniCounter = 0;
sTIM_CntInit.TIMER_Prescaler = 150;//
sTIM_CntInit.TIMER_Period = 82;
sTIM_CntInit.TIMER_CounterMode = TIMER_CntMode_ClkFixedDir;
sTIM_CntInit.TIMER_CounterDirection = TIMER_CntDir_Up;
sTIM_CntInit.TIMER_EventSource = TIMER_EvSrc_None;
sTIM_CntInit.TIMER_FilterSampling = TIMER_FDTS_TIMER_CLK_div_1;
sTIM_CntInit.TIMER_ARR_UpdateMode = TIMER_ARR_Update_Immediately;
sTIM_CntInit.TIMER_ETR_FilterConf = TIMER_Filter_1FF_at_TIMER_CLK;
sTIM_CntInit.TIMER_ETR_Prescaler = TIMER_ETR_Prescaler_None;
sTIM_CntInit.TIMER_ETR_Polarity = TIMER_ETRPolarity_NonInverted;
sTIM_CntInit.TIMER_BRK_Polarity = TIMER_BRKPolarity_NonInverted;
TIMER_CntInit (MDR_TIMER1,&sTIM_CntInit);
NVIC_EnableIRQ(Timer1_IRQn);
TIMER_ITConfig(MDR_TIMER1,TIMER_STATUS_CNT_ARR, ENABLE);
/* TMR1 enable */
TIMER_Cmd (MDR_TIMER1,ENABLE);
// TIMER2
RST_CLK_PCLKcmd(RST_CLK_PCLK_TIMER2,ENABLE);
/* Reset all TIMER1 settings */
TIMER_DeInit(MDR_TIMER2);
TIMER_BRGInit(MDR_TIMER2,TIMER_HCLKdiv1);
/* TIM2 configuration ------------------------------------------------*/
/* Initializes the TIMERx Counter ------------------------------------*/
sTIM_CntInit.TIMER_IniCounter = 0;
sTIM_CntInit.TIMER_Prescaler = 0xf;//
sTIM_CntInit.TIMER_Period = 0xffff;
sTIM_CntInit.TIMER_CounterMode = TIMER_CntMode_ClkFixedDir;
sTIM_CntInit.TIMER_CounterDirection = TIMER_CntDir_Up;
sTIM_CntInit.TIMER_EventSource = TIMER_EvSrc_None;
sTIM_CntInit.TIMER_FilterSampling = TIMER_FDTS_TIMER_CLK_div_1;
sTIM_CntInit.TIMER_ARR_UpdateMode = TIMER_ARR_Update_Immediately;
sTIM_CntInit.TIMER_ETR_FilterConf = TIMER_Filter_1FF_at_TIMER_CLK;
sTIM_CntInit.TIMER_ETR_Prescaler = TIMER_ETR_Prescaler_None;
sTIM_CntInit.TIMER_ETR_Polarity = TIMER_ETRPolarity_NonInverted;
sTIM_CntInit.TIMER_BRK_Polarity = TIMER_BRKPolarity_NonInverted;
TIMER_CntInit (MDR_TIMER2,&sTIM_CntInit);
NVIC_EnableIRQ(Timer2_IRQn);
TIMER_ITConfig(MDR_TIMER2,TIMER_STATUS_CNT_ARR, ENABLE);
/* TMR2 enable */
TIMER_Cmd (MDR_TIMER2,ENABLE);
// TIMER3
RST_CLK_PCLKcmd(RST_CLK_PCLK_TIMER3,ENABLE);
/* Reset all TIMER3 settings */
TIMER_DeInit(MDR_TIMER3);
TIMER_BRGInit(MDR_TIMER3,TIMER_HCLKdiv1);
/* TIM3 configuration ------------------------------------------------*/
/* Initializes the TIMERx Counter ------------------------------------*/
sTIM_CntInit.TIMER_IniCounter = 0;
sTIM_CntInit.TIMER_Prescaler = 0;
sTIM_CntInit.TIMER_Period = 0xFFFF;
sTIM_CntInit.TIMER_CounterMode = TIMER_CntMode_EvtFixedDir;
sTIM_CntInit.TIMER_CounterDirection = TIMER_CntDir_Up;
sTIM_CntInit.TIMER_EventSource = TIMER_EvSrc_CH1;
sTIM_CntInit.TIMER_FilterSampling = TIMER_FDTS_TIMER_CLK_div_1;
sTIM_CntInit.TIMER_ARR_UpdateMode = TIMER_ARR_Update_Immediately;
sTIM_CntInit.TIMER_ETR_FilterConf = TIMER_Filter_1FF_at_TIMER_CLK;
sTIM_CntInit.TIMER_ETR_Prescaler = TIMER_ETR_Prescaler_None;
sTIM_CntInit.TIMER_ETR_Polarity = TIMER_ETRPolarity_NonInverted;
sTIM_CntInit.TIMER_BRK_Polarity = TIMER_BRKPolarity_NonInverted;
TIMER_CntInit (MDR_TIMER3,&sTIM_CntInit);
// NVIC_EnableIRQ(Timer3_IRQn);
// TIMER_ITConfig(MDR_TIMER3,TIMER_STATUS_CNT_ARR, ENABLE);
/* Enable TIMER3 */
TIMER_Cmd(MDR_TIMER3,ENABLE);
/************************ UART1 Initialization *************************/
PORT_StructInit(&PORT_InitStructure);//reset struct
PORT_InitStructure.PORT_Pin = PORT_Pin_12|PORT_Pin_13;//RX TX
PORT_InitStructure.PORT_FUNC = PORT_FUNC_OVERRID;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_SLOW;
PORT_Init(MDR_PORTE, &PORT_InitStructure);
PORT_InitStructure.PORT_Pin = PORT_Pin_14;//EN RS485
PORT_InitStructure.PORT_OE =PORT_OE_OUT;
PORT_InitStructure.PORT_PD = PORT_PD_OPEN;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_PORT;
PORT_Init(MDR_PORTE, &PORT_InitStructure);
RS485_TX_OFF;
//UART1
RST_CLK_PCLKcmd(RST_CLK_PCLK_UART1,ENABLE);
/* Set the HCLK division factor = 1 for UART1,UART2*/
UART_BRGInit(MDR_UART1, UART_HCLKdiv1);
UART_DeInit(MDR_UART1);
/* Disable interrupt on UART1 */
NVIC_DisableIRQ(UART1_IRQn);
/* Initialize UART_InitStructure */
UART_InitStructure.UART_BaudRate = 38400;
UART_InitStructure.UART_WordLength = UART_WordLength8b;
UART_InitStructure.UART_StopBits = UART_StopBits1;//PKDU2 niobyi
UART_InitStructure.UART_Parity = UART_Parity_No;
UART_InitStructure.UART_FIFOMode = UART_FIFO_OFF;
UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_RXE | UART_HardwareFlowControl_TXE;
/* Configure UART1 parameters*/
UART_Init(MDR_UART1,&UART_InitStructure);
NVIC_EnableIRQ(UART1_IRQn);
UART_ITConfig(MDR_UART1,UART_IT_RX, ENABLE);
/* Enables UART1 peripheral */
UART_Cmd(MDR_UART1,ENABLE);
//PORT
/************************ Joystick Initialization *************************/
/* Configure PORTC pins 10..14 for input to handle joystick events */
PORT_StructInit(&PORT_InitStructure);//reset struct
PORT_InitStructure.PORT_Pin = ( PORT_Pin_10 | PORT_Pin_11 | PORT_Pin_12 |
PORT_Pin_13 | PORT_Pin_14 );
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_PORT;
PORT_InitStructure.PORT_SPEED = PORT_OUTPUT_OFF;
PORT_Init( MDR_PORTC, &PORT_InitStructure );
/************************ LEDs Initialization *************************/
PORT_StructInit( &PORT_InitStructure );//reset struct
/* Configure PORTD pins 10..14 for output to switch LEDs on/off */
PORT_InitStructure.PORT_Pin = LEDs_PINs;
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_PORT;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_SLOW;
PORT_Init( MDR_PORTD, &PORT_InitStructure );
/* All LEDs switch off */
PORT_ResetBits(MDR_PORTD, LEDs_PINs);
}
void main(void)
#endif
{
RST_CLK_PCLKcmd(RST_CLK_PCLK_PORTD, ENABLE);
/* Configure all unused PORT pins to low power consumption */
PORT_StructInit(&PORT_InitStructure);
PORT_InitStructure.PORT_Pin = (PORT_Pin_All & ~(PORT_Pin_10 | PORT_Pin_11 |
PORT_Pin_12 | PORT_Pin_13 |
PORT_Pin_14));
PORT_Init(MDR_PORTD, &PORT_InitStructure);
/* Configure PORTD pins 10..14 for output to switch LEDs on/off */
PORT_InitStructure.PORT_Pin = (PORT_Pin_10 | PORT_Pin_11 | PORT_Pin_12 |
PORT_Pin_13 | PORT_Pin_14);
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_PORT;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_SLOW;
PORT_Init(MDR_PORTD, &PORT_InitStructure);
/* Consequently turn all three used LEDs on and off */
LEDOn(LED1);
Delay(4*BLINK_DELAY);
LEDOff(LED1);
Delay(4*BLINK_DELAY);
LEDOn(LED2);
Delay(4*BLINK_DELAY);
LEDOff(LED2);
Delay(4*BLINK_DELAY);
LEDOn(LED3);
Delay(4*BLINK_DELAY);
LEDOff(LED3);
Delay(4*BLINK_DELAY);
/* Infinite loop that demonstrates different input clock sources using */
while (1)
{
/* Set RST_CLK to default */
RST_CLK_DeInit();
RST_CLK_PCLKcmd(RST_CLK_PCLK_PORTD, ENABLE);
/* 1. CPU_CLK = HSI clock */
/* Enable HSI clock source */
RST_CLK_HSIcmd(ENABLE);
/* Switch LED2 on and wait for HSI ready status */
LEDOn(LED2);
Delay(BLINK_DELAY);
if (RST_CLK_HSIstatus() == SUCCESS) /* Good HSI clock */
{
/* Switch LED2 off */
LEDOff(LED2);
/* Select HSI clock on the CPU clock MUX */
RST_CLK_CPUclkSelection(RST_CLK_CPUclkHSI);
/* LED1 blinking with HSI clock as input clock source */
BlinkLED1(BLINK_NUM, BLINK_DELAY);
}
else /* HSI timeout */
{
IndicateError();
}
/* 2. CPU_CLK = HSI/2 clock */
/* Enable HSI clock source */
RST_CLK_HSIcmd(ENABLE);
/* Disable CPU_PLL */
RST_CLK_CPU_PLLcmd(DISABLE);
/* Select HSI/2 clock as CPU_PLL input clock source */
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSIdiv2, 1);
/* Switch LED2 on and wait for HSI ready status */
LEDOn(LED2);
Delay(BLINK_DELAY);
if (RST_CLK_HSIstatus() == SUCCESS) /* Good HSI clock */
{
/* Switch LED2 off */
LEDOff(LED2);
/* Set CPU_C3_prescaler to 1 */
RST_CLK_CPUclkPrescaler(RST_CLK_CPUclkDIV1);
/* Switch CPU_C2_SEL to CPU_C1 clock instead of CPU_PLL output */
RST_CLK_CPU_PLLuse(DISABLE);
/* LED1 blinking with HSI/2 clock as input clock source */
BlinkLED1(BLINK_NUM, BLINK_DELAY);
}
else /* HSI timeout */
{
IndicateError();
}
/* 3. CPU_CLK = 7*HSE/2 clock */
/* Enable HSE clock oscillator */
RST_CLK_HSEconfig(RST_CLK_HSE_ON);
/* Switch LED2 on and wait for HSE ready status */
LEDOn(LED2);
Delay(BLINK_DELAY);
if (RST_CLK_HSEstatus() == SUCCESS) /* Good HSE clock */
{
/* Select HSE clock as CPU_PLL input clock source */
/* Set PLL multiplier to 7 */
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSEdiv1, 7);
/* Enable CPU_PLL */
RST_CLK_CPU_PLLcmd(ENABLE);
/* Switch LED2 on and wait for PLL ready status */
if (RST_CLK_HSEstatus() == SUCCESS) /* Good CPU PLL */
{
/* Switch LED2 off */
LEDOff(LED2);
/* Set CPU_C3_prescaler to 2 */
RST_CLK_CPUclkPrescaler(RST_CLK_CPUclkDIV2);
/* Set CPU_C2_SEL to CPU_PLL output instead of CPU_C1 clock */
RST_CLK_CPU_PLLuse(ENABLE);
/* Select CPU_C3 clock on the CPU clock MUX */
RST_CLK_CPUclkSelection(RST_CLK_CPUclkCPU_C3);
/* LED1 blinking with 7*HSE/2 clock as input clock source */
BlinkLED1(BLINK_NUM, BLINK_DELAY);
}
else /* CPU_PLL timeout */
{
IndicateError();
}
}
else /* HSE timeout */
{
IndicateError();
}
/* 4. CPU_CLK = LSI clock */
/* Enable LSI clock source */
RST_CLK_LSIcmd(ENABLE);
/* Switch LED2 on and wait for LSI ready status */
LEDOn(LED2);
Delay(BLINK_DELAY);
if (RST_CLK_LSIstatus() == SUCCESS) /* Good LSI clock */
{
/* Switch LED2 off */
LEDOff(LED2);
/* Select LSI clock on the CPU clock MUX */
RST_CLK_CPUclkSelection(RST_CLK_CPUclkLSI);
/* LED1 blinking with LSI clock as input clock source */
BlinkLED1(BLINK_NUM, BLINK_DELAY);
}
else /* LSI timeout */
{
IndicateError();
}
}
}