static USHORT
ShiftInBits(
struct rtl8190_priv *priv)
{
ULONG ioaddr = priv->pshare->ioaddr;
USHORT x,d,i;
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~( EEDO | EEDI);
d = 0;
for(i=0; i<16; i++)
{
d = d << 1;
RaiseClock(priv, &x);
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EEDI);
if(x & EEDO)
d |= 1;
LowerClock(priv, &x);
}
return d;
}
u16 rtl_shift_in_bits(void __iomem *ioaddr)
{
u8 x;
u16 d, i;
x = RTL_R8(Cfg9346);
x &= ~(Cfg9346_EEDI | Cfg9346_EEDO);
d = 0;
for (i = 0; i < 16; i++) {
d = d << 1;
rtl_raise_clock(&x, ioaddr);
x = RTL_R8(Cfg9346);
x &= ~Cfg9346_EEDI;
if (x & Cfg9346_EEDO)
d |= 1;
rtl_lower_clock(&x, ioaddr);
}
return d;
}
static void set_swGpio_LED(struct rtl8192cd_priv *priv, unsigned int ledNum, int flag)
{
unsigned int ledItem; /* parameter to decode GPIO item */
if (ledNum >= SWLED_GPIORT_CNT)
return;
ledItem = SWLED_GPIORT_ITEM(LED_ROUTE, ledNum);
if (ledItem & SWLED_GPIORT_ENABLEMSK)
{
/* get the corresponding information (GPIO number/Active high or low) of LED */
int gpio;
int activeMode; /* !=0 : Active High, ==0 : Active Low */
gpio = ledItem & SWLED_GPIORT_RTBITMSK;
activeMode = ledItem & SWLED_GPIORT_HLMSK;
if (flag) { /* Turn ON LED */
if (activeMode) /* Active High */
RTL_W8(0x90, RTL_R8(0x90) | BIT(gpio));
else /* Active Low */
RTL_W8(0x90, RTL_R8(0x90) &~ BIT(gpio));
}
else { /* Turn OFF LED */
if (activeMode) /* Active High */
RTL_W8(0x90, RTL_R8(0x90) &~ BIT(gpio));
else /* Active Low */
RTL_W8(0x90, RTL_R8(0x90) | BIT(gpio));
}
}
}
static int ethtool_get_settings(struct net_device *netdev,struct ethtool_cmd *ecmd){
struct r1000_private *priv = (struct r1000_private *)(netdev->priv);
unsigned long ioaddr = priv->ioaddr;
unsigned int bmcr = R1000_READ_GMII_REG(ioaddr,PHY_STAT_REG);
unsigned int bmsr = R1000_READ_GMII_REG(ioaddr,PHY_AUTO_NEGO_REG);
unsigned int gbcr = R1000_READ_GMII_REG(ioaddr,PHY_1000_CTRL_REG);
ecmd->supported = (SUPPORTED_10baseT_Half|
SUPPORTED_10baseT_Full|
SUPPORTED_100baseT_Half|
SUPPORTED_100baseT_Full|
SUPPORTED_1000baseT_Full|
SUPPORTED_Autoneg|
SUPPORTED_TP);
ecmd->advertising = ADVERTISED_TP;
if(bmsr&ADVERTISE_10HALF)
ecmd->advertising |= ADVERTISED_10baseT_Half;
if(bmsr&ADVERTISE_10FULL)
ecmd->advertising |= ADVERTISED_10baseT_Full;
if(bmsr&ADVERTISE_100HALF)
ecmd->advertising |= ADVERTISED_100baseT_Half;
if(bmsr&ADVERTISE_100FULL)
ecmd->advertising |= ADVERTISED_100baseT_Full;
if(gbcr&PHY_Cap_1000_Full)
ecmd->advertising |= ADVERTISED_1000baseT_Full;
if(bmcr&PHY_Enable_Auto_Nego)
ecmd->advertising |= ADVERTISED_Autoneg;
ecmd->port = PORT_TP;
if(priv->mcfg == MCFG_METHOD_1)
ecmd->transceiver = XCVR_EXTERNAL;
else
ecmd->transceiver = XCVR_INTERNAL;
if(RTL_R8(PHYstatus)&LinkStatus){
if(RTL_R8(PHYstatus)&_1000Mbps)
ecmd->speed = SPEED_1000;
else if(RTL_R8(PHYstatus)&_100Mbps)
ecmd->speed = SPEED_100;
else if(RTL_R8(PHYstatus)&_10Mbps)
ecmd->speed = SPEED_10;
if(RTL_R8(PHYstatus)&FullDup)
ecmd->duplex = DUPLEX_FULL;
else
ecmd->duplex = DUPLEX_HALF;
}else{
ecmd->speed = -1;
ecmd->duplex = -1;
}
ecmd->autoneg = AUTONEG_ENABLE;
return 0;
}
//-------------------------------------------------------------------
//rtl_eeprom_type():
// tell the eeprom type
//return value:
// 0: the eeprom type is 93C46
// 1: the eeprom type is 93C56 or 93C66
//-------------------------------------------------------------------
void rtl_eeprom_type(struct rtl8168_private *tp)
{
void __iomem *ioaddr=tp->mmio_addr;
u16 magic = 0;
if (tp->mcfg == CFG_METHOD_DEFAULT)
goto out_no_eeprom;
if(RTL_R8(0xD2)&0x04) {
//not support
//tp->eeprom_type = EEPROM_TWSI;
//tp->eeprom_len = 256;
goto out_no_eeprom;
} else if(RTL_R32(RxConfig) & RxCfg_9356SEL) {
tp->eeprom_type = EEPROM_TYPE_93C56;
tp->eeprom_len = 256;
} else {
tp->eeprom_type = EEPROM_TYPE_93C46;
tp->eeprom_len = 128;
}
magic = rtl_eeprom_read_sc(tp, 0);
out_no_eeprom:
if ((magic != 0x8129) && (magic != 0x8128)) {
tp->eeprom_type = EEPROM_TYPE_NONE;
tp->eeprom_len = 0;
}
}
void rtl_shift_out_bits(int data, int count, void __iomem *ioaddr)
{
u8 x;
int mask;
mask = 0x01 << (count - 1);
x = RTL_R8(Cfg9346);
x &= ~(Cfg9346_EEDI | Cfg9346_EEDO);
do {
if (data & mask)
x |= Cfg9346_EEDI;
else
x &= ~Cfg9346_EEDI;
RTL_W8(Cfg9346, x);
udelay(RTL_CLOCK_RATE);
rtl_raise_clock(&x, ioaddr);
rtl_lower_clock(&x, ioaddr);
mask = mask >> 1;
} while(mask);
x &= ~Cfg9346_EEDI;
RTL_W8(Cfg9346, x);
}
static VOID
WriteEEprom(
struct rtl8190_priv *priv,
UCHAR AddressSize,
USHORT reg,
USHORT data)
{
ULONG ioaddr = priv->pshare->ioaddr;
UCHAR x;
// select EEPROM, mask off ASIC and reset bits, set EECS
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EEDI | EEDO | EESK | CR9346_EEM0);
x |= CR9346_EEM1 | EECS;
RTL_W8(CSR_EEPROM_CONTROL_REG, x);
ShiftOutBits(priv, EEPROM_EWEN_OPCODE, 5);
/////ShiftOutBits(CSRBaseIoAddress, reg, 4);
ShiftOutBits(priv, 0, 6);
StandBy(priv);
// Erase this particular word. Write the erase opcode and register
// number in that order. The opcode is 3bits in length; reg is 6 bits long.
ShiftOutBits(priv, EEPROM_ERASE_OPCODE, 3);
ShiftOutBits(priv, reg, AddressSize);
if (WaitEEPROMCmdDone(priv) == FALSE)
{
return;
}
StandBy(priv);
// write the new word to the EEPROM
// send the write opcode the EEPORM
ShiftOutBits(priv, EEPROM_WRITE_OPCODE, 3);
// select which word in the EEPROM that we are writing to.
ShiftOutBits(priv, reg, AddressSize);
// write the data to the selected EEPROM word.
ShiftOutBits(priv, data, 16);
if (WaitEEPROMCmdDone(priv) == FALSE)
{
// DbgPrint("D100: Failed EEPROM Write");
return;
}
StandBy(priv);
ShiftOutBits(priv, EEPROM_EWDS_OPCODE, 5);
ShiftOutBits(priv, reg, 4);
EEpromCleanup(priv);
return;
}
static void
rtl8169_tx_timeout(struct net_device *dev)
{
struct rtl8169_private *tp = dev->priv;
void *ioaddr = tp->mmio_addr;
u8 tmp8;
/* disable Tx, if not already */
tmp8 = RTL_R8(ChipCmd);
if (tmp8 & CmdTxEnb)
RTL_W8(ChipCmd, tmp8 & ~CmdTxEnb);
/* Disable interrupts by clearing the interrupt mask. */
RTL_W16(IntrMask, 0x0000);
/* Stop a shared interrupt from scavenging while we are. */
spin_lock_irq(&tp->lock);
rtl8169_tx_clear(tp);
spin_unlock_irq(&tp->lock);
/* ...and finally, reset everything */
rtl8169_hw_start(dev);
netif_wake_queue(dev);
}
//-------------------------------------------------------------------
//rtl_eeprom_read_sc():
// read one word from eeprom
//-------------------------------------------------------------------
u16 rtl_eeprom_read_sc(void __iomem *ioaddr, u16 reg)
{
int addr_sz = 6;
u8 x;
u16 data;
if (rtl_eeprom_type(ioaddr))
addr_sz = 8;
else
addr_sz = 6;
x = RTL_R8(Cfg9346);
x &= ~(Cfg9346_EEDI | Cfg9346_EEDO | Cfg9346_EESK);
x |= Cfg9346_EEM1 | Cfg9346_EECS;
RTL_W8(Cfg9346, x);
rtl_shift_out_bits(RTL_EEPROM_READ_OPCODE, 3, ioaddr);
rtl_shift_out_bits(reg, addr_sz, ioaddr);
data = rtl_shift_in_bits(ioaddr);
rtl_eeprom_cleanup(ioaddr);
return data;
}
static VOID
ShiftOutBits(
struct rtl8190_priv *priv,
USHORT data,
USHORT count)
{
ULONG ioaddr = priv->pshare->ioaddr;
USHORT x,mask;
mask = 0x01 << (count - 1);
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EEDO | EEDI);
do
{
x &= ~EEDI;
if(data & mask)
x |= EEDI;
RTL_W8(CSR_EEPROM_CONTROL_REG, (UCHAR)x);
delay_us(CLOCK_RATE);
RaiseClock(priv, &x);
LowerClock(priv, &x);
mask = mask >> 1;
} while(mask);
x &= ~EEDI;
RTL_W8(CSR_EEPROM_CONTROL_REG, (UCHAR)x);
}
static void rtl8169_phy_timer(unsigned long __opaque)
{
struct net_device *dev = (struct net_device *)__opaque;
struct rtl8169_private *tp = dev->priv;
struct timer_list *timer = &tp->timer;
void *ioaddr = tp->mmio_addr;
assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
assert(tp->phy_version < RTL_GIGA_PHY_VER_G);
if (RTL_R8(PHYstatus) & LinkStatus)
tp->phy_link_down_cnt = 0;
else {
tp->phy_link_down_cnt++;
if (tp->phy_link_down_cnt >= 12) {
int reg;
// If link on 1000, perform phy reset.
reg = mdio_read(ioaddr, PHY_1000_CTRL_REG);
if (reg & PHY_Cap_1000_Full)
rtl8169_hw_phy_reset(dev);
tp->phy_link_down_cnt = 0;
}
}
mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
}
//*****************************************************************************
//
// I/O based Read EEPROM Routines
//
//*****************************************************************************
//-----------------------------------------------------------------------------
// Procedure: ReadEEprom
//
// Description: This routine serially reads one word out of the EEPROM.
//
// Arguments:
// Reg - EEPROM word to read.
//
// Returns:
// Contents of EEPROM word (Reg).
//-----------------------------------------------------------------------------
static USHORT
ReadEEprom(
struct rtl8190_priv *priv,
UCHAR AddressSize,
USHORT Reg)
{
ULONG ioaddr = priv->pshare->ioaddr;
USHORT x;
USHORT data;
// select EEPROM, reset bits, set EECS
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EEDI | EEDO | EESK | CR9346_EEM0);
x |= CR9346_EEM1 | EECS;
RTL_W8(CSR_EEPROM_CONTROL_REG, (UCHAR)x);
// write the read opcode and register number in that order
// The opcode is 3bits in length, reg is 6 bits long
ShiftOutBits(priv, EEPROM_READ_OPCODE, 3);
ShiftOutBits(priv, Reg, AddressSize);
// Now read the data (16 bits) in from the selected EEPROM word
data = ShiftInBits(priv);
EEpromCleanup(priv);
return data;
}
static void rtl8169_hw_start(struct eth_device *dev)
{
u32 i;
#ifdef DEBUG_RTL8169
int stime = currticks();
printf ("%s\n", __FUNCTION__);
#endif
#if 0
/* Soft reset the chip. */
RTL_W8(ChipCmd, CmdReset);
/* Check that the chip has finished the reset. */
for (i = 1000; i > 0; i--) {
if ((RTL_R8(ChipCmd) & CmdReset) == 0)
break;
else
udelay(10);
}
#endif
RTL_W8(Cfg9346, Cfg9346_Unlock);
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
RTL_W8(EarlyTxThres, EarlyTxThld);
/* For gigabit rtl8169 */
RTL_W16(RxMaxSize, RxPacketMaxSize);
/* Set Rx Config register */
i = rtl8169_rx_config | (RTL_R32(RxConfig) &
rtl_chip_info[tpc->chipset].RxConfigMask);
RTL_W32(RxConfig, i);
/* Set DMA burst size and Interframe Gap Time */
RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
(InterFrameGap << TxInterFrameGapShift));
tpc->cur_rx = 0;
RTL_W32(TxDescStartAddr, (unsigned long)tpc->TxDescArray);
RTL_W32(RxDescStartAddr, (unsigned long)tpc->RxDescArray);
RTL_W8(Cfg9346, Cfg9346_Lock);
udelay(10);
RTL_W32(RxMissed, 0);
rtl8169_set_rx_mode(dev);
/* no early-rx interrupts */
RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
#ifdef DEBUG_RTL8169
printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
#endif
}
__inline__ unsigned char DMDP_RTL_R8(unsigned int phy, unsigned int reg)
{
struct rtl8192cd_priv *priv;
//printk("++++++++++++++++++++++++++%s(%x)++++++++++++++++++++++++++\n", __FUNCTION__, reg);
if (phy >= NUM_WLAN_IFACE || phy < 0) {
printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
return -1;
}
priv = (struct rtl8192cd_priv *)if_priv[phy];
return RTL_R8(reg);
}
void rtl_eeprom_cleanup(void __iomem *ioaddr)
{
u8 x;
x = RTL_R8(Cfg9346);
x &= ~(Cfg9346_EEDI | Cfg9346_EECS);
RTL_W8(Cfg9346, x);
rtl_raise_clock(&x, ioaddr);
rtl_lower_clock(&x, ioaddr);
}
void rtl_stand_by(void __iomem *ioaddr)
{
u8 x;
x = RTL_R8(Cfg9346);
x &= ~(Cfg9346_EECS | Cfg9346_EESK);
RTL_W8(Cfg9346, x);
udelay(RTL_CLOCK_RATE);
x |= Cfg9346_EECS;
RTL_W8(Cfg9346, x);
}
/**************************************************************************
RECV - Receive a frame
***************************************************************************/
static int rtl_recv(struct eth_device *dev)
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
/* nic->packetlen should contain length of data */
int cur_rx;
int length = 0;
#ifdef DEBUG_RTL8169_RX
printf ("%s\n", __FUNCTION__);
#endif
ioaddr = dev->iobase;
cur_rx = tpc->cur_rx;
rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
unsigned char rxdata[RX_BUF_LEN];
length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
status) & 0x00001FFF) - 4;
rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
if (cur_rx == NUM_RX_DESC - 1)
tpc->RxDescArray[cur_rx].status =
cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
else
tpc->RxDescArray[cur_rx].status =
cpu_to_le32(OWNbit + RX_BUF_SIZE);
tpc->RxDescArray[cur_rx].buf_addr =
cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx]));
rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
net_process_received_packet(rxdata, length);
} else {
puts("Error Rx");
}
cur_rx = (cur_rx + 1) % NUM_RX_DESC;
tpc->cur_rx = cur_rx;
return 1;
} else {
ushort sts = RTL_R8(IntrStatus);
RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
udelay(100); /* wait */
}
tpc->cur_rx = cur_rx;
return (0); /* initially as this is called to flush the input */
}
static VOID
EEpromCleanup(
struct rtl8190_priv *priv)
{
ULONG ioaddr = priv->pshare->ioaddr;
USHORT x;
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EECS | EEDI);
RTL_W8(CSR_EEPROM_CONTROL_REG, (UCHAR)x);
RaiseClock(priv, &x);
LowerClock(priv, &x);
}
static VOID
StandBy(
struct rtl8190_priv *priv)
{
ULONG ioaddr = priv->pshare->ioaddr;
UCHAR x;
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EECS | EESK);
RTL_W8(CSR_EEPROM_CONTROL_REG, x);
delay_us(CLOCK_RATE);
x |= EECS;
RTL_W8(CSR_EEPROM_CONTROL_REG, x);
delay_us(CLOCK_RATE);
}
static USHORT
WaitEEPROMCmdDone(
struct rtl8190_priv *priv)
{
ULONG ioaddr = priv->pshare->ioaddr;
UCHAR x;
USHORT i;
StandBy(priv);
for (i=0; i<200; i++)
{
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
if (x & EEDO)
return (TRUE);
delay_us(CLOCK_RATE);
}
return FALSE;
}
u8
ODM_Read1Byte(
PDM_ODM_T pDM_Odm,
u32 RegAddr
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
return RTL_R8(RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
struct rtw_adapter * Adapter = pDM_Odm->Adapter;
return rtw_read8(Adapter,RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
struct rtw_adapter * Adapter = pDM_Odm->Adapter;
return PlatformEFIORead1Byte(Adapter, RegAddr);
#endif
}
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
return RTL_R8(RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read8(Adapter,RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
PADAPTER Adapter = pDM_Odm->Adapter;
return PlatformEFIORead1Byte(Adapter, RegAddr);
#endif
}
int rtl_eeprom_cmd_done(void __iomem *ioaddr)
{
u8 x;
int i;
rtl_stand_by(ioaddr);
for (i = 0; i < 50000; i++) {
x = RTL_R8(Cfg9346);
if (x & Cfg9346_EEDO) {
udelay(RTL_CLOCK_RATE * 2 * 3);
return 0;
}
udelay(1);
}
return -1;
}
//-------------------------------------------------------------------
//rtl_eeprom_write_sc():
// write one word to a specific address in the eeprom
//-------------------------------------------------------------------
void rtl_eeprom_write_sc(void __iomem *ioaddr, u16 reg, u16 data)
{
u8 x;
int addr_sz = 6;
int w_dummy_addr = 4;
if (rtl_eeprom_type(ioaddr)) {
addr_sz = 8;
w_dummy_addr = 6;
} else {
addr_sz = 6;
w_dummy_addr = 4;
}
x = RTL_R8(Cfg9346);
x &= ~(Cfg9346_EEDI | Cfg9346_EEDO | Cfg9346_EESK);
x |= Cfg9346_EEM1 | Cfg9346_EECS;
RTL_W8(Cfg9346, x);
rtl_shift_out_bits(RTL_EEPROM_EWEN_OPCODE, 5, ioaddr);
rtl_shift_out_bits(reg, w_dummy_addr, ioaddr);
rtl_stand_by(ioaddr);
rtl_shift_out_bits(RTL_EEPROM_ERASE_OPCODE, 3, ioaddr);
rtl_shift_out_bits(reg, addr_sz, ioaddr);
if (rtl_eeprom_cmd_done(ioaddr) < 0) {
return;
}
rtl_stand_by(ioaddr);
rtl_shift_out_bits(RTL_EEPROM_WRITE_OPCODE, 3, ioaddr);
rtl_shift_out_bits(reg, addr_sz, ioaddr);
rtl_shift_out_bits(data, 16, ioaddr);
if (rtl_eeprom_cmd_done(ioaddr) < 0) {
return;
}
rtl_stand_by(ioaddr);
rtl_shift_out_bits(RTL_EEPROM_EWDS_OPCODE, 5, ioaddr);
rtl_shift_out_bits(reg, w_dummy_addr, ioaddr);
rtl_eeprom_cleanup(ioaddr);
}
static int rtl8169_init_board(unsigned long dev_iobase, const char *name)
{
int i;
u32 tmp;
#ifdef DEBUG_RTL8169
printf ("%s\n", __FUNCTION__);
#endif
ioaddr = dev_iobase;
/* Soft reset the chip. */
RTL_W8(ChipCmd, CmdReset);
/* Check that the chip has finished the reset. */
for (i = 1000; i > 0; i--)
if ((RTL_R8(ChipCmd) & CmdReset) == 0)
break;
else
udelay(10);
/* identify chip attached to board */
tmp = RTL_R32(TxConfig);
tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
if (tmp == rtl_chip_info[i].version) {
tpc->chipset = i;
goto match;
}
}
/* if unknown chip, assume array element #0, original RTL-8169 in this case */
printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
name);
printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
tpc->chipset = 0;
match:
return 0;
}
VOID
odm_DynamicTxPowerAP(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
//#if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1))
prtl8192cd_priv priv = pDM_Odm->priv;
s4Byte i;
s2Byte pwr_thd = TX_POWER_NEAR_FIELD_THRESH_AP;
if(!priv->pshare->rf_ft_var.tx_pwr_ctrl)
return;
#if ((RTL8812E_SUPPORT==1) || (RTL8881A_SUPPORT==1))
if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8881A))
pwr_thd = TX_POWER_NEAR_FIELD_THRESH_8812;
#endif
#if defined(CONFIG_RTL_92D_SUPPORT) || defined(CONFIG_RTL_92C_SUPPORT)
if(CHIP_VER_92X_SERIES(priv))
{
#ifdef HIGH_POWER_EXT_PA
if(pDM_Odm->ExtPA)
tx_power_control(priv);
#endif
}
#endif
/*
* Check if station is near by to use lower tx power
*/
if ((priv->up_time % 3) == 0 ) {
int disable_pwr_ctrl = ((pDM_Odm->FalseAlmCnt.Cnt_all > 1000 ) || ((pDM_Odm->FalseAlmCnt.Cnt_all > 300 ) && ((RTL_R8(0xc50) & 0x7f) >= 0x32))) ? 1 : 0;
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
if(IS_STA_VALID(pstat) ) {
if(disable_pwr_ctrl)
pstat->hp_level = 0;
else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd))
pstat->hp_level = 1;
else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd-8)))
pstat->hp_level = 0;
}
}
#if defined(CONFIG_WLAN_HAL_8192EE)
if (GET_CHIP_VER(priv) == VERSION_8192E) {
if( !disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff) ) {
if(pDM_Odm->RSSI_Min > pwr_thd)
RRSR_power_control_11n(priv, 1 );
else if(pDM_Odm->RSSI_Min < (pwr_thd-8))
RRSR_power_control_11n(priv, 0 );
} else {
RRSR_power_control_11n(priv, 0 );
}
}
#endif
}
//#endif
#endif
}
static int rtl_init(unsigned long dev_ioaddr, const char *name,
unsigned char *enetaddr)
{
static int board_idx = -1;
int i, rc;
int option = -1, Cap10_100 = 0, Cap1000 = 0;
#ifdef DEBUG_RTL8169
printf ("%s\n", __FUNCTION__);
#endif
ioaddr = dev_ioaddr;
board_idx++;
/* point to private storage */
tpc = &tpx;
rc = rtl8169_init_board(ioaddr, name);
if (rc)
return rc;
/* Get MAC address. FIXME: read EEPROM */
for (i = 0; i < MAC_ADDR_LEN; i++)
enetaddr[i] = RTL_R8(MAC0 + i);
#ifdef DEBUG_RTL8169
printf("chipset = %d\n", tpc->chipset);
printf("MAC Address");
for (i = 0; i < MAC_ADDR_LEN; i++)
printf(":%02x", enetaddr[i]);
putc('\n');
#endif
#ifdef DEBUG_RTL8169
/* Print out some hardware info */
printf("%s: at ioaddr 0x%lx\n", name, ioaddr);
#endif
/* if TBI is not endbled */
if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
int val = mdio_read(PHY_AUTO_NEGO_REG);
option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
/* Force RTL8169 in 10/100/1000 Full/Half mode. */
if (option > 0) {
#ifdef DEBUG_RTL8169
printf("%s: Force-mode Enabled.\n", name);
#endif
Cap10_100 = 0, Cap1000 = 0;
switch (option) {
case _10_Half:
Cap10_100 = PHY_Cap_10_Half;
Cap1000 = PHY_Cap_Null;
break;
case _10_Full:
Cap10_100 = PHY_Cap_10_Full;
Cap1000 = PHY_Cap_Null;
break;
case _100_Half:
Cap10_100 = PHY_Cap_100_Half;
Cap1000 = PHY_Cap_Null;
break;
case _100_Full:
Cap10_100 = PHY_Cap_100_Full;
Cap1000 = PHY_Cap_Null;
break;
case _1000_Full:
Cap10_100 = PHY_Cap_Null;
Cap1000 = PHY_Cap_1000_Full;
break;
default:
break;
}
mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
mdio_write(PHY_1000_CTRL_REG, Cap1000);
} else {
#ifdef DEBUG_RTL8169
printf("%s: Auto-negotiation Enabled.\n",
name);
#endif
/* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
mdio_write(PHY_AUTO_NEGO_REG,
PHY_Cap_10_Half | PHY_Cap_10_Full |
PHY_Cap_100_Half | PHY_Cap_100_Full |
(val & 0x1F));
/* enable 1000 Full Mode */
mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
}
/* Enable auto-negotiation and restart auto-nigotiation */
mdio_write(PHY_CTRL_REG,
PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
udelay(100);
/* wait for auto-negotiation process */
for (i = 10000; i > 0; i--) {
/* check if auto-negotiation complete */
if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
udelay(100);
option = RTL_R8(PHYstatus);
if (option & _1000bpsF) {
#ifdef DEBUG_RTL8169
printf("%s: 1000Mbps Full-duplex operation.\n",
name);
#endif
} else {
#ifdef DEBUG_RTL8169
printf("%s: %sMbps %s-duplex operation.\n",
name,
(option & _100bps) ? "100" :
"10",
(option & FullDup) ? "Full" :
"Half");
#endif
}
break;
} else {
udelay(100);
}
} /* end for-loop to wait for auto-negotiation process */
} else {
udelay(100);
#ifdef DEBUG_RTL8169
printf
("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
name,
(RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
#endif
}
tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
if (!tpc->RxDescArray)
return -ENOMEM;
tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
if (!tpc->TxDescArray)
return -ENOMEM;
return 0;
}
static void rtl8169_hw_start(pci_dev_t dev)
#endif
{
u32 i;
#ifdef DEBUG_RTL8169
int stime = currticks();
printf ("%s\n", __FUNCTION__);
#endif
#if 0
/* Soft reset the chip. */
RTL_W8(ChipCmd, CmdReset);
/* Check that the chip has finished the reset. */
for (i = 1000; i > 0; i--) {
if ((RTL_R8(ChipCmd) & CmdReset) == 0)
break;
else
udelay(10);
}
#endif
RTL_W8(Cfg9346, Cfg9346_Unlock);
/* RTL-8169sb/8110sb or previous version */
if (tpc->chipset <= 5)
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
RTL_W8(EarlyTxThres, EarlyTxThld);
/* For gigabit rtl8169 */
RTL_W16(RxMaxSize, RxPacketMaxSize);
/* Set Rx Config register */
i = rtl8169_rx_config | (RTL_R32(RxConfig) &
rtl_chip_info[tpc->chipset].RxConfigMask);
RTL_W32(RxConfig, i);
/* Set DMA burst size and Interframe Gap Time */
RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
(InterFrameGap << TxInterFrameGapShift));
tpc->cur_rx = 0;
#ifdef CONFIG_DM_ETH
RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)tpc->TxDescArray));
#else
RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)tpc->TxDescArray));
#endif
RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
#ifdef CONFIG_DM_ETH
RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
#else
RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
#endif
RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
/* RTL-8169sc/8110sc or later version */
if (tpc->chipset > 5)
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
RTL_W8(Cfg9346, Cfg9346_Lock);
udelay(10);
RTL_W32(RxMissed, 0);
rtl8169_set_rx_mode();
/* no early-rx interrupts */
RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
#ifdef DEBUG_RTL8169
printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
#endif
}
static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
uchar **packetp)
#endif
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
/* nic->packetlen should contain length of data */
int cur_rx;
int length = 0;
#ifdef DEBUG_RTL8169_RX
printf ("%s\n", __FUNCTION__);
#endif
ioaddr = dev_iobase;
cur_rx = tpc->cur_rx;
rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
status) & 0x00001FFF) - 4;
rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
if (cur_rx == NUM_RX_DESC - 1)
tpc->RxDescArray[cur_rx].status =
cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
else
tpc->RxDescArray[cur_rx].status =
cpu_to_le32(OWNbit + RX_BUF_SIZE);
#ifdef CONFIG_DM_ETH
tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
dm_pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)
tpc->RxBufferRing[cur_rx]));
#else
tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
tpc->RxBufferRing[cur_rx]));
#endif
rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
#ifdef CONFIG_DM_ETH
*packetp = rxdata;
#else
net_process_received_packet(rxdata, length);
#endif
} else {
puts("Error Rx");
length = -EIO;
}
cur_rx = (cur_rx + 1) % NUM_RX_DESC;
tpc->cur_rx = cur_rx;
return length;
} else {
ushort sts = RTL_R8(IntrStatus);
RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
udelay(100); /* wait */
}
tpc->cur_rx = cur_rx;
return (0); /* initially as this is called to flush the input */
}
static int
OOB_set_ip_mac(struct rtl8168_private *tp, struct sockaddr_in *sa, u8 *mac)
{
u32 data;
if (tp->mcfg == CFG_METHOD_13) {
OCP_write(tp, 0xF, 0xd0, be32_to_cpu(sa->sin_addr.s_addr));
memcpy(&data, mac, 4);
OCP_write(tp, 0xF, 0x00, le32_to_cpu(data));
data = 0;
memcpy(&data, mac + 4, 2);
OCP_write(tp, 0x3, 0x04, le32_to_cpu(data));
OOB_notify(tp, OOB_CMD_SET_IPMAC);
} else if (tp->mcfg == CFG_METHOD_17) {
void __iomem *ioaddr = tp->mmio_addr;
struct net_device *dev = tp->dev;
u32 rx_mode;
rx_mode = RTL_R32(RxConfig);
if (netif_running(dev)) {
netif_stop_queue(dev);
RTL_W32(RxConfig, rx_mode & ~0x3f);
while ((RTL_R8(0xd3) & (BIT_5 | BIT_4)) != ((BIT_5 | BIT_4)))
udelay(20);
RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
// } else {
// unsigned long flags;
//
// spin_lock_irqsave(&tp->phy_lock, flags);
// mdio_write(tp, 0x1f, 0x0000);
// data = mdio_read(tp, MII_CTRL1000);
// data &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
// mdio_write(tp, MII_CTRL1000, data);
// mdio_write(tp, 0x00, 0x9200);
// spin_unlock_irqrestore(&tp->phy_lock, flags);
//
// ssleep(3);
// RTL_W16(IntrStatus, RTL_R16(IntrStatus));
//
// RTL_W32(MAR0, 0);
// RTL_W32(MAR0 + 4, 0);
// RTL_W16(RxMaxSize, 0x05f3);
}
RTL_W8(0xD3, RTL_R8(0xD3) & ~BIT_7);
rtl8168_eri_write(ioaddr, 0x180, 4, 0x06080888, ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0x184, 4, 0xdd860008, ERIAR_ExGMAC);
memcpy(&data, mac, 2);
rtl8168_eri_write(ioaddr, 0xf0, 4, (le32_to_cpu(data) << 16), ERIAR_ExGMAC);
memcpy(&data, mac + 2, 4);
rtl8168_eri_write(ioaddr, 0xf4, 4, le32_to_cpu(data), ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0x190, 4, 0x3c110600, ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0x194, 4, 0x2c32332b, ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0x198, 4, 0x003a0201, ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0x19c, 4, 0x00000000, ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0x1f0, 4, cpu_to_le32(sa->sin_addr.s_addr), ERIAR_ExGMAC);
memcpy(&data, mac, 4);
rtl8168_eri_write(ioaddr, 0x258, 4, le32_to_cpu(data), ERIAR_ExGMAC);
memcpy(&data, mac + 4, 2);
rtl8168_eri_write(ioaddr, 0x25c, 2, le32_to_cpu(data), ERIAR_ExGMAC);
RTL_W8(0xe0, RTL_R8(0xe0) | BIT_6);
while (!(RTL_R8(0xd3) & BIT_1))
udelay(20);
RTL_W32(0xb0, 0x9800e035);
RTL_W32(0xb0, 0x9801e034);
RTL_W32(0xb0, 0x9802e019);
RTL_W32(0xb0, 0x98039918);
RTL_W32(0xb0, 0x9804c011);
RTL_W32(0xb0, 0x98057100);
RTL_W32(0xb0, 0x9806499f);
RTL_W32(0xb0, 0x9807f011);
RTL_W32(0xb0, 0x9808c00e);
RTL_W32(0xb0, 0x98097100);
RTL_W32(0xb0, 0x980A4995);
RTL_W32(0xb0, 0x980Bf00d);
RTL_W32(0xb0, 0x980C4895);
RTL_W32(0xb0, 0x980D9900);
RTL_W32(0xb0, 0x980Ec009);
RTL_W32(0xb0, 0x980F7100);
RTL_W32(0xb0, 0x98104890);
RTL_W32(0xb0, 0x98119900);
RTL_W32(0xb0, 0x98124810);
RTL_W32(0xb0, 0x98139900);
RTL_W32(0xb0, 0x9814e004);
RTL_W32(0xb0, 0x9815d44e);
RTL_W32(0xb0, 0x9816d506);
RTL_W32(0xb0, 0x9817c0b4);
RTL_W32(0xb0, 0x9818c002);
RTL_W32(0xb0, 0x9819b800);
RTL_W32(0xb0, 0x981A0500);
RTL_W32(0xb0, 0x981B1a26);
RTL_W32(0xb0, 0x981Ca4ca);
RTL_W32(0xb0, 0x981D21bc);
RTL_W32(0xb0, 0x981E25bc);
RTL_W32(0xb0, 0x981F1305);
RTL_W32(0xb0, 0x9820f00d);
RTL_W32(0xb0, 0x9821c213);
RTL_W32(0xb0, 0x98227340);
RTL_W32(0xb0, 0x982349b0);
RTL_W32(0xb0, 0x9824f009);
RTL_W32(0xb0, 0x98251a3a);
RTL_W32(0xb0, 0x9826a4ca);
RTL_W32(0xb0, 0x982721b9);
RTL_W32(0xb0, 0x982825b9);
RTL_W32(0xb0, 0x98291303);
RTL_W32(0xb0, 0x982Af006);
RTL_W32(0xb0, 0x982B1309);
RTL_W32(0xb0, 0x982Cf004);
RTL_W32(0xb0, 0x982Dc306);
RTL_W32(0xb0, 0x982E1a26);
RTL_W32(0xb0, 0x982Fbb00);
RTL_W32(0xb0, 0x9830c302);
RTL_W32(0xb0, 0x9831bb00);
RTL_W32(0xb0, 0x98320f3e);
RTL_W32(0xb0, 0x98330f4e);
RTL_W32(0xb0, 0x9834c0ae);
RTL_W32(0xb0, 0x98351800);
RTL_W32(0xb0, 0x9836b800);
RTL_W32(0xb0, 0xfe173000);
RTL_W32(0xb0, 0xfe1604ff);
RTL_W32(0xb0, 0xfe150f4d);
data = rtl8168_eri_read(ioaddr, 0xd6, 1, ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0xd6, 1, data | BIT_0, ERIAR_ExGMAC);
if (netif_running(dev)) {
rtl8168_init_ring_indexes(tp);
RTL_W8(ChipCmd, CmdRxEnb | CmdTxEnb);
RTL_W32(RxConfig, rx_mode);
netif_wake_queue(dev);
} else {
RTL_W8(0xD3, RTL_R8(0xD3) | BIT_7);
// data = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC);
// data &= ~BIT_0;
// rtl8168_eri_write( ioaddr, 0xDC, 1, data, ERIAR_ExGMAC);
// data |= BIT_0;
// rtl8168_eri_write( ioaddr, 0xDC, 1, data, ERIAR_ExGMAC);
RTL_W32(RxConfig, rx_mode | 0x0e);
}
} else {
return -EFAULT;
}
return 0;
}
