/*
========================================================================
Routine Description:
Process MGMT ring DMA done interrupt, running in DPC level
Arguments:
pAd Pointer to our adapter
Return Value:
None
IRQL = DISPATCH_LEVEL
Note:
========================================================================
*/
VOID RTMPHandleMgmtRingDmaDoneInterrupt(
IN PRTMP_ADAPTER pAd)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PNDIS_PACKET pPacket;
// int i;
UCHAR FREE = 0;
PRTMP_MGMT_RING pMgmtRing = &pAd->MgmtRing;
NdisAcquireSpinLock(&pAd->MgmtRingLock);
RTMP_IO_READ32(pAd, TX_MGMTDTX_IDX, &pMgmtRing->TxDmaIdx);
while (pMgmtRing->TxSwFreeIdx!= pMgmtRing->TxDmaIdx)
{
FREE++;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
#endif
pTxD->DMADONE = 0;
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket;
if (pPacket == NULL)
continue;
if (pPacket)
{
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket = NULL;
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket;
if (pPacket)
{
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket = NULL;
INC_RING_INDEX(pMgmtRing->TxSwFreeIdx, MGMT_RING_SIZE);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, TRUE, TYPE_TXD);
#endif
}
NdisReleaseSpinLock(&pAd->MgmtRingLock);
#ifdef CONFIG_STA_SUPPORT
#endif // CONFIG_STA_SUPPORT //
}
int RtmpPCIMgmtKickOut(
IN RTMP_ADAPTER *pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket,
IN PUCHAR pSrcBufVA,
IN UINT SrcBufLen)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
ULONG SwIdx = pAd->MgmtRing.TxCpuIdx;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC)pAd->MgmtRing.Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) pAd->MgmtRing.Cell[SwIdx].AllocVa;
#endif
pAd->MgmtRing.Cell[SwIdx].pNdisPacket = pPacket;
pAd->MgmtRing.Cell[SwIdx].pNextNdisPacket = NULL;
RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_MGMT);
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 1;
pTxD->DMADONE = 0;
pTxD->SDLen1 = 0;
pTxD->SDPtr0 = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
pTxD->SDLen0 = SrcBufLen;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
INC_RING_INDEX(pAd->MgmtRing.TxCpuIdx, MGMT_RING_SIZE);
RTMP_IO_WRITE32(pAd, TX_MGMTCTX_IDX, pAd->MgmtRing.TxCpuIdx);
return 0;
}
/*
========================================================================
Routine Description:
Arguments:
Return Value:
Note: PsPoll use BulkOutPipeId = 0
========================================================================
*/
VOID RTUSBBulkOutPsPoll(
IN PRTMP_ADAPTER pAd)
{
PTX_CONTEXT pPsPollContext = &(pAd->PsPollContext);
PURB pUrb;
int ret = 0;
unsigned long IrqFlags;
RTMP_IRQ_LOCK(&pAd->BulkOutLock[0], IrqFlags);
if ((pAd->BulkOutPending[0] == TRUE) || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_TX))
{
RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);
return;
}
pAd->BulkOutPending[0] = TRUE;
pAd->watchDogTxPendingCnt[0] = 1;
pPsPollContext->IRPPending = TRUE;
RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);
/* Clear PS-Poll bulk flag*/
RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_PSPOLL);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pPsPollContext->TransferBuffer, TYPE_TXINFO);
#endif /* RT_BIG_ENDIAN */
/* Init Tx context descriptor*/
#ifdef CONFIG_MULTI_CHANNEL
if (pAd->Multi_Channel_Enable == TRUE)
RTUSBInitTxDesc(pAd, pPsPollContext, 0, (usb_complete_t)RtmpUsbBulkOutPsPollComplete);
else
#endif /* CONFIG_MULTI_CHANNEL */
RTUSBInitTxDesc(pAd, pPsPollContext, MGMTPIPEIDX, (usb_complete_t)RtmpUsbBulkOutPsPollComplete);
pUrb = pPsPollContext->pUrb;
if((ret = RTUSB_SUBMIT_URB(pUrb))!=0)
{
RTMP_IRQ_LOCK(&pAd->BulkOutLock[0], IrqFlags);
pAd->BulkOutPending[0] = FALSE;
pAd->watchDogTxPendingCnt[0] = 0;
pPsPollContext->IRPPending = FALSE;
RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);
DBGPRINT(RT_DEBUG_ERROR, ("RTUSBBulkOutPsPoll: Submit Tx URB failed %d\n", ret));
return;
}
}
/*
========================================================================
Routine Description:
Arguments:
Return Value:
Note: NULL frame use BulkOutPipeId = 0
========================================================================
*/
VOID RTUSBBulkOutNullFrame(
IN PRTMP_ADAPTER pAd)
{
PTX_CONTEXT pNullContext = &(pAd->NullContext);
PURB pUrb;
int ret = 0;
unsigned long IrqFlags;
RTMP_IRQ_LOCK(&pAd->BulkOutLock[0], IrqFlags);
if ((pAd->BulkOutPending[0] == TRUE) || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_TX))
{
RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);
DBGPRINT(RT_DEBUG_ERROR, ("RTUSBBulkOutNullFrame: IN STOP_TX STATUS %d\n"));
return;
}
pAd->BulkOutPending[0] = TRUE;
pAd->watchDogTxPendingCnt[0] = 1;
pNullContext->IRPPending = TRUE;
RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);
/* Increase Total transmit byte counter*/
pAd->RalinkCounters.TransmittedByteCount += pNullContext->BulkOutSize;
/* Clear Null frame bulk flag*/
RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_NULL);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pNullContext->TransferBuffer, TYPE_TXINFO);
#endif /* RT_BIG_ENDIAN */
/* Init Tx context descriptor*/
RTUSBInitTxDesc(pAd, pNullContext, 0, (usb_complete_t)RtmpUsbBulkOutNullFrameComplete);
pUrb = pNullContext->pUrb;
if((ret = RTUSB_SUBMIT_URB(pUrb))!=0)
{
RTMP_IRQ_LOCK(&pAd->BulkOutLock[0], IrqFlags);
pAd->BulkOutPending[0] = FALSE;
pAd->watchDogTxPendingCnt[0] = 0;
pNullContext->IRPPending = FALSE;
RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);
DBGPRINT(RT_DEBUG_ERROR, ("RTUSBBulkOutNullFrame: Submit Tx URB failed %d\n", ret));
return;
}
}
VOID RtmpPCIDataLastTxIdx(
IN PRTMP_ADAPTER pAd,
IN UCHAR QueIdx,
IN USHORT LastTxIdx)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PRTMP_TX_RING pTxRing;
pTxRing = &pAd->TxRing[QueIdx];
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[LastTxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[LastTxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
pTxD->LastSec1 = 1;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
}
INT ATESetUpFrame(
IN PRTMP_ADAPTER pAd,
IN UINT32 TxIdx)
{
PATE_INFO pATEInfo = &(pAd->ate);
UINT pos = 0;
PTX_CONTEXT pNullContext;
PUCHAR pDest;
HTTRANSMIT_SETTING TxHTPhyMode;
TXWI_STRUC *pTxWI;
TXINFO_STRUC *pTxInfo;
UINT32 TransferBufferLength, OrgBufferLength = 0;
UCHAR padLen = 0;
UINT8 TXWISize = pAd->chipCap.TXWISize;
#ifdef RALINK_QA
PHEADER_802_11 pHeader80211 = NULL;
#endif /* RALINK_QA */
if ((RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) ||
(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET)) ||
(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) ||
(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
{
return -1;
}
/* We always use QID_AC_BE and FIFO_EDCA in ATE mode. */
pNullContext = &(pAd->NullContext);
ASSERT(pNullContext != NULL);
if (pNullContext->InUse == FALSE)
{
/* set the in use bit */
pNullContext->InUse = TRUE;
NdisZeroMemory(&(pAd->NullFrame), sizeof(HEADER_802_11));
/* fill 802.11 header */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
pHeader80211 = NdisMoveMemory(&(pAd->NullFrame),
pATEInfo->Header, pATEInfo->HLen);
}
else
#endif /* RALINK_QA */
{
NdisMoveMemory(&(pAd->NullFrame), TemplateFrame,
sizeof(HEADER_802_11));
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)&(pAd->NullFrame), DIR_READ, FALSE);
#endif /* RT_BIG_ENDIAN */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
/* modify sequence number... */
if (pATEInfo->TxDoneCount == 0)
{
pATEInfo->seq = pHeader80211->Sequence;
}
else
{
pHeader80211->Sequence = ++pATEInfo->seq;
}
/* We already got all the address fields from QA GUI. */
}
else
#endif /* RALINK_QA */
{
COPY_MAC_ADDR(pAd->NullFrame.Addr1, pATEInfo->Addr1);
COPY_MAC_ADDR(pAd->NullFrame.Addr2, pATEInfo->Addr2);
COPY_MAC_ADDR(pAd->NullFrame.Addr3, pATEInfo->Addr3);
}
RTMPZeroMemory(&pAd->NullContext.TransferBuffer->field.WirelessPacket[0], TX_BUFFER_NORMSIZE);
pTxInfo = (TXINFO_STRUC *)&pAd->NullContext.TransferBuffer->field.WirelessPacket[0];
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
/* Avoid to exceed the range of WirelessPacket[]. */
ASSERT(pATEInfo->TxInfo.TxInfoPktLen <= (MAX_FRAME_SIZE - 34/* == 2312 */));
NdisMoveMemory(pTxInfo, &(pATEInfo->TxInfo), sizeof(pATEInfo->TxInfo));
}
else
#endif /* RALINK_QA */
{
/* Avoid to exceed the range of WirelessPacket[]. */
ASSERT(pATEInfo->TxLength <= (MAX_FRAME_SIZE - 34/* == 2312 */));
/* pTxInfo->TxInfoPktLen will be updated to include padding later */
ATEWriteTxInfo(pAd, pTxInfo, (USHORT)(TXWISize + pATEInfo->TxLength)
, TRUE, EpToQueue[MGMTPIPEIDX], FALSE, FALSE);
pTxInfo->TxInfoQSEL = FIFO_EDCA;
}
pTxWI = (TXWI_STRUC *)&pAd->NullContext.TransferBuffer->field.WirelessPacket[TXINFO_SIZE];
/* fill TxWI */
if (pATEInfo->bQATxStart == TRUE)
{
TxHTPhyMode.field.BW = pATEInfo->TxWI.TxWIBW;
TxHTPhyMode.field.ShortGI = pATEInfo->TxWI.TxWIShortGI;
TxHTPhyMode.field.STBC = pATEInfo->TxWI.TxWISTBC;
TxHTPhyMode.field.MCS = pATEInfo->TxWI.TxWIMCS;
TxHTPhyMode.field.MODE = pATEInfo->TxWI.TxWIPHYMODE;
ATEWriteTxWI(pAd, pTxWI, pATEInfo->TxWI.TxWIFRAG, pATEInfo->TxWI.TxWITS,
pATEInfo->TxWI.TxWIAMPDU, pATEInfo->TxWI.TxWIACK, pATEInfo->TxWI.TxWINSEQ,
pATEInfo->TxWI.TxWIBAWinSize, BSSID_WCID,
pATEInfo->TxWI.TxWIMPDUByteCnt/* include 802.11 header */,
pATEInfo->TxWI.TxWIPacketId,
0, pATEInfo->TxWI.TxWITXOP/*IFS_HTTXOP*/, pATEInfo->TxWI.TxWICFACK
/*FALSE*/, TxHTPhyMode);
}
else
{
TxHTPhyMode.field.BW = pATEInfo->TxWI.TxWIBW;
TxHTPhyMode.field.ShortGI = pATEInfo->TxWI.TxWIShortGI;
TxHTPhyMode.field.STBC = 0;
TxHTPhyMode.field.MCS = pATEInfo->TxWI.TxWIMCS;
TxHTPhyMode.field.MODE = pATEInfo->TxWI.TxWIPHYMODE;
ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE
/* No ack required. */, FALSE, 0, BSSID_WCID, pATEInfo->TxLength,
0, 0, IFS_HTTXOP, FALSE, TxHTPhyMode);
}
hex_dump("ATE", pAd->NullContext.TransferBuffer->field.WirelessPacket, 24);
dump_txinfo(pAd, pTxInfo);
dumpTxWI(pAd, pTxWI);
RTMPMoveMemory(&pAd->NullContext.TransferBuffer->field.WirelessPacket[TXINFO_SIZE + TXWISize],
&pAd->NullFrame, sizeof(HEADER_802_11));
pDest = &(pAd->NullContext.TransferBuffer->field.WirelessPacket[TXINFO_SIZE + TXWISize + sizeof(HEADER_802_11)]);
/* prepare frame payload */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
/* copy the pattern one by one to the frame payload */
if ((pATEInfo->PLen != 0) && (pATEInfo->DLen != 0))
{
for (pos = 0; pos < pATEInfo->DLen; pos += pATEInfo->PLen)
{
RTMPMoveMemory(pDest, pATEInfo->Pattern, pATEInfo->PLen);
pDest += pATEInfo->PLen;
}
}
TransferBufferLength = TXINFO_SIZE + TXWISize + pATEInfo->TxWI.TxWIMPDUByteCnt;
}
else
#endif /* RALINK_QA */
{
for (pos = 0; pos < (pATEInfo->TxLength - sizeof(HEADER_802_11)); pos++)
{
/* default payload is 0xA5 */
*pDest = pATEInfo->Payload;
pDest += 1;
}
TransferBufferLength = TXINFO_SIZE + TXWISize + pATEInfo->TxLength;
}
OrgBufferLength = TransferBufferLength;
TransferBufferLength = (TransferBufferLength + 3) & (~3);
/* Always add 4 extra bytes at every packet. */
padLen = TransferBufferLength - OrgBufferLength + 4;/* 4 == last packet padding */
/*
RTMP_PKT_TAIL_PADDING == 11.
[11 == 3(max 4 byte padding) + 4(last packet padding) + 4(MaxBulkOutsize align padding)]
*/
ASSERT((padLen <= (RTMP_PKT_TAIL_PADDING - 4/* 4 == MaxBulkOutsize alignment padding */)));
/* Now memzero all extra padding bytes. */
NdisZeroMemory(pDest, padLen);
pDest += padLen;
/* Update pTxInfo->TxInfoPktLen to include padding. */
pTxInfo->TxInfoPktLen = TransferBufferLength - TXINFO_SIZE;
TransferBufferLength += 4;
/* If TransferBufferLength is multiple of 64, add extra 4 bytes again. */
if ((TransferBufferLength % pAd->BulkOutMaxPacketSize) == 0)
{
NdisZeroMemory(pDest, 4);
TransferBufferLength += 4;
}
/* Fill out frame length information for global Bulk out arbitor. */
pAd->NullContext.BulkOutSize = TransferBufferLength;
}
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
RTMPFrameEndianChange(pAd, (((PUCHAR)pTxInfo) + TXWISize + TXINFO_SIZE), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxInfo, TYPE_TXINFO);
#endif /* RT_BIG_ENDIAN */
hex_dump("ATE TX", &pAd->NullContext.TransferBuffer->field.WirelessPacket[0], TXWISize + TXINFO_SIZE);
return 0;
}
/*
==========================================================================
Description:
Setup Frame format.
NOTE:
This routine should only be used in ATE mode.
==========================================================================
*/
INT ATESetUpFrame(
IN PRTMP_ADAPTER pAd,
IN UINT32 TxIdx)
{
PATE_INFO pATEInfo = &(pAd->ate);
UINT pos = 0;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PNDIS_PACKET pPacket=NULL;
PUCHAR pDest=NULL;
PVOID AllocVa=NULL;
NDIS_PHYSICAL_ADDRESS AllocPa;
HTTRANSMIT_SETTING TxHTPhyMode;
PRTMP_TX_RING pTxRing = &pAd->TxRing[QID_AC_BE];
PTXWI_STRUC pTxWI = (PTXWI_STRUC) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
PUCHAR pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
UINT8 TXWISize = pAd->chipCap.TXWISize;
#ifdef RALINK_QA
PHEADER_802_11 pHeader80211;
#endif /* RALINK_QA */
/* fill TxWI */
TxHTPhyMode.field.BW = pATEInfo->TxWI.BW;
TxHTPhyMode.field.ShortGI = pATEInfo->TxWI.ShortGI;
TxHTPhyMode.field.STBC = pATEInfo->TxWI.STBC;
TxHTPhyMode.field.MCS = pATEInfo->TxWI.MCS;
TxHTPhyMode.field.MODE = pATEInfo->TxWI.PHYMODE;
if (pATEInfo->bQATxStart == TRUE)
{
/* always use QID_AC_BE and FIFO_EDCA */
ATEWriteTxWI(pAd, pTxWI, pATEInfo->TxWI.FRAG, pATEInfo->TxWI.CFACK,
pATEInfo->TxWI.TS, pATEInfo->TxWI.AMPDU, pATEInfo->TxWI.ACK,
pATEInfo->TxWI.NSEQ, pATEInfo->TxWI.BAWinSize, 0,
pATEInfo->TxWI.MPDUtotalByteCount, pATEInfo->TxWI.PacketId, 0, 0,
pATEInfo->TxWI.txop/*IFS_HTTXOP*/, pATEInfo->TxWI.CFACK/*FALSE*/,
&TxHTPhyMode);
}
else
{
ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
4, 0, pATEInfo->TxLength, 0, 0, 0, IFS_HTTXOP, FALSE, &TxHTPhyMode);
}
/* fill 802.11 header */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, pATEInfo->Header, pATEInfo->HLen);
}
else
#endif /* RALINK_QA */
{
pATEInfo->HLen = LENGTH_802_11;
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, TemplateFrame, pATEInfo->HLen);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 4, pATEInfo->Addr1, ETH_LENGTH_OF_ADDRESS);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 10, pATEInfo->Addr2, ETH_LENGTH_OF_ADDRESS);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 16, pATEInfo->Addr3, ETH_LENGTH_OF_ADDRESS);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_READ, FALSE);
#endif /* RT_BIG_ENDIAN */
/* alloc buffer for payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->DLen + 0x100, FALSE, &AllocVa, &AllocPa);
}
else
#endif /* RALINK_QA */
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->TxLength, FALSE, &AllocVa, &AllocPa);
}
if (pPacket == NULL)
{
pATEInfo->TxCount = 0;
DBGPRINT_ERR(("%s : fail to alloc packet space.\n", __FUNCTION__));
return -1;
}
pTxRing->Cell[TxIdx].pNextNdisPacket = pPacket;
pDest = (PUCHAR) AllocVa;
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->DLen;
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->DLen;
}
else
#endif /* RALINK_QA */
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->TxLength - LENGTH_802_11;
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->TxLength - LENGTH_802_11;
}
/* prepare frame payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
/* copy pattern to payload */
if ((pATEInfo->PLen != 0))
{
for (pos = 0; pos < pATEInfo->DLen; pos += pATEInfo->PLen)
{
memcpy(GET_OS_PKT_DATAPTR(pPacket) + pos, pATEInfo->Pattern, pATEInfo->PLen);
}
}
}
else
#endif /* RALINK_QA */
{
for (pos = 0; pos < GET_OS_PKT_LEN(pPacket); pos++)
{
/* default payload is 0xA5 */
pDest[pos] = pATEInfo->Payload;
}
}
/* build Tx descriptor */
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif /* !RT_BIG_ENDIAN */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
/* prepare TxD */
NdisZeroMemory(pTxD, TXD_SIZE);
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + pATEInfo->HLen;
pTxD->SDPtr1 = AllocPa;
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0;
pTxD->LastSec1 = 1;
pDest = (PUCHAR)pTxWI;
pDest += TXWISize;
pHeader80211 = (PHEADER_802_11)pDest;
/* modify sequence number... */
if (pATEInfo->TxDoneCount == 0)
pATEInfo->seq = pHeader80211->Sequence;
else
pHeader80211->Sequence = ++pATEInfo->seq;
}
else
#endif /* RALINK_QA */
{
NdisZeroMemory(pTxD, TXD_SIZE);
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow (pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + LENGTH_802_11;
pTxD->LastSec0 = 0;
pTxD->SDPtr1 = AllocPa;
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec1 = 1;
}
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif /* RT_BIG_ENDIAN */
return 0;
}
NDIS_STATUS MlmeHardTransmitTxRing(
IN PRTMP_ADAPTER pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket)
{
PACKET_INFO PacketInfo;
PUCHAR pSrcBufVA;
UINT SrcBufLen;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PHEADER_802_11 pHeader_802_11;
BOOLEAN bAckRequired, bInsertTimestamp;
ULONG SrcBufPA;
UCHAR MlmeRate;
ULONG SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
PTXWI_STRUC pFirstTxWI;
ULONG FreeNum;
MAC_TABLE_ENTRY *pMacEntry = NULL;
RTMP_QueryPacketInfo(pPacket, &PacketInfo, &pSrcBufVA, &SrcBufLen);
if (pSrcBufVA == NULL)
{
return NDIS_STATUS_FAILURE;
}
FreeNum = GET_TXRING_FREENO(pAd, QueIdx);
if (FreeNum == 0)
{
return NDIS_STATUS_FAILURE;
}
SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC)pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
if (pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket)
{
DBGPRINT(RT_DEBUG_OFF, ("MlmeHardTransmit Error\n"));
return NDIS_STATUS_FAILURE;
}
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
AsicForceWakeup(pAd, TRUE);
}
#endif
pFirstTxWI =(PTXWI_STRUC)pSrcBufVA;
pHeader_802_11 = (PHEADER_802_11) (pSrcBufVA + TXWI_SIZE);
if (pHeader_802_11->Addr1[0] & 0x01)
{
MlmeRate = pAd->CommonCfg.BasicMlmeRate;
}
else
{
MlmeRate = pAd->CommonCfg.MlmeRate;
}
if ((pHeader_802_11->FC.Type == BTYPE_DATA) &&
(pHeader_802_11->FC.SubType == SUBTYPE_QOS_NULL))
{
pMacEntry = MacTableLookup(pAd, pHeader_802_11->Addr1);
}
if ((pAd->LatchRfRegs.Channel > 14) && (MlmeRate < RATE_6))
MlmeRate = RATE_6;
#ifdef CONFIG_STA_SUPPORT
if (pHeader_802_11->FC.Type != BTYPE_DATA)
{
if ((pHeader_802_11->FC.SubType == SUBTYPE_PROBE_REQ) || !(pAd->CommonCfg.bAPSDCapable && pAd->CommonCfg.APEdcaParm.bAPSDCapable))
{
pHeader_802_11->FC.PwrMgmt = PWR_ACTIVE;
}
else
{
pHeader_802_11->FC.PwrMgmt = pAd->CommonCfg.bAPSDForcePowerSave;
}
}
#endif
bInsertTimestamp = FALSE;
if (pHeader_802_11->FC.Type == BTYPE_CNTL)
{
bAckRequired = FALSE;
}
else
{
if (pHeader_802_11->Addr1[0] & 0x01)
{
bAckRequired = FALSE;
pHeader_802_11->Duration = 0;
}
else
{
bAckRequired = TRUE;
pHeader_802_11->Duration = RTMPCalcDuration(pAd, MlmeRate, 14);
if (pHeader_802_11->FC.SubType == SUBTYPE_PROBE_RSP)
{
bInsertTimestamp = TRUE;
}
}
}
pHeader_802_11->Sequence = pAd->Sequence++;
if (pAd->Sequence > 0xfff)
pAd->Sequence = 0;
if ((pHeader_802_11->FC.SubType != SUBTYPE_PROBE_REQ)
&& (pAd->CommonCfg.bIEEE80211H == 1)
&& (pAd->CommonCfg.RadarDetect.RDMode != RD_NORMAL_MODE))
{
DBGPRINT(RT_DEBUG_ERROR,("MlmeHardTransmit --> radar detect not in normal mode !!!\n"));
return (NDIS_STATUS_FAILURE);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader_802_11, DIR_WRITE, FALSE);
#endif
if (pMacEntry == NULL)
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE, bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, RESERVED_WCID, (SrcBufLen - TXWI_SIZE), PID_MGMT, 0, (UCHAR)pAd->CommonCfg.MlmeTransmit.field.MCS, IFS_BACKOFF, FALSE, &pAd->CommonCfg.MlmeTransmit);
}
else
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE,
bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, pMacEntry->Aid, (SrcBufLen - TXWI_SIZE),
pMacEntry->MaxHTPhyMode.field.MCS, 0,
(UCHAR)pMacEntry->MaxHTPhyMode.field.MCS,
IFS_BACKOFF, FALSE, &pMacEntry->MaxHTPhyMode);
}
pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket = pPacket;
pAd->TxRing[QueIdx].Cell[SwIdx].pNextNdisPacket = NULL;
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)pFirstTxWI, TYPE_TXWI);
#endif
SrcBufPA = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_EDCA);
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 1;
pTxD->SDLen0 = SrcBufLen;
pTxD->SDLen1 = 0;
pTxD->SDPtr0 = SrcBufPA;
pTxD->DMADONE = 0;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
INC_RING_INDEX(pAd->TxRing[QueIdx].TxCpuIdx, TX_RING_SIZE);
RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QueIdx*0x10, pAd->TxRing[QueIdx].TxCpuIdx);
return NDIS_STATUS_SUCCESS;
}
/*
========================================================================
Routine Description:
Arguments:
Return Value:
Note: NULL frame use BulkOutPipeId = 0
========================================================================
*/
VOID RTUSBBulkOutNullFrame(
IN PRTMP_ADAPTER pAd,
IN UCHAR BulkOutPipeId)
{
PTX_CONTEXT pNullContext;
PURB pUrb;
int ret = 0;
unsigned long IrqFlags;
if (BulkOutPipeId == EDCA_AC0_PIPE)
pNullContext = &pAd->NullContext[0];
else if (BulkOutPipeId == HCCA_PIPE)
pNullContext = &pAd->NullContext[1];
else
DBGPRINT(RT_DEBUG_ERROR, ("%s: Unknow BulkOut Pipe\n", __FUNCTION__));
RTMP_IRQ_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
if ((pAd->BulkOutPending[BulkOutPipeId] == TRUE) || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_TX))
{
RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
return;
}
pAd->BulkOutPending[BulkOutPipeId] = TRUE;
pAd->watchDogTxPendingCnt[BulkOutPipeId] = 1;
pNullContext->IRPPending = TRUE;
RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
/* Increase Total transmit byte counter*/
pAd->RalinkCounters.TransmittedByteCount += pNullContext->BulkOutSize;
/* Clear Null frame bulk flag*/
if (BulkOutPipeId == EDCA_AC0_PIPE)
RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_NULL);
else if (BulkOutPipeId == HCCA_PIPE)
RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_NULL_HCCA);
else
DBGPRINT(RT_DEBUG_ERROR, ("%s: Unknow BulkOut Pipe\n", __FUNCTION__));
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pNullContext->TransferBuffer, TYPE_TXINFO);
#endif /* RT_BIG_ENDIAN */
/* Init Tx context descriptor*/
/* Init Tx context descriptor*/
if (BulkOutPipeId == EDCA_AC0_PIPE)
RTUSBInitTxDesc(pAd, pNullContext, BulkOutPipeId, (usb_complete_t)RtmpUsbBulkOutNullFrameComplete);
#if defined(CONFIG_MULTI_CHANNEL) || defined(DOT11Z_TDLS_SUPPORT)
else if (BulkOutPipeId == HCCA_PIPE)
RTUSBInitTxDesc(pAd, pNullContext, BulkOutPipeId, (usb_complete_t)RtmpUsbBulkOutHCCANullFrameComplete);
#endif /* defined(CONFIG_MULTI_CHANNEL) || defined(DOT11Z_TDLS_SUPPORT) */
pUrb = pNullContext->pUrb;
if((ret = RTUSB_SUBMIT_URB(pUrb))!=0)
{
RTMP_IRQ_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
pAd->BulkOutPending[BulkOutPipeId] = FALSE;
pAd->watchDogTxPendingCnt[BulkOutPipeId] = 0;
pNullContext->IRPPending = FALSE;
RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
DBGPRINT(RT_DEBUG_ERROR, ("RTUSBBulkOutNullFrame: Submit Tx URB failed %d\n", ret));
return;
}
}
/*
========================================================================
Routine Description:
Get a received packet.
Arguments:
pAd device control block
pSaveRxD receive descriptor information
*pbReschedule need reschedule flag
*pRxPending pending received packet flag
Return Value:
the recieved packet
Note:
========================================================================
*/
PNDIS_PACKET GetPacketFromRxRing(
IN RTMP_ADAPTER *pAd,
OUT RX_BLK *pRxBlk,
OUT BOOLEAN *pbReschedule,
INOUT UINT32 *pRxPending,
OUT BOOLEAN *bCmdRspPacket)
{
RX_CONTEXT *pRxContext;
PNDIS_PACKET pNetPkt;
UCHAR *pData, *RXDMA;
ULONG ThisFrameLen, RxBufferLength, valid_len;
RXWI_STRUC *pRxWI;
UINT8 RXWISize = pAd->chipCap.RXWISize;
RXINFO_STRUC *pRxInfo;
#ifdef RLT_MAC
RXFCE_INFO *pRxFceInfo;
#endif /* RLT_MAC */
*bCmdRspPacket = FALSE;
pRxContext = &pAd->RxContext[pAd->NextRxBulkInReadIndex];
if ((pRxContext->Readable == FALSE) || (pRxContext->InUse == TRUE))
return NULL;
RxBufferLength = pRxContext->BulkInOffset - pAd->ReadPosition;
valid_len = RXDMA_FIELD_SIZE * 2;
if (RxBufferLength < valid_len)
{
goto label_null;
}
pData = &pRxContext->TransferBuffer[pAd->ReadPosition];
RXDMA = pData;
/* The RXDMA field is 4 bytes, now just use the first 2 bytes. The Length including the (RXWI + MSDU + Padding) */
ThisFrameLen = *pData + (*(pData+1)<<8);
if (ThisFrameLen == 0)
{
DBGPRINT(RT_DEBUG_TRACE, ("BIRIdx(%d): RXDMALen is zero.[%ld], BulkInBufLen = %ld)\n",
pAd->NextRxBulkInReadIndex, ThisFrameLen, pRxContext->BulkInOffset));
goto label_null;
}
if ((ThisFrameLen & 0x3) != 0)
{
DBGPRINT(RT_DEBUG_ERROR, ("BIRIdx(%d): RXDMALen not multiple of 4.[%ld], BulkInBufLen = %ld)\n",
pAd->NextRxBulkInReadIndex, ThisFrameLen, pRxContext->BulkInOffset));
goto label_null;
}
if ((ThisFrameLen + 8) > RxBufferLength) /* 8 for (RXDMA_FIELD_SIZE + sizeof(RXINFO_STRUC))*/
{
DBGPRINT(RT_DEBUG_ERROR,("BIRIdx(%d):FrameLen(0x%lx) outranges. BulkInLen=0x%lx, remaining RxBufLen=0x%lx, ReadPos=0x%lx\n",
pAd->NextRxBulkInReadIndex, ThisFrameLen, pRxContext->BulkInOffset, RxBufferLength, pAd->ReadPosition));
/* error frame. finish this loop*/
goto label_null;
}
/* skip USB frame length field*/
pData += RXDMA_FIELD_SIZE;
#ifdef RLT_MAC
pRxFceInfo = (RXFCE_INFO *)(pData + ThisFrameLen);
/* Check if command response or data packet */
if ((pRxFceInfo->info_type == CMD_PACKET) && (pAd->chipCap.CmdRspRxRing == RX_RING0))
{
//CmdRspEventCallbackHandle(pAd, RXDMA);
/* Update next packet read position.*/
pAd->ReadPosition += (sizeof(*pRxFceInfo) * 2 + pRxFceInfo->pkt_len);
*bCmdRspPacket = TRUE;
goto label_null;
}
pRxInfo = (RXINFO_STRUC *)pData;
pData += RXINFO_SIZE;
#endif /* RLT_MAC */
#ifdef RTMP_MAC
pRxInfo = *(RXINFO_STRUC *)(pData + ThisFrameLen);
#endif /* RTMP_MAC */
pRxWI = (RXWI_STRUC *)pData;
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, pData, TYPE_RXWI);
#endif /* RT_BIG_ENDIAN */
if (pRxWI->RxWIMPDUByteCnt > ThisFrameLen)
{
DBGPRINT(RT_DEBUG_ERROR, ("%s():pRxWIMPDUtotalByteCount(%d) large than RxDMALen(%ld)\n",
__FUNCTION__, pRxWI->RxWIMPDUByteCnt, ThisFrameLen));
goto label_null;
}
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, pData, TYPE_RXWI);
#endif /* RT_BIG_ENDIAN */
/* allocate a rx packet*/
pNetPkt = RTMP_AllocateFragPacketBuffer(pAd, ThisFrameLen);
if (pNetPkt == NULL)
{
DBGPRINT(RT_DEBUG_ERROR,("%s():Cannot Allocate sk buffer for this Bulk-In buffer!\n", __FUNCTION__));
goto label_null;
}
/* copy the rx packet*/
RTMP_USB_PKT_COPY(get_netdev_from_bssid(pAd, BSS0), pNetPkt, ThisFrameLen, pData);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxInfo, TYPE_RXINFO);
#endif /* RT_BIG_ENDIAN */
#ifdef RLT_MAC
NdisMoveMemory((VOID *)&pRxBlk->hw_rx_info[0], (VOID *)pRxFceInfo, sizeof(RXFCE_INFO));
pRxBlk->pRxFceInfo = (RXFCE_INFO *)&pRxBlk->hw_rx_info[0];
#endif /* RLT_MAC */
NdisMoveMemory(&pRxBlk->hw_rx_info[RXINFO_OFFSET], pRxInfo, RXINFO_SIZE);
pRxBlk->pRxInfo = (RXINFO_STRUC *)&pRxBlk->hw_rx_info[RXINFO_OFFSET];
/* update next packet read position.*/
pAd->ReadPosition += (ThisFrameLen + RXDMA_FIELD_SIZE + RXINFO_SIZE); /* 8 for (RXDMA_FIELD_SIZE + sizeof(RXINFO_STRUC))*/
return pNetPkt;
label_null:
return NULL;
}
BOOLEAN RTMPFreeTXDUponTxDmaDone(
IN PRTMP_ADAPTER pAd,
IN UCHAR QueIdx)
{
PRTMP_TX_RING pTxRing;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
#endif
PNDIS_PACKET pPacket;
UCHAR FREE = 0;
TXD_STRUC TxD, *pOriTxD;
//ULONG IrqFlags;
BOOLEAN bReschedule = FALSE;
ASSERT(QueIdx < NUM_OF_TX_RING);
pTxRing = &pAd->TxRing[QueIdx];
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF, &pTxRing->TxDmaIdx);
while (pTxRing->TxSwFreeIdx != pTxRing->TxDmaIdx)
{
// RTMP_IRQ_LOCK(&pAd->irq_lock, IrqFlags);
#ifdef RALINK_ATE
#ifdef RALINK_QA
PHEADER_802_11 pHeader80211;
if ((ATE_ON(pAd)) && (pAd->ate.bQATxStart == TRUE))
{
if (pAd->ate.QID == QueIdx)
{
pAd->ate.TxDoneCount++;
pAd->RalinkCounters.KickTxCount++;
/* always use QID_AC_BE and FIFO_EDCA */
ASSERT(pAd->ate.QID == 0);
pAd->ate.TxAc0++;
FREE++;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
pHeader80211 = pTxRing->Cell[pTxRing->TxSwFreeIdx].DmaBuf.AllocVa + sizeof(TXWI_STRUC);
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader80211, DIR_READ, FALSE);
#endif
pHeader80211->Sequence = ++pAd->ate.seq;
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader80211, DIR_WRITE, FALSE);
#endif
if ((pAd->ate.bQATxStart == TRUE) && (pAd->ate.Mode & ATE_TXFRAME) && (pAd->ate.TxDoneCount < pAd->ate.TxCount))
{
pAd->RalinkCounters.TransmittedByteCount.QuadPart += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecTransmittedByteCount += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecDmaDoneCount[QueIdx] ++;
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
/* get TX_DTX_IDX again */
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF , &pTxRing->TxDmaIdx);
goto kick_out;
}
else if ((pAd->ate.TxStatus == 1)/* or (pAd->ate.bQATxStart == TRUE) ??? */ && (pAd->ate.TxDoneCount == pAd->ate.TxCount))
{
DBGPRINT(RT_DEBUG_TRACE,("all Tx is done\n"));
// Tx status enters idle mode.
pAd->ate.TxStatus = 0;
}
else if (!(pAd->ate.Mode & ATE_TXFRAME))
{
/* not complete sending yet, but someone press the Stop TX botton */
DBGPRINT(RT_DEBUG_INFO,("not complete sending yet, but someone pressed the Stop TX bottom\n"));
DBGPRINT(RT_DEBUG_INFO,("pAd->ate.Mode = 0x%02x\n", pAd->ate.Mode));
}
else
{
DBGPRINT(RT_DEBUG_OFF,("pTxRing->TxSwFreeIdx = %d\n", pTxRing->TxSwFreeIdx));
}
#ifndef RT_BIG_ENDIAN
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#else
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#endif // RT_BIG_ENDIAN //
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
continue;
}
}
#endif // RALINK_QA //
#endif // RALINK_ATE //
// static rate also need NICUpdateFifoStaCounters() function.
//if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED))
#ifdef VENDOR_FEATURE1_SUPPORT
/*
Note:
Can not take off the NICUpdateFifoStaCounters(); Or the
FIFO overflow rate will be high, i.e. > 3%
(see the rate by "iwpriv ra0 show stainfo")
Based on different platform, try to find the best value to
replace '4' here (overflow rate target is about 0%).
*/
if (++pAd->FifoUpdateRx >= 4)
{
NICUpdateFifoStaCounters(pAd);
pAd->FifoUpdateRx = 0;
}
#else
NICUpdateFifoStaCounters(pAd);
#endif // VENDOR_FEATURE1_SUPPORT //
/* Note : If (pAd->ate.bQATxStart == TRUE), we will never reach here. */
FREE++;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
#ifdef CONFIG_AP_SUPPORT
#ifdef UAPSD_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
UAPSD_SP_PacketCheck(pAd,
pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket,
((UCHAR *)pTxRing->Cell[\
pTxRing->TxSwFreeIdx].DmaBuf.AllocVa)+TXWI_SIZE);
}
#endif // UAPSD_AP_SUPPORT //
#endif // CONFIG_AP_SUPPORT //
#ifdef RALINK_ATE
/* Execution of this block is not allowed when ATE is running. */
if (!(ATE_ON(pAd)))
#endif // RALINK_ATE //
{
pPacket = pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket;
if (pPacket)
{
#ifdef CONFIG_5VT_ENHANCE
if (RTMP_GET_PACKET_5VT(pPacket))
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, 16, PCI_DMA_TODEVICE);
else
#endif // CONFIG_5VT_ENHANCE //
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
//Always assign pNdisPacket as NULL after clear
pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket = NULL;
pPacket = pTxRing->Cell[pTxRing->TxSwFreeIdx].pNextNdisPacket;
if (pPacket)
{
#ifdef CONFIG_5VT_ENHANCE
if (RTMP_GET_PACKET_5VT(pPacket))
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, 16, PCI_DMA_TODEVICE);
else
#endif // CONFIG_5VT_ENHANCE //
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
//Always assign pNextNdisPacket as NULL after clear
pTxRing->Cell[pTxRing->TxSwFreeIdx].pNextNdisPacket = NULL;
}
pAd->RalinkCounters.TransmittedByteCount.QuadPart += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecTransmittedByteCount += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecDmaDoneCount[QueIdx] ++;
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
/* get tx_tdx_idx again */
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF , &pTxRing->TxDmaIdx);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#else
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#endif
#ifdef RALINK_ATE
#ifdef RALINK_QA
kick_out:
#endif // RALINK_QA //
/*
ATE_TXCONT mode also need to send some normal frames, so let it in.
ATE_STOP must be changed not to be 0xff
to prevent it from running into this block.
*/
if ((pAd->ate.Mode & ATE_TXFRAME) && (pAd->ate.QID == QueIdx))
{
// TxDoneCount++ has been done if QA is used.
if (pAd->ate.bQATxStart == FALSE)
{
pAd->ate.TxDoneCount++;
}
if (((pAd->ate.TxCount - pAd->ate.TxDoneCount + 1) >= TX_RING_SIZE))
{
/* Note : We increase TxCpuIdx here, not TxSwFreeIdx ! */
INC_RING_INDEX(pAd->TxRing[QueIdx].TxCpuIdx, TX_RING_SIZE);
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pAd->TxRing[QueIdx].TxCpuIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pAd->TxRing[QueIdx].TxCpuIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
#ifndef RT_BIG_ENDIAN
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#else
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#endif
// kick Tx-Ring
RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QueIdx * RINGREG_DIFF, pAd->TxRing[QueIdx].TxCpuIdx);
pAd->RalinkCounters.KickTxCount++;
}
}
#endif // RALINK_ATE //
// RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags);
}
return bReschedule;
}
/*
Must be run in Interrupt context
This function handle PCI specific TxDesc and cpu index update and kick the packet out.
*/
int RtmpPCIMgmtKickOut(
IN RTMP_ADAPTER *pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket,
IN PUCHAR pSrcBufVA,
IN UINT SrcBufLen)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
ULONG SwIdx = pAd->MgmtRing.TxCpuIdx;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC)pAd->MgmtRing.Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) pAd->MgmtRing.Cell[SwIdx].AllocVa;
#endif
pAd->MgmtRing.Cell[SwIdx].pNdisPacket = pPacket;
pAd->MgmtRing.Cell[SwIdx].pNextNdisPacket = NULL;
RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_MGMT);
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 1;
pTxD->DMADONE = 0;
pTxD->SDLen1 = 0;
pTxD->SDPtr0 = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
pTxD->SDLen0 = SrcBufLen;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
//==================================================================
/* DBGPRINT_RAW(RT_DEBUG_TRACE, ("MLMEHardTransmit\n"));
for (i = 0; i < (TXWI_SIZE+24); i++)
{
DBGPRINT_RAW(RT_DEBUG_TRACE, ("%x:", *(pSrcBufVA+i)));
if ( i%4 == 3)
DBGPRINT_RAW(RT_DEBUG_TRACE, (" :: "));
if ( i%16 == 15)
DBGPRINT_RAW(RT_DEBUG_TRACE, ("\n "));
}
DBGPRINT_RAW(RT_DEBUG_TRACE, ("\n "));*/
//=======================================================================
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
// Increase TX_CTX_IDX, but write to register later.
INC_RING_INDEX(pAd->MgmtRing.TxCpuIdx, MGMT_RING_SIZE);
RTMP_IO_WRITE32(pAd, TX_MGMTCTX_IDX, pAd->MgmtRing.TxCpuIdx);
return 0;
}
PNDIS_PACKET GetPacketFromRxRing(
IN PRTMP_ADAPTER pAd,
OUT PRT28XX_RXD_STRUC pSaveRxD,
OUT BOOLEAN *pbReschedule,
IN OUT UINT32 *pRxPending)
{
PRXD_STRUC pRxD;
#ifdef RT_BIG_ENDIAN
PRXD_STRUC pDestRxD;
RXD_STRUC RxD;
#endif
PNDIS_PACKET pRxPacket = NULL;
PNDIS_PACKET pNewPacket;
PVOID AllocVa;
NDIS_PHYSICAL_ADDRESS AllocPa;
BOOLEAN bReschedule = FALSE;
RTMP_DMACB *pRxCell;
RTMP_SEM_LOCK(&pAd->RxRingLock);
if (*pRxPending == 0)
{
// Get how may packets had been received
RTMP_IO_READ32(pAd, RX_DRX_IDX , &pAd->RxRing.RxDmaIdx);
if (pAd->RxRing.RxSwReadIdx == pAd->RxRing.RxDmaIdx)
{
// no more rx packets
bReschedule = FALSE;
goto done;
}
// get rx pending count
if (pAd->RxRing.RxDmaIdx > pAd->RxRing.RxSwReadIdx)
*pRxPending = pAd->RxRing.RxDmaIdx - pAd->RxRing.RxSwReadIdx;
else
*pRxPending = pAd->RxRing.RxDmaIdx + RX_RING_SIZE - pAd->RxRing.RxSwReadIdx;
}
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx];
#ifdef RT_BIG_ENDIAN
pDestRxD = (PRXD_STRUC) pRxCell->AllocVa;
RxD = *pDestRxD;
pRxD = &RxD;
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
#else
// Point to Rx indexed rx ring descriptor
pRxD = (PRXD_STRUC) pRxCell->AllocVa;
#endif
if (pRxD->DDONE == 0)
{
*pRxPending = 0;
// DMAIndx had done but DDONE bit not ready
bReschedule = TRUE;
goto done;
}
// return rx descriptor
NdisMoveMemory(pSaveRxD, pRxD, RXD_SIZE);
pNewPacket = RTMP_AllocateRxPacketBuffer(pAd, RX_BUFFER_AGGRESIZE, FALSE, &AllocVa, &AllocPa);
if (pNewPacket)
{
// unmap the rx buffer
PCI_UNMAP_SINGLE(pAd, pRxCell->DmaBuf.AllocPa,
pRxCell->DmaBuf.AllocSize, PCI_DMA_FROMDEVICE);
pRxPacket = pRxCell->pNdisPacket;
pRxCell->DmaBuf.AllocSize = RX_BUFFER_AGGRESIZE;
pRxCell->pNdisPacket = (PNDIS_PACKET) pNewPacket;
pRxCell->DmaBuf.AllocVa = AllocVa;
pRxCell->DmaBuf.AllocPa = AllocPa;
/* update SDP0 to new buffer of rx packet */
pRxD->SDP0 = AllocPa;
}
else
{
//DBGPRINT(RT_DEBUG_TRACE,("No Rx Buffer\n"));
pRxPacket = NULL;
bReschedule = TRUE;
}
pRxD->DDONE = 0;
// had handled one rx packet
*pRxPending = *pRxPending - 1;
// update rx descriptor and kick rx
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxD, (PUCHAR)pRxD, FALSE, TYPE_RXD);
#endif
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
done:
RTMP_SEM_UNLOCK(&pAd->RxRingLock);
*pbReschedule = bReschedule;
return pRxPacket;
}
USHORT RtmpPCI_WriteMultiTxResource(
IN PRTMP_ADAPTER pAd,
IN TX_BLK *pTxBlk,
IN UCHAR frameNum,
OUT USHORT *FreeNumber)
{
BOOLEAN bIsLast;
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHdrLen;
UINT32 firstDMALen;
bIsLast = ((frameNum == (pTxBlk->TotalFrameNum - 1)) ? 1 : 0);
pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
BufBasePaLow = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
if (frameNum == 0)
{
if (pTxBlk->TxFrameType == TX_AMSDU_FRAME)
hwHdrLen = pTxBlk->MpduHeaderLen - LENGTH_AMSDU_SUBFRAMEHEAD + pTxBlk->HdrPadLen + LENGTH_AMSDU_SUBFRAMEHEAD;
else if (pTxBlk->TxFrameType == TX_RALINK_FRAME)
hwHdrLen = pTxBlk->MpduHeaderLen - LENGTH_ARALINK_HEADER_FIELD + pTxBlk->HdrPadLen + LENGTH_ARALINK_HEADER_FIELD;
else
hwHdrLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
firstDMALen = TXINFO_SIZE + TXWI_SIZE + hwHdrLen;
}
else
{
firstDMALen = pTxBlk->MpduHeaderLen;
}
NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf, firstDMALen);
pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
NdisZeroMemory(pTxD, TXD_SIZE);
pTxD->SDPtr0 = BufBasePaLow;
pTxD->SDLen0 = firstDMALen;
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, PCI_DMA_TODEVICE);;
pTxD->SDLen1 = pTxBlk->SrcBufLen;
pTxD->LastSec0 = 0;
pTxD->LastSec1 = (bIsLast) ? 1 : 0;
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
if (frameNum == 0)
RTMPFrameEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA+ TXINFO_SIZE + TXWI_SIZE), DIR_WRITE, FALSE);
if (frameNum != 0)
RTMPWIEndianChange((PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE), TYPE_TXWI);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
RetTxIdx = TxIdx;
INC_RING_INDEX(TxIdx, TX_RING_SIZE);
pTxRing->TxCpuIdx = TxIdx;
*FreeNumber -= 1;
return RetTxIdx;
}
/*
==========================================================================
Description:
Setup Frame format.
NOTE:
This routine should only be used in ATE mode.
==========================================================================
*/
INT ATESetUpFrame(
IN PRTMP_ADAPTER pAd,
IN UINT32 TxIdx)
{
PATE_INFO pATEInfo = &(pAd->ate);
UINT pos = 0;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PNDIS_PACKET pPacket=NULL;
PUCHAR pDest=NULL;
PVOID AllocVa=NULL;
NDIS_PHYSICAL_ADDRESS AllocPa;
HTTRANSMIT_SETTING TxHTPhyMode;
PRTMP_TX_RING pTxRing = &pAd->TxRing[QID_AC_BE];
PTXWI_STRUC pTxWI = (PTXWI_STRUC) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
PUCHAR pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
UINT8 TXWISize = pAd->chipCap.TXWISize;
#ifdef RALINK_QA
PHEADER_802_11 pHeader80211;
#endif /* RALINK_QA */
/* fill TxWI */
TxHTPhyMode.field.BW = pATEInfo->TxWI.BW;
TxHTPhyMode.field.ShortGI = pATEInfo->TxWI.ShortGI;
TxHTPhyMode.field.STBC = pATEInfo->TxWI.STBC;
TxHTPhyMode.field.MCS = pATEInfo->TxWI.MCS;
TxHTPhyMode.field.MODE = pATEInfo->TxWI.PHYMODE;
if (pATEInfo->bQATxStart == TRUE)
{
/* always use QID_AC_BE and FIFO_EDCA */
ATEWriteTxWI(pAd, pTxWI, pATEInfo->TxWI.FRAG, pATEInfo->TxWI.CFACK,
pATEInfo->TxWI.TS, pATEInfo->TxWI.AMPDU, pATEInfo->TxWI.ACK,
pATEInfo->TxWI.NSEQ, pATEInfo->TxWI.BAWinSize, 0,
pATEInfo->TxWI.MPDUtotalByteCount, pATEInfo->TxWI.PacketId, 0, 0,
pATEInfo->TxWI.txop/*IFS_HTTXOP*/, pATEInfo->TxWI.CFACK/*FALSE*/,
&TxHTPhyMode);
#ifdef TXBF_SUPPORT
if (IS_RT2883(pAd) || IS_RT3883(pAd))
{
/* Must copy rsv bits to actual TxWI */
pTxWI->rsv = pATEInfo->TxWI.rsv;
pTxWI->iTxBF = pATEInfo->TxWI.iTxBF;
pTxWI->Sounding = pATEInfo->TxWI.Sounding;
pTxWI->eTxBF = pATEInfo->TxWI.eTxBF;
pTxWI->Autofallback = pATEInfo->TxWI.Autofallback;
pTxWI->NDPSndBW = pATEInfo->TxWI.NDPSndBW;
pTxWI->NDPSndRate = pATEInfo->TxWI.NDPSndRate;
}
#endif /* TXBF_SUPPORT */
}
else
{
ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
4, 0, pATEInfo->TxLength, 0, 0, 0, IFS_HTTXOP, FALSE, &TxHTPhyMode);
#ifdef TXBF_SUPPORT
if (pATEInfo->bTxBF == 1)
{
if (IS_RT2883(pAd) || IS_RT3883(pAd))
{
pTxWI->rsv = 0;
pTxWI->iTxBF = pATEInfo->TxWI.iTxBF;
pTxWI->Sounding = (pATEInfo->txSoundingMode == 1 ? 1 : 0);
pTxWI->eTxBF = pATEInfo->TxWI.eTxBF;
pTxWI->Autofallback = pATEInfo->TxWI.Autofallback;
pTxWI->NDPSndBW = pATEInfo->TxWI.BW;
if (pATEInfo->txSoundingMode == 3)
pTxWI->NDPSndRate = 2;
else if (pATEInfo->txSoundingMode == 2)
pTxWI->NDPSndRate = 1;
else
pTxWI->NDPSndRate = 0;
}
}
#endif /* TXBF_SUPPORT */
}
/* fill 802.11 header */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, pATEInfo->Header, pATEInfo->HLen);
}
else
#endif /* RALINK_QA */
{
pATEInfo->HLen = LENGTH_802_11;
#ifdef TXBF_SUPPORT
TemplateFrame[0] = 0x08; /* Data */
TemplateFrame[1] = 0x00;
if (pATEInfo->bTxBF && pATEInfo->txSoundingMode!=0)
{
/* QoS Data */
pATEInfo->HLen = 32;
TemplateFrame[0] = 0x88;
TemplateFrame[1] = 0x80;
switch (pATEInfo->txSoundingMode)
{
case 1:
/* Data Sounding */
TemplateFrame[28] = pAd->CommonCfg.ETxBfNoncompress? 0x80: 0xc0;
TemplateFrame[29] = 0x00;
break;
case 2:
case 3:
/* 2 or 3 Stream NDP */
TemplateFrame[28] = pAd->CommonCfg.ETxBfNoncompress? 0x80: 0xc0;
TemplateFrame[29] = 0x01; /* NDP Announce */
break;
default:
TemplateFrame[28] = TemplateFrame[29] = 0x0;
}
}
#endif /* TXBF_SUPPORT */
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, TemplateFrame, pATEInfo->HLen);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 4, pATEInfo->Addr1, ETH_LENGTH_OF_ADDRESS);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 10, pATEInfo->Addr2, ETH_LENGTH_OF_ADDRESS);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 16, pATEInfo->Addr3, ETH_LENGTH_OF_ADDRESS);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_READ, FALSE);
#endif /* RT_BIG_ENDIAN */
/* alloc buffer for payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->DLen + 0x100, FALSE, &AllocVa, &AllocPa);
}
else
#endif /* RALINK_QA */
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->TxLength, FALSE, &AllocVa, &AllocPa);
}
if (pPacket == NULL)
{
pATEInfo->TxCount = 0;
DBGPRINT_ERR(("%s : fail to alloc packet space.\n", __FUNCTION__));
return -1;
}
pTxRing->Cell[TxIdx].pNextNdisPacket = pPacket;
pDest = (PUCHAR) AllocVa;
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->DLen;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->DLen;
#endif /* LIMUX */
}
else
#endif /* RALINK_QA */
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->TxLength - LENGTH_802_11;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->TxLength - LENGTH_802_11;
#endif /* LINUX */
}
/* prepare frame payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
/* copy pattern to payload */
if ((pATEInfo->PLen != 0))
{
for (pos = 0; pos < pATEInfo->DLen; pos += pATEInfo->PLen)
{
memcpy(GET_OS_PKT_DATAPTR(pPacket) + pos, pATEInfo->Pattern, pATEInfo->PLen);
}
}
}
else
#endif /* RALINK_QA */
{
for (pos = 0; pos < GET_OS_PKT_LEN(pPacket); pos++)
{
/* default payload is 0xA5 */
pDest[pos] = pATEInfo->Payload;
}
}
/* build Tx descriptor */
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif /* !RT_BIG_ENDIAN */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
/* prepare TxD */
NdisZeroMemory(pTxD, TXD_SIZE);
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + pATEInfo->HLen;
pTxD->SDPtr1 = AllocPa;
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0;
pTxD->LastSec1 = 1;
pDest = (PUCHAR)pTxWI;
pDest += TXWISize;
pHeader80211 = (PHEADER_802_11)pDest;
/* modify sequence number... */
if (pATEInfo->TxDoneCount == 0)
pATEInfo->seq = pHeader80211->Sequence;
else
pHeader80211->Sequence = ++pATEInfo->seq;
}
else
#endif /* RALINK_QA */
{
NdisZeroMemory(pTxD, TXD_SIZE);
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow (pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + LENGTH_802_11;
pTxD->LastSec0 = 0;
pTxD->SDPtr1 = AllocPa;
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec1 = 1;
}
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif /* RT_BIG_ENDIAN */
return 0;
}
/*
========================================================================
Routine Description:
Get a received packet.
Arguments:
pAd device control block
pSaveRxD receive descriptor information
*pbReschedule need reschedule flag
*pRxPending pending received packet flag
Return Value:
the recieved packet
Note:
========================================================================
*/
PNDIS_PACKET GetPacketFromRxRing(
IN PRTMP_ADAPTER pAd,
OUT PRT28XX_RXD_STRUC pSaveRxD,
OUT BOOLEAN *pbReschedule,
IN OUT UINT32 *pRxPending)
{
PRX_CONTEXT pRxContext;
PNDIS_PACKET pNetPkt;
PUCHAR pData;
ULONG ThisFrameLen;
ULONG RxBufferLength;
PRXWI_STRUC pRxWI;
pRxContext = &pAd->RxContext[pAd->NextRxBulkInReadIndex];
if ((pRxContext->Readable == FALSE) || (pRxContext->InUse == TRUE))
return NULL;
RxBufferLength = pRxContext->BulkInOffset - pAd->ReadPosition;
if (RxBufferLength < (RT2870_RXDMALEN_FIELD_SIZE + sizeof(RXWI_STRUC) + sizeof(RXINFO_STRUC)))
{
goto label_null;
}
pData = &pRxContext->TransferBuffer[pAd->ReadPosition]; /* 4KB */
// The RXDMA field is 4 bytes, now just use the first 2 bytes. The Length including the (RXWI + MSDU + Padding)
ThisFrameLen = *pData + (*(pData+1)<<8);
if (ThisFrameLen == 0)
{
DBGPRINT(RT_DEBUG_TRACE, ("BIRIdx(%d): RXDMALen is zero.[%ld], BulkInBufLen = %ld)\n",
pAd->NextRxBulkInReadIndex, ThisFrameLen, pRxContext->BulkInOffset));
goto label_null;
}
if ((ThisFrameLen&0x3) != 0)
{
DBGPRINT(RT_DEBUG_ERROR, ("BIRIdx(%d): RXDMALen not multiple of 4.[%ld], BulkInBufLen = %ld)\n",
pAd->NextRxBulkInReadIndex, ThisFrameLen, pRxContext->BulkInOffset));
goto label_null;
}
if ((ThisFrameLen + 8)> RxBufferLength) // 8 for (RT2870_RXDMALEN_FIELD_SIZE + sizeof(RXINFO_STRUC))
{
DBGPRINT(RT_DEBUG_TRACE,("BIRIdx(%d):FrameLen(0x%lx) outranges. BulkInLen=0x%lx, remaining RxBufLen=0x%lx, ReadPos=0x%lx\n",
pAd->NextRxBulkInReadIndex, ThisFrameLen, pRxContext->BulkInOffset, RxBufferLength, pAd->ReadPosition));
// error frame. finish this loop
goto label_null;
}
// skip USB frame length field
pData += RT2870_RXDMALEN_FIELD_SIZE;
pRxWI = (PRXWI_STRUC)pData;
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pData, TYPE_RXWI);
#endif // RT_BIG_ENDIAN //
if (pRxWI->MPDUtotalByteCount > ThisFrameLen)
{
DBGPRINT(RT_DEBUG_ERROR, ("%s():pRxWIMPDUtotalByteCount(%d) large than RxDMALen(%ld)\n",
__FUNCTION__, pRxWI->MPDUtotalByteCount, ThisFrameLen));
goto label_null;
}
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pData, TYPE_RXWI);
#endif // RT_BIG_ENDIAN //
// allocate a rx packet
pNetPkt = RTMP_AllocateFragPacketBuffer(pAd, ThisFrameLen);
if (pNetPkt == NULL)
{
DBGPRINT(RT_DEBUG_ERROR,("%s():Cannot Allocate sk buffer for this Bulk-In buffer!\n", __FUNCTION__));
goto label_null;
}
// copy the rx packet
memcpy(skb_put(pNetPkt, ThisFrameLen), pData, ThisFrameLen);
GET_OS_PKT_NETDEV(pNetPkt) = get_netdev_from_bssid(pAd, BSS0);;
RTMP_SET_PACKET_SOURCE(OSPKT_TO_RTPKT(pNetPkt), PKTSRC_NDIS);
// copy RxD
*pSaveRxD = *(PRXINFO_STRUC)(pData + ThisFrameLen);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pSaveRxD, TYPE_RXINFO);
#endif // RT_BIG_ENDIAN //
// update next packet read position.
pAd->ReadPosition += (ThisFrameLen + RT2870_RXDMALEN_FIELD_SIZE + RXINFO_SIZE); // 8 for (RT2870_RXDMALEN_FIELD_SIZE + sizeof(RXINFO_STRUC))
return pNetPkt;
label_null:
return NULL;
}
BOOLEAN RTMPFreeTXDUponTxDmaDone(
IN PRTMP_ADAPTER pAd,
IN UCHAR QueIdx)
{
PRTMP_TX_RING pTxRing;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
#endif
PNDIS_PACKET pPacket;
UCHAR FREE = 0;
TXD_STRUC TxD, *pOriTxD;
BOOLEAN bReschedule = FALSE;
ASSERT(QueIdx < NUM_OF_TX_RING);
pTxRing = &pAd->TxRing[QueIdx];
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF, &pTxRing->TxDmaIdx);
while (pTxRing->TxSwFreeIdx != pTxRing->TxDmaIdx)
{
#ifdef RALINK_ATE
#ifdef RALINK_28xx_QA
PHEADER_802_11 pHeader80211;
if ((ATE_ON(pAd)) && (pAd->ate.bQATxStart == TRUE))
{
if (pAd->ate.QID == QueIdx)
{
pAd->ate.TxDoneCount++;
pAd->RalinkCounters.KickTxCount++;
ASSERT(pAd->ate.QID == 0);
pAd->ate.TxAc0++;
FREE++;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
pHeader80211 = pTxRing->Cell[pTxRing->TxSwFreeIdx].DmaBuf.AllocVa + sizeof(TXWI_STRUC);
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader80211, DIR_READ, FALSE);
#endif
pHeader80211->Sequence = ++pAd->ate.seq;
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader80211, DIR_WRITE, FALSE);
#endif
if ((pAd->ate.bQATxStart == TRUE) && (pAd->ate.Mode & ATE_TXFRAME) && (pAd->ate.TxDoneCount < pAd->ate.TxCount))
{
pAd->RalinkCounters.TransmittedByteCount += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecTransmittedByteCount += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecDmaDoneCount[QueIdx] ++;
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF , &pTxRing->TxDmaIdx);
goto kick_out;
}
else if ((pAd->ate.TxStatus == 1) && (pAd->ate.TxDoneCount == pAd->ate.TxCount))
{
DBGPRINT(RT_DEBUG_TRACE,("all Tx is done\n"));
pAd->ate.TxStatus = 0;
}
else if (!(pAd->ate.Mode & ATE_TXFRAME))
{
DBGPRINT(RT_DEBUG_ERROR,("not complete sending yet, but someone pressed the Stop TX bottom\n"));
DBGPRINT(RT_DEBUG_ERROR,("pAd->ate.Mode = 0x%02x\n", pAd->ate.Mode));
}
else
{
DBGPRINT(RT_DEBUG_OFF,("pTxRing->TxSwFreeIdx = %d\n", pTxRing->TxSwFreeIdx));
}
#ifndef RT_BIG_ENDIAN
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#else
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#endif
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
continue;
}
}
#endif
#endif
NICUpdateFifoStaCounters(pAd);
FREE++;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
#ifdef RALINK_ATE
if (!(ATE_ON(pAd)))
#endif
{
pPacket = pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket;
if (pPacket)
{
#ifdef CONFIG_5VT_ENHANCE
if (RTMP_GET_PACKET_5VT(pPacket))
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, 16, PCI_DMA_TODEVICE);
else
#endif
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket = NULL;
pPacket = pTxRing->Cell[pTxRing->TxSwFreeIdx].pNextNdisPacket;
ASSERT(pPacket == NULL);
if (pPacket)
{
#ifdef CONFIG_5VT_ENHANCE
if (RTMP_GET_PACKET_5VT(pPacket))
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, 16, PCI_DMA_TODEVICE);
else
#endif
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pTxRing->Cell[pTxRing->TxSwFreeIdx].pNextNdisPacket = NULL;
}
pAd->RalinkCounters.TransmittedByteCount += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecDmaDoneCount[QueIdx] ++;
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF , &pTxRing->TxDmaIdx);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#else
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#endif
#ifdef RALINK_ATE
#ifdef RALINK_28xx_QA
kick_out:
#endif
if ((pAd->ate.Mode & ATE_TXFRAME) && (pAd->ate.QID == QueIdx))
{
if (pAd->ate.bQATxStart == FALSE)
{
pAd->ate.TxDoneCount++;
}
if (((pAd->ate.TxCount - pAd->ate.TxDoneCount + 1) >= TX_RING_SIZE))
{
INC_RING_INDEX(pAd->TxRing[QueIdx].TxCpuIdx, TX_RING_SIZE);
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pAd->TxRing[QueIdx].TxCpuIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pAd->TxRing[QueIdx].TxCpuIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
#ifndef RT_BIG_ENDIAN
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#else
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#endif
RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QueIdx * RINGREG_DIFF, pAd->TxRing[QueIdx].TxCpuIdx);
pAd->RalinkCounters.KickTxCount++;
}
}
#endif
}
return bReschedule;
}
USHORT RtmpPCI_WriteFragTxResource(
IN PRTMP_ADAPTER pAd,
IN TX_BLK *pTxBlk,
IN UCHAR fragNum,
OUT USHORT *FreeNumber)
{
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHeaderLen;
UINT32 firstDMALen;
pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
BufBasePaLow = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
hwHeaderLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
firstDMALen = TXINFO_SIZE + TXWI_SIZE + hwHeaderLen;
NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf, firstDMALen);
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
NdisZeroMemory(pTxD, TXD_SIZE);
if (fragNum == pTxBlk->TotalFragNum)
{
pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
}
pTxD->SDPtr0 = BufBasePaLow;
pTxD->SDLen0 = firstDMALen;
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, PCI_DMA_TODEVICE);
pTxD->SDLen1 = pTxBlk->SrcBufLen;
pTxD->LastSec0 = 0;
pTxD->LastSec1 = 1;
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE), TYPE_TXWI);
RTMPFrameEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE + TXWI_SIZE), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
RetTxIdx = TxIdx;
pTxBlk->Priv += pTxBlk->SrcBufLen;
INC_RING_INDEX(TxIdx, TX_RING_SIZE);
pTxRing->TxCpuIdx = TxIdx;
*FreeNumber -= 1;
return RetTxIdx;
}
/*
========================================================================
Routine Description:
In the case, Client may be silent left without sending DeAuth or DeAssoc.
AP'll continue retry packets for the client since AP doesn't know the STA
is gone. To Minimum affection of exist traffic is disable retransmition for
all those packet relative to the STA.
So decide to change ack required setting of all packet in TX ring
to "no ACK" requirement for specific Client.
Arguments:
Adapter Pointer to our adapter
Return Value:
None
IRQL = DISPATCH_LEVEL
========================================================================
*/
static VOID ClearTxRingClientAck(RTMP_ADAPTER *pAd, MAC_TABLE_ENTRY *pEntry)
{
UINT8 TXWISize;
if (!pAd || !pEntry)
return;
TXWISize = pAd->chipCap.TXWISize;
#ifdef RLT_MAC
if (pAd->chipCap.hif_type == HIF_RLT) {
DBGPRINT(RT_DEBUG_OFF, ("%s(): TBD for this function!\n", __FUNCTION__));
}
#endif /* RLT_MAC */
#ifdef RTMP_MAC
if (pAd->chipCap.hif_type == HIF_RTMP) {
INT index;
USHORT TxIdx;
RTMP_TX_RING *pTxRing;
TXD_STRUC *pTxD;
TXWI_STRUC *pTxWI;
#ifdef RT_BIG_ENDIAN
TXD_STRUC TxD, *pDestTxD;
TXWI_STRUC TxWI, *pDestTxWI;
#endif /* RT_BIG_ENDIAN */
for (index = 3; index >= 0; index--)
{
pTxRing = &pAd->TxRing[index];
for (TxIdx = 0; TxIdx < TX_RING_SIZE; TxIdx++)
{
#ifdef RT_BIG_ENDIAN
pDestTxD = (TXD_STRUC *) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (TXD_STRUC *) pTxRing->Cell[TxIdx].AllocVa;
#endif /* RT_BIG_ENDIAN */
if (!pTxD->DMADONE)
{
#ifdef RT_BIG_ENDIAN
pDestTxWI = (TXWI_STRUC *) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
NdisMoveMemory((PUCHAR)&TxWI, (PUCHAR)pDestTxWI, TXWISize);
pTxWI = &TxWI;
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
#else
pTxWI = (TXWI_STRUC *)pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
#endif /* RT_BIG_ENDIAN */
if (pTxWI->TXWI_O.wcid == pEntry->wcid)
pTxWI->TXWI_O.ACK = FALSE;
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
NdisMoveMemory((PUCHAR)pDestTxWI, (PUCHAR)pTxWI, TXWISize);
#endif /* RT_BIG_ENDIAN */
}
}
}
}
#endif /* RTMP_MAC */
}
PNDIS_PACKET GetPacketFromRxRing(
IN PRTMP_ADAPTER pAd,
OUT PRT28XX_RXD_STRUC pSaveRxD,
OUT BOOLEAN *pbReschedule,
IN OUT UINT32 *pRxPending)
{
PRXD_STRUC pRxD;
#ifdef RT_BIG_ENDIAN
PRXD_STRUC pDestRxD;
RXD_STRUC RxD;
#endif
PNDIS_PACKET pRxPacket = NULL;
PNDIS_PACKET pNewPacket;
PVOID AllocVa;
NDIS_PHYSICAL_ADDRESS AllocPa;
BOOLEAN bReschedule = FALSE;
RTMP_DMACB *pRxCell;
RTMP_SEM_LOCK(&pAd->RxRingLock);
if (*pRxPending == 0)
{
/* Get how may packets had been received*/
RTMP_IO_READ32(pAd, RX_DRX_IDX , &pAd->RxRing.RxDmaIdx);
if (pAd->RxRing.RxSwReadIdx == pAd->RxRing.RxDmaIdx)
{
/* no more rx packets*/
bReschedule = FALSE;
goto done;
}
/* get rx pending count*/
if (pAd->RxRing.RxDmaIdx > pAd->RxRing.RxSwReadIdx)
*pRxPending = pAd->RxRing.RxDmaIdx - pAd->RxRing.RxSwReadIdx;
else
*pRxPending = pAd->RxRing.RxDmaIdx + RX_RING_SIZE - pAd->RxRing.RxSwReadIdx;
#ifdef DESC_32B_SUPPORT
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx];
dma_cache_sync(NULL, pRxCell->AllocVa, RXD_SIZE, DMA_FROM_DEVICE);
#endif /* DESC_32B_SUPPORT */
}
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx];
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pRxCell->AllocPa, RXD_SIZE);
#ifdef RT_BIG_ENDIAN
pDestRxD = (PRXD_STRUC) pRxCell->AllocVa;
RxD = *pDestRxD;
pRxD = &RxD;
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
#else
/* Point to Rx indexed rx ring descriptor*/
pRxD = (PRXD_STRUC) pRxCell->AllocVa;
#endif
if (pRxD->DDONE == 0)
{
*pRxPending = 0;
/* DMAIndx had done but DDONE bit not ready*/
bReschedule = TRUE;
goto done;
}
#ifdef DESC_32B_SUPPORT
prefetch(&pAd->RxRing.Cell[(pAd->RxRing.RxSwReadIdx + 1) % RX_RING_SIZE].AllocVa);
#endif /* DESC_32B_SUPPORT */
/* return rx descriptor*/
NdisMoveMemory(pSaveRxD, pRxD, RXD_SIZE);
pNewPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev, RX_BUFFER_AGGRESIZE, FALSE, &AllocVa, &AllocPa);
if (pNewPacket)
{
/* unmap the rx buffer*/
PCI_UNMAP_SINGLE(pAd, pRxCell->DmaBuf.AllocPa,
pRxCell->DmaBuf.AllocSize, RTMP_PCI_DMA_FROMDEVICE);
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pRxCell->DmaBuf.AllocPa, pRxCell->DmaBuf.AllocSize);
pRxPacket = pRxCell->pNdisPacket;
pRxCell->DmaBuf.AllocSize = RX_BUFFER_AGGRESIZE;
pRxCell->pNdisPacket = (PNDIS_PACKET) pNewPacket;
pRxCell->DmaBuf.AllocVa = AllocVa;
pRxCell->DmaBuf.AllocPa = AllocPa;
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pRxCell->DmaBuf.AllocPa, pRxCell->DmaBuf.AllocSize);
/* update SDP0 to new buffer of rx packet */
pRxD->SDP0 = AllocPa;
#ifdef RX_DMA_SCATTER
pRxD->SDL0 = RX_BUFFER_AGGRESIZE;
#endif /* RX_DMA_SCATTER */
}
else
{
/*DBGPRINT(RT_DEBUG_TRACE,("No Rx Buffer\n"));*/
pRxPacket = NULL;
bReschedule = TRUE;
}
/* had handled one rx packet*/
*pRxPending = *pRxPending - 1;
#ifndef CACHE_LINE_32B
pRxD->DDONE = 0;
/* update rx descriptor and kick rx */
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxD, (PUCHAR)pRxD, FALSE, TYPE_RXD);
#endif
#ifdef DESC_32B_SUPPORT
dma_cache_sync(NULL, pRxCell->AllocVa, RXD_SIZE, DMA_TO_DEVICE);
#endif /* DESC_32B_SUPPORT */
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
#else /* CACHE_LINE_32B */
/*
Because our RXD_SIZE is 16B, but if the cache line size is 32B, we
will suffer a problem as below:
1. We flush RXD 0, start address of RXD 0 is 32B-align.
Nothing occurs.
2. We flush RXD 1, start address of RXD 1 is 16B-align.
Because cache line size is 32B, cache must flush 32B, cannot flush
16B only, so RXD0 and RXD1 will be flushed.
But when traffic is busy, maybe RXD0 is updated by MAC, i.e.
DDONE bit is 1, so when the cache flushs RXD0, the DDONE bit will
be cleared to 0.
3. Then when we handle RXD0 in the future, we will find the DDONE bit
is 0 and we will wait for MAC to set it to 1 forever.
*/
if (pAd->RxRing.RxSwReadIdx & 0x01)
{
RTMP_DMACB *pRxCellLast;
#ifdef RT_BIG_ENDIAN
PRXD_STRUC pDestRxDLast;
#endif
/* 16B-align */
/* update last BD 32B-align, DMA Done bit = 0 */
pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].LastBDInfo.DDONE = 0;
#ifdef RT_BIG_ENDIAN
pRxCellLast = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx - 1];
pDestRxDLast = (PRXD_STRUC) pRxCellLast->AllocVa;
RTMPDescriptorEndianChange((PUCHAR)&pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].LastBDInfo, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxDLast, (PUCHAR)&pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].LastBDInfo, FALSE, TYPE_RXD);
#endif
/* update current BD 16B-align, DMA Done bit = 0 */
pRxD->DDONE = 0;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxD, (PUCHAR)pRxD, FALSE, TYPE_RXD);
#endif
/* flush cache from last BD */
RTMP_DCACHE_FLUSH(pRxCellLast->AllocPa, 32); /* use RXD_SIZE should be OK */
/* update SW read and CPU index */
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
}
else
{
/* 32B-align */
/* do not set DDONE bit and backup it */
if (pAd->RxRing.RxSwReadIdx >= (RX_RING_SIZE-1))
{
DBGPRINT(RT_DEBUG_TRACE,
("Please change RX_RING_SIZE to mutiple of 2!\n"));
/* flush cache from current BD */
RTMP_DCACHE_FLUSH(pRxCell->AllocPa, RXD_SIZE);
/* update SW read and CPU index */
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
}
else
{
/* backup current BD */
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx + 1];
pRxCell->LastBDInfo = *pRxD;
/* update CPU index */
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
}
}
#endif /* CACHE_LINE_32B */
done:
RTMP_SEM_UNLOCK(&pAd->RxRingLock);
*pbReschedule = bReschedule;
return pRxPacket;
}
NDIS_STATUS MlmeHardTransmitTxRing(
IN PRTMP_ADAPTER pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket)
{
PACKET_INFO PacketInfo;
PUCHAR pSrcBufVA;
UINT SrcBufLen;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PHEADER_802_11 pHeader_802_11;
BOOLEAN bAckRequired, bInsertTimestamp;
ULONG SrcBufPA;
//UCHAR TxBufIdx;
UCHAR MlmeRate;
ULONG SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
PTXWI_STRUC pFirstTxWI;
//ULONG i;
//HTTRANSMIT_SETTING MlmeTransmit; //Rate for this MGMT frame.
ULONG FreeNum;
MAC_TABLE_ENTRY *pMacEntry = NULL;
RTMP_QueryPacketInfo(pPacket, &PacketInfo, &pSrcBufVA, &SrcBufLen);
if (pSrcBufVA == NULL)
{
// The buffer shouldn't be NULL
return NDIS_STATUS_FAILURE;
}
// Make sure MGMT ring resource won't be used by other threads
//NdisAcquireSpinLock(&pAd->TxRingLock);
FreeNum = GET_TXRING_FREENO(pAd, QueIdx);
if (FreeNum == 0)
{
//NdisReleaseSpinLock(&pAd->TxRingLock);
return NDIS_STATUS_FAILURE;
}
SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC)pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
if (pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket)
{
DBGPRINT(RT_DEBUG_OFF, ("MlmeHardTransmit Error\n"));
//NdisReleaseSpinLock(&pAd->TxRingLock);
return NDIS_STATUS_FAILURE;
}
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
// outgoing frame always wakeup PHY to prevent frame lost
// if (pAd->StaCfg.Psm == PWR_SAVE)
if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
AsicForceWakeup(pAd, TRUE);
}
#endif // CONFIG_STA_SUPPORT //
pFirstTxWI =(PTXWI_STRUC)pSrcBufVA;
pHeader_802_11 = (PHEADER_802_11) (pSrcBufVA + TXWI_SIZE);
if (pHeader_802_11->Addr1[0] & 0x01)
{
MlmeRate = pAd->CommonCfg.BasicMlmeRate;
}
else
{
MlmeRate = pAd->CommonCfg.MlmeRate;
}
if ((pHeader_802_11->FC.Type == BTYPE_DATA) &&
(pHeader_802_11->FC.SubType == SUBTYPE_QOS_NULL))
{
pMacEntry = MacTableLookup(pAd, pHeader_802_11->Addr1);
}
// Verify Mlme rate for a / g bands.
if ((pAd->LatchRfRegs.Channel > 14) && (MlmeRate < RATE_6)) // 11A band
MlmeRate = RATE_6;
//
// Should not be hard code to set PwrMgmt to 0 (PWR_ACTIVE)
// Snice it's been set to 0 while on MgtMacHeaderInit
// By the way this will cause frame to be send on PWR_SAVE failed.
//
//
// In WMM-UAPSD, mlme frame should be set psm as power saving but probe request frame
#ifdef CONFIG_STA_SUPPORT
// Data-Null packets alse pass through MMRequest in RT2860, however, we hope control the psm bit to pass APSD
if (pHeader_802_11->FC.Type != BTYPE_DATA)
{
if ((pHeader_802_11->FC.SubType == SUBTYPE_PROBE_REQ) || !(pAd->CommonCfg.bAPSDCapable && pAd->CommonCfg.APEdcaParm.bAPSDCapable))
{
pHeader_802_11->FC.PwrMgmt = PWR_ACTIVE;
}
else
{
pHeader_802_11->FC.PwrMgmt = pAd->CommonCfg.bAPSDForcePowerSave;
}
}
#endif // CONFIG_STA_SUPPORT //
bInsertTimestamp = FALSE;
if (pHeader_802_11->FC.Type == BTYPE_CNTL) // must be PS-POLL
{
bAckRequired = FALSE;
}
else // BTYPE_MGMT or BTYPE_DATA(must be NULL frame)
{
if (pHeader_802_11->Addr1[0] & 0x01) // MULTICAST, BROADCAST
{
bAckRequired = FALSE;
pHeader_802_11->Duration = 0;
}
else
{
bAckRequired = TRUE;
pHeader_802_11->Duration = RTMPCalcDuration(pAd, MlmeRate, 14);
if (pHeader_802_11->FC.SubType == SUBTYPE_PROBE_RSP)
{
bInsertTimestamp = TRUE;
}
}
}
pHeader_802_11->Sequence = pAd->Sequence++;
if (pAd->Sequence > 0xfff)
pAd->Sequence = 0;
// Before radar detection done, mgmt frame can not be sent but probe req
// Because we need to use probe req to trigger driver to send probe req in passive scan
if ((pHeader_802_11->FC.SubType != SUBTYPE_PROBE_REQ)
&& (pAd->CommonCfg.bIEEE80211H == 1)
&& (pAd->CommonCfg.RadarDetect.RDMode != RD_NORMAL_MODE))
{
DBGPRINT(RT_DEBUG_ERROR,("MlmeHardTransmit --> radar detect not in normal mode !!!\n"));
//NdisReleaseSpinLock(&pAd->TxRingLock);
return (NDIS_STATUS_FAILURE);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader_802_11, DIR_WRITE, FALSE);
#endif
//
// fill scatter-and-gather buffer list into TXD. Internally created NDIS PACKET
// should always has only one ohysical buffer, and the whole frame size equals
// to the first scatter buffer size
//
// Initialize TX Descriptor
// For inter-frame gap, the number is for this frame and next frame
// For MLME rate, we will fix as 2Mb to match other vendor's implement
// pAd->CommonCfg.MlmeTransmit.field.MODE = 1;
// management frame doesn't need encryption. so use RESERVED_WCID no matter u are sending to specific wcid or not.
// Only beacon use Nseq=TRUE. So here we use Nseq=FALSE.
if (pMacEntry == NULL)
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE, bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, RESERVED_WCID, (SrcBufLen - TXWI_SIZE), PID_MGMT, 0, (UCHAR)pAd->CommonCfg.MlmeTransmit.field.MCS, IFS_BACKOFF, FALSE, &pAd->CommonCfg.MlmeTransmit);
}
else
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE,
bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, pMacEntry->Aid, (SrcBufLen - TXWI_SIZE),
pMacEntry->MaxHTPhyMode.field.MCS, 0,
(UCHAR)pMacEntry->MaxHTPhyMode.field.MCS,
IFS_BACKOFF, FALSE, &pMacEntry->MaxHTPhyMode);
}
pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket = pPacket;
pAd->TxRing[QueIdx].Cell[SwIdx].pNextNdisPacket = NULL;
// pFirstTxWI->MPDUtotalByteCount = SrcBufLen - TXWI_SIZE;
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)pFirstTxWI, TYPE_TXWI);
#endif
SrcBufPA = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_EDCA);
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 1;
pTxD->SDLen0 = SrcBufLen;
pTxD->SDLen1 = 0;
pTxD->SDPtr0 = SrcBufPA;
pTxD->DMADONE = 0;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
// Increase TX_CTX_IDX, but write to register later.
INC_RING_INDEX(pAd->TxRing[QueIdx].TxCpuIdx, TX_RING_SIZE);
RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QueIdx*0x10, pAd->TxRing[QueIdx].TxCpuIdx);
// Make sure to release MGMT ring resource
// NdisReleaseSpinLock(&pAd->TxRingLock);
return NDIS_STATUS_SUCCESS;
}
NDIS_STATUS MlmeHardTransmitTxRing(
IN PRTMP_ADAPTER pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket)
{
PACKET_INFO PacketInfo;
PUCHAR pSrcBufVA;
UINT SrcBufLen;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PHEADER_802_11 pHeader_802_11;
BOOLEAN bAckRequired, bInsertTimestamp;
ULONG SrcBufPA;
/*UCHAR TxBufIdx;*/
UCHAR MlmeRate;
ULONG SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
PTXWI_STRUC pFirstTxWI;
/*ULONG i;*/
/*HTTRANSMIT_SETTING MlmeTransmit; Rate for this MGMT frame.*/
ULONG FreeNum;
MAC_TABLE_ENTRY *pMacEntry = NULL;
UINT8 TXWISize = pAd->chipCap.TXWISize;
#ifdef CONFIG_AP_SUPPORT
#ifdef SPECIFIC_TX_POWER_SUPPORT
UCHAR TxPwrAdj = 0;
#endif /* SPECIFIC_TX_POWER_SUPPORT */
#endif /* CONFIG_AP_SUPPORT */
RTMP_QueryPacketInfo(pPacket, &PacketInfo, &pSrcBufVA, &SrcBufLen);
if (pSrcBufVA == NULL)
{
/* The buffer shouldn't be NULL*/
return NDIS_STATUS_FAILURE;
}
/* Make sure MGMT ring resource won't be used by other threads*/
/*NdisAcquireSpinLock(&pAd->TxRingLock);*/
FreeNum = GET_TXRING_FREENO(pAd, QueIdx);
if (FreeNum == 0)
{
/*NdisReleaseSpinLock(&pAd->TxRingLock);*/
return NDIS_STATUS_FAILURE;
}
SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC)pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
#endif
if (pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket)
{
DBGPRINT(RT_DEBUG_OFF, ("MlmeHardTransmit Error\n"));
/*NdisReleaseSpinLock(&pAd->TxRingLock);*/
return NDIS_STATUS_FAILURE;
}
pFirstTxWI =(PTXWI_STRUC)(pSrcBufVA + TXINFO_SIZE);
pHeader_802_11 = (PHEADER_802_11)(pSrcBufVA + TXINFO_SIZE + TXWISize);
if (pHeader_802_11->Addr1[0] & 0x01)
{
MlmeRate = pAd->CommonCfg.BasicMlmeRate;
}
else
{
MlmeRate = pAd->CommonCfg.MlmeRate;
}
if ((pHeader_802_11->FC.Type == BTYPE_DATA) &&
(pHeader_802_11->FC.SubType == SUBTYPE_QOS_NULL))
{
pMacEntry = MacTableLookup(pAd, pHeader_802_11->Addr1);
}
/* Verify Mlme rate for a / g bands.*/
if ((pAd->LatchRfRegs.Channel > 14) && (MlmeRate < RATE_6)) /* 11A band*/
MlmeRate = RATE_6;
/*
Should not be hard code to set PwrMgmt to 0 (PWR_ACTIVE)
Snice it's been set to 0 while on MgtMacHeaderInit
By the way this will cause frame to be send on PWR_SAVE failed.
*/
/* In WMM-UAPSD, mlme frame should be set psm as power saving but probe request frame*/
bInsertTimestamp = FALSE;
if (pHeader_802_11->FC.Type == BTYPE_CNTL) /* must be PS-POLL*/
{
bAckRequired = FALSE;
}
else /* BTYPE_MGMT or BTYPE_DATA(must be NULL frame)*/
{
if (pHeader_802_11->Addr1[0] & 0x01) /* MULTICAST, BROADCAST*/
{
bAckRequired = FALSE;
pHeader_802_11->Duration = 0;
}
else
{
bAckRequired = TRUE;
pHeader_802_11->Duration = RTMPCalcDuration(pAd, MlmeRate, 14);
if (pHeader_802_11->FC.SubType == SUBTYPE_PROBE_RSP)
{
bInsertTimestamp = TRUE;
#ifdef CONFIG_AP_SUPPORT
#ifdef SPECIFIC_TX_POWER_SUPPORT
/* Find which MBSSID to be send this probeRsp */
UINT32 apidx;
for (apidx=0; apidx<pAd->ApCfg.BssidNum; apidx++)
{
if (RTMPEqualMemory(pHeader_802_11->Addr2, pAd->ApCfg.MBSSID[apidx].Bssid, MAC_ADDR_LEN))
break;
}
if (!(apidx >= pAd->ApCfg.BssidNum) &&
(pAd->ApCfg.MBSSID[apidx].TxPwrAdj != -1) &&
(pAd->CommonCfg.MlmeTransmit.field.MODE == MODE_CCK) &&
(pAd->CommonCfg.MlmeTransmit.field.MCS == RATE_1))
{
TxPwrAdj = pAd->ApCfg.MBSSID[apidx].TxPwrAdj;
}
#endif /* SPECIFIC_TX_POWER_SUPPORT */
#endif /* CONFIG_AP_SUPPORT */
}
}
}
pHeader_802_11->Sequence = pAd->Sequence++;
if (pAd->Sequence > 0xfff)
pAd->Sequence = 0;
/* Before radar detection done, mgmt frame can not be sent but probe req*/
/* Because we need to use probe req to trigger driver to send probe req in passive scan*/
if ((pHeader_802_11->FC.SubType != SUBTYPE_PROBE_REQ)
&& (pAd->CommonCfg.bIEEE80211H == 1)
&& (pAd->Dot11_H.RDMode != RD_NORMAL_MODE))
{
DBGPRINT(RT_DEBUG_ERROR,("MlmeHardTransmit --> radar detect not in normal mode !!!\n"));
/*NdisReleaseSpinLock(&pAd->TxRingLock);*/
return (NDIS_STATUS_FAILURE);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader_802_11, DIR_WRITE, FALSE);
#endif
/*
Fill scatter-and-gather buffer list into TXD. Internally created NDIS PACKET
should always has only one ohysical buffer, and the whole frame size equals
to the first scatter buffer size
*/
/*
Initialize TX Descriptor
For inter-frame gap, the number is for this frame and next frame
For MLME rate, we will fix as 2Mb to match other vendor's implement
*/
/* pAd->CommonCfg.MlmeTransmit.field.MODE = 1;*/
/* management frame doesn't need encryption. so use RESERVED_WCID no matter u are sending to specific wcid or not.*/
/* Only beacon use Nseq=TRUE. So here we use Nseq=FALSE.*/
if (pMacEntry == NULL)
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE, bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, RESERVED_WCID, (SrcBufLen - TXINFO_SIZE - TXWISize), PID_MGMT, 0, (UCHAR)pAd->CommonCfg.MlmeTransmit.field.MCS, IFS_BACKOFF, FALSE, &pAd->CommonCfg.MlmeTransmit);
#ifdef SPECIFIC_TX_POWER_SUPPORT
if (IS_RT6352(pAd))
pFirstTxWI->TxPwrAdj = TxPwrAdj;
#endif /* SPECIFIC_TX_POWER_SUPPORT */
}
else
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE,
bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, pMacEntry->Aid, (SrcBufLen - TXINFO_SIZE - TXWISize),
pMacEntry->MaxHTPhyMode.field.MCS, 0,
(UCHAR)pMacEntry->MaxHTPhyMode.field.MCS,
IFS_BACKOFF, FALSE, &pMacEntry->MaxHTPhyMode);
}
pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket = pPacket;
pAd->TxRing[QueIdx].Cell[SwIdx].pNextNdisPacket = NULL;
/* pFirstTxWI->MPDUtotalByteCount = SrcBufLen - TXWI_SIZE;*/
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)pFirstTxWI, TYPE_TXWI);
#endif
SrcBufPA = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, RTMP_PCI_DMA_TODEVICE);
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 0;
pTxD->SDLen1 = 0;
pTxD->SDPtr0 = SrcBufPA;
pTxD->SDLen0 = SrcBufLen;
RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(SrcBufPA, SrcBufLen);
RTMP_DCACHE_FLUSH(pAd->TxRing[QueIdx].Cell[SwIdx].AllocPa, RXD_SIZE);
/* Increase TX_CTX_IDX, but write to register later.*/
INC_RING_INDEX(pAd->TxRing[QueIdx].TxCpuIdx, TX_RING_SIZE);
RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QueIdx*0x10, pAd->TxRing[QueIdx].TxCpuIdx);
/* Make sure to release MGMT ring resource*/
/* NdisReleaseSpinLock(&pAd->TxRingLock);*/
return NDIS_STATUS_SUCCESS;
}
USHORT RtmpPCI_WriteSingleTxResource(
IN PRTMP_ADAPTER pAd,
IN TX_BLK *pTxBlk,
IN BOOLEAN bIsLast,
OUT USHORT *FreeNumber)
{
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHeaderLen;
//
// get Tx Ring Resource
//
pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
BufBasePaLow = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
// copy TXINFO + TXWI + WLAN Header + LLC into DMA Header Buffer
//hwHeaderLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4);
hwHeaderLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf, TXINFO_SIZE + TXWI_SIZE + hwHeaderLen);
pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
//
// build Tx Descriptor
//
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
NdisZeroMemory(pTxD, TXD_SIZE);
pTxD->SDPtr0 = BufBasePaLow;
pTxD->SDLen0 = TXINFO_SIZE + TXWI_SIZE + hwHeaderLen; // include padding
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, PCI_DMA_TODEVICE);;
pTxD->SDLen1 = pTxBlk->SrcBufLen;
pTxD->LastSec0 = 0;
pTxD->LastSec1 = (bIsLast) ? 1 : 0;
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE), TYPE_TXWI);
RTMPFrameEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE + TXWI_SIZE), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif // RT_BIG_ENDIAN //
RetTxIdx = TxIdx;
//
// Update Tx index
//
INC_RING_INDEX(TxIdx, TX_RING_SIZE);
pTxRing->TxCpuIdx = TxIdx;
*FreeNumber -= 1;
return RetTxIdx;
}
USHORT RtmpPCI_WriteMultiTxResource(
IN PRTMP_ADAPTER pAd,
IN TX_BLK *pTxBlk,
IN UCHAR frameNum,
OUT USHORT *FreeNumber)
{
BOOLEAN bIsLast;
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHdrLen;
UINT32 firstDMALen;
UINT8 TXWISize = pAd->chipCap.TXWISize;
bIsLast = ((frameNum == (pTxBlk->TotalFrameNum - 1)) ? 1 : 0);
/* get Tx Ring Resource*/
pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
BufBasePaLow = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
if (frameNum == 0)
{
/* copy TXINFO + TXWI + WLAN Header + LLC into DMA Header Buffer*/
if (pTxBlk->TxFrameType == TX_AMSDU_FRAME)
/*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen-LENGTH_AMSDU_SUBFRAMEHEAD, 4)+LENGTH_AMSDU_SUBFRAMEHEAD;*/
hwHdrLen = pTxBlk->MpduHeaderLen - LENGTH_AMSDU_SUBFRAMEHEAD + pTxBlk->HdrPadLen + LENGTH_AMSDU_SUBFRAMEHEAD;
else if (pTxBlk->TxFrameType == TX_RALINK_FRAME)
/*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen-LENGTH_ARALINK_HEADER_FIELD, 4)+LENGTH_ARALINK_HEADER_FIELD;*/
hwHdrLen = pTxBlk->MpduHeaderLen - LENGTH_ARALINK_HEADER_FIELD + pTxBlk->HdrPadLen + LENGTH_ARALINK_HEADER_FIELD;
else
/*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4);*/
hwHdrLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
firstDMALen = TXINFO_SIZE + TXWISize + hwHdrLen;
}
else
{
firstDMALen = pTxBlk->MpduHeaderLen;
}
NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf, firstDMALen);
pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
/* build Tx Descriptor*/
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
NdisZeroMemory(pTxD, TXD_SIZE);
pTxD->SDPtr0 = BufBasePaLow;
pTxD->SDLen0 = firstDMALen; /* include padding*/
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, RTMP_PCI_DMA_TODEVICE);;
pTxD->SDLen1 = pTxBlk->SrcBufLen;
pTxD->LastSec0 = !(pTxD->SDLen1);
pTxD->LastSec1 = (bIsLast && pTxD->SDLen1) ? 1 : 0;
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
if (frameNum == 0)
RTMPFrameEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA+ TXINFO_SIZE + TXWISize), DIR_WRITE, FALSE);
if (frameNum != 0)
RTMPWIEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE), TYPE_TXWI);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif /* RT_BIG_ENDIAN */
RetTxIdx = TxIdx;
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pTxRing->Cell[TxIdx].DmaBuf.AllocPa, pTxD->SDLen0);
RTMP_DCACHE_FLUSH(pTxBlk->pSrcBufData, pTxBlk->SrcBufLen);
RTMP_DCACHE_FLUSH(pTxRing->Cell[TxIdx].AllocPa, RXD_SIZE);
/* Update Tx index*/
INC_RING_INDEX(TxIdx, TX_RING_SIZE);
pTxRing->TxCpuIdx = TxIdx;
*FreeNumber -= 1;
return RetTxIdx;
}
/*
========================================================================
Routine Description:
Process MGMT ring DMA done interrupt, running in DPC level
Arguments:
pAd Pointer to our adapter
Return Value:
None
IRQL = DISPATCH_LEVEL
Note:
========================================================================
*/
VOID RTMPHandleMgmtRingDmaDoneInterrupt(
IN PRTMP_ADAPTER pAd)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PNDIS_PACKET pPacket;
// int i;
UCHAR FREE = 0;
PRTMP_MGMT_RING pMgmtRing = &pAd->MgmtRing;
NdisAcquireSpinLock(&pAd->MgmtRingLock);
RTMP_IO_READ32(pAd, TX_MGMTDTX_IDX, &pMgmtRing->TxDmaIdx);
while (pMgmtRing->TxSwFreeIdx!= pMgmtRing->TxDmaIdx)
{
FREE++;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
#endif
pTxD->DMADONE = 0;
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket;
if (pPacket == NULL)
continue;
#ifdef CONFIG_AP_SUPPORT
#define LMR_FRAME_GET() (GET_OS_PKT_DATAPTR(pPacket)+TXWI_SIZE)
#ifdef UAPSD_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
UAPSD_QoSNullTxMgmtTxDoneHandle(pAd,
pPacket,
LMR_FRAME_GET());
}
#endif // UAPSD_AP_SUPPORT //
#ifdef WMM_ACM_SUPPORT
{
HEADER_802_11 *pHeader;
/* handle Power Save ADDTS Response */
pHeader = (HEADER_802_11 *)(LMR_FRAME_GET());
if ((pHeader->FC.Type == BTYPE_MGMT) &&
(pHeader->FC.SubType == SUBTYPE_ACTION))
{
ACMP_PsRspDeltsSentOutHandle(pAd,
MacTableLookup(pAd, pHeader->Addr1),
((UCHAR *)pHeader)+sizeof(HEADER_802_11));
}
}
#endif // WMM_ACM_SUPPORT //
#endif // CONFIG_AP_SUPPORT //
if (pPacket)
{
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket = NULL;
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket;
if (pPacket)
{
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket = NULL;
INC_RING_INDEX(pMgmtRing->TxSwFreeIdx, MGMT_RING_SIZE);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, TRUE, TYPE_TXD);
#endif
}
NdisReleaseSpinLock(&pAd->MgmtRingLock);
#ifdef CONFIG_STA_SUPPORT
#ifdef WMM_ACM_SUPPORT
/* return power save right if possible, ex:
0. sta enter PS mode;
1. sta enters ACTIVE mode;
2. sta sends ADDTS request frame;
3. sta receives ADDTS response frame;
4. sta enter PS mode; (ACMP_StaPsCtrlRightReturn) */
if (ACMR_IS_ENABLED(pAd))
ACMP_StaPsCtrlRightReturn(pAd);
/* End of if */
#endif // WMM_ACM_SUPPORT //
#endif // CONFIG_STA_SUPPORT //
}
USHORT RtmpPCI_WriteFragTxResource(
IN PRTMP_ADAPTER pAd,
IN TX_BLK *pTxBlk,
IN UCHAR fragNum,
OUT USHORT *FreeNumber)
{
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHeaderLen;
UINT32 firstDMALen;
UINT8 TXWISize = pAd->chipCap.TXWISize;
/* Get Tx Ring Resource*/
pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
BufBasePaLow = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
/* Copy TXINFO + TXWI + WLAN Header + LLC into DMA Header Buffer*/
/*hwHeaderLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4);*/
hwHeaderLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
firstDMALen = TXINFO_SIZE + TXWISize + hwHeaderLen;
NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf, firstDMALen);
/* Build Tx Descriptor*/
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
NdisZeroMemory(pTxD, TXD_SIZE);
if (fragNum == pTxBlk->TotalFragNum)
{
pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
}
pTxD->SDPtr0 = BufBasePaLow;
pTxD->SDLen0 = firstDMALen; /* include padding*/
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, RTMP_PCI_DMA_TODEVICE);
pTxD->SDLen1 = pTxBlk->SrcBufLen;
if (pTxD->SDLen1 > 0)
{
pTxD->LastSec0 = 0;
pTxD->LastSec1 = 1;
}
else
{
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 0;
}
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE), TYPE_TXWI);
RTMPFrameEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE + TXWISize), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif /* RT_BIG_ENDIAN */
RetTxIdx = TxIdx;
pTxBlk->Priv += pTxBlk->SrcBufLen;
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pTxRing->Cell[TxIdx].DmaBuf.AllocPa, pTxD->SDLen0);
RTMP_DCACHE_FLUSH(pTxBlk->pSrcBufData, pTxBlk->SrcBufLen);
RTMP_DCACHE_FLUSH(pTxRing->Cell[TxIdx].AllocPa, RXD_SIZE);
/* Update Tx index*/
INC_RING_INDEX(TxIdx, TX_RING_SIZE);
pTxRing->TxCpuIdx = TxIdx;
*FreeNumber -= 1;
return RetTxIdx;
}
VOID RTUSBBulkOutDataPacket(
IN PRTMP_ADAPTER pAd,
IN UCHAR BulkOutPipeId,
IN UCHAR Index)
{
PHT_TX_CONTEXT pHTTXContext;
PURB pUrb;
int ret = 0;
PTXINFO_STRUC pTxInfo, pLastTxInfo = NULL;
PTXWI_STRUC pTxWI;
ULONG TmpBulkEndPos, ThisBulkSize;
unsigned long IrqFlags = 0, IrqFlags2 = 0;
PUCHAR pWirelessPkt, pAppendant;
#ifdef USB_BULK_BUF_ALIGMENT
BOOLEAN bLasAlignmentsectiontRound = FALSE;
#else
BOOLEAN bTxQLastRound = FALSE;
UCHAR allzero[4]= {0x0,0x0,0x0,0x0};
#endif /* USB_BULK_BUF_ALIGMENT */
BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
if ((pAd->BulkOutPending[BulkOutPipeId] == TRUE) || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_TX))
{
BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
return;
}
pAd->BulkOutPending[BulkOutPipeId] = TRUE;
if (((!OPSTATUS_TEST_FLAG(pAd, fOP_AP_STATUS_MEDIA_STATE_CONNECTED)) &&
( !OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)))
)
{
pAd->BulkOutPending[BulkOutPipeId] = FALSE;
BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
return;
}
BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
pHTTXContext = &(pAd->TxContext[BulkOutPipeId]);
BULK_OUT_LOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags2);
#ifdef USB_BULK_BUF_ALIGMENT
if ( (pHTTXContext->NextBulkIdx != pHTTXContext->CurtBulkIdx)
|| ((pHTTXContext->CurWriteRealPos > pHTTXContext->CurWritePosition) &&(pHTTXContext->NextBulkIdx == pHTTXContext->CurWriteIdx))
|| ((pHTTXContext->CurWriteRealPos == 0) && (pHTTXContext->NextBulkIdx == pHTTXContext->CurWriteIdx))
)
#else
if ((pHTTXContext->ENextBulkOutPosition == pHTTXContext->CurWritePosition)
|| ((pHTTXContext->ENextBulkOutPosition-8) == pHTTXContext->CurWritePosition))
#endif /* USB_BULK_BUF_ALIGMENT */
/* druing writing. */
{
BULK_OUT_UNLOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags2);
BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
pAd->BulkOutPending[BulkOutPipeId] = FALSE;
/* Clear Data flag*/
RTUSB_CLEAR_BULK_FLAG(pAd, (fRTUSB_BULK_OUT_DATA_FRAG << BulkOutPipeId));
RTUSB_CLEAR_BULK_FLAG(pAd, (fRTUSB_BULK_OUT_DATA_NORMAL << BulkOutPipeId));
BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
return;
}
/* Clear Data flag*/
RTUSB_CLEAR_BULK_FLAG(pAd, (fRTUSB_BULK_OUT_DATA_FRAG << BulkOutPipeId));
RTUSB_CLEAR_BULK_FLAG(pAd, (fRTUSB_BULK_OUT_DATA_NORMAL << BulkOutPipeId));
/*DBGPRINT(RT_DEBUG_TRACE,("BulkOut-B:I=0x%lx, CWPos=%ld, CWRPos=%ld, NBPos=%ld, ENBPos=%ld, bCopy=%d!\n", in_interrupt(), */
/* pHTTXContext->CurWritePosition, pHTTXContext->CurWriteRealPos, pHTTXContext->NextBulkOutPosition, */
/* pHTTXContext->ENextBulkOutPosition, pHTTXContext->bCopySavePad));*/
pHTTXContext->NextBulkOutPosition = pHTTXContext->ENextBulkOutPosition;
ThisBulkSize = 0;
TmpBulkEndPos = pHTTXContext->NextBulkOutPosition;
#ifdef USB_BULK_BUF_ALIGMENT
INT idx;
idx = pHTTXContext->NextBulkIdx;
pWirelessPkt = &pHTTXContext->TransferBuffer[idx]->field.WirelessPacket[0];
#else
pWirelessPkt = &pHTTXContext->TransferBuffer->field.WirelessPacket[0];
#endif /* USB_BULK_BUF_ALIGMENT */
#ifndef USB_BULK_BUF_ALIGMENT
if ((pHTTXContext->bCopySavePad == TRUE))
{
if (RTMPEqualMemory(pHTTXContext->SavedPad, allzero,4))
{
DBGPRINT_RAW(RT_DEBUG_ERROR,("e1, allzero : %x %x %x %x %x %x %x %x \n",
pHTTXContext->SavedPad[0], pHTTXContext->SavedPad[1], pHTTXContext->SavedPad[2],pHTTXContext->SavedPad[3]
,pHTTXContext->SavedPad[4], pHTTXContext->SavedPad[5], pHTTXContext->SavedPad[6],pHTTXContext->SavedPad[7]));
}
NdisMoveMemory(&pWirelessPkt[TmpBulkEndPos], pHTTXContext->SavedPad, 8);
pHTTXContext->bCopySavePad = FALSE;
if (pAd->bForcePrintTX == TRUE)
DBGPRINT(RT_DEBUG_TRACE,("RTUSBBulkOutDataPacket --> COPY PAD. CurWrite = %ld, NextBulk = %ld. ENextBulk = %ld.\n", pHTTXContext->CurWritePosition, pHTTXContext->NextBulkOutPosition, pHTTXContext->ENextBulkOutPosition));
}
#endif /* USB_BULK_BUF_ALIGMENT */
do
{
pTxInfo = (PTXINFO_STRUC)&pWirelessPkt[TmpBulkEndPos];
pTxWI = (PTXWI_STRUC)&pWirelessPkt[TmpBulkEndPos + TXINFO_SIZE];
if (pAd->bForcePrintTX == TRUE)
DBGPRINT(RT_DEBUG_TRACE, ("RTUSBBulkOutDataPacket AMPDU = %d.\n", pTxWI->AMPDU));
/* add by Iverson, limit BulkOut size to 4k to pass WMM b mode 2T1R test items*/
/*if ((ThisBulkSize != 0) && (pTxWI->AMPDU == 0))*/
if ((ThisBulkSize != 0) && (pTxWI->PHYMODE == MODE_CCK))
{
#ifdef INF_AMAZON_SE
/*Iverson Add for AMAZON USB (RT2070 && RT3070) to pass WMM A2-T4 ~ A2-T10*/
if(OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WMM_INUSED))
{
/*Iverson patch for WMM A5-T07 ,WirelessStaToWirelessSta do not bulk out aggregate*/
if(pTxWI->PacketId == 6)
{
pHTTXContext->ENextBulkOutPosition = TmpBulkEndPos;
break;
}
else if (((ThisBulkSize&0xffff8000) != 0) || ((ThisBulkSize&pAd->BulkOutDataSizeLimit[BulkOutPipeId]) == pAd->BulkOutDataSizeLimit[BulkOutPipeId]))
{
/*printk("===Bulkout size limit :%d ===\n",MaxBulkOutSize);*/
/*DBGPRINT(RT_DEBUG_TRACE,("b mode BulkOutPipeId %d pAd->BulkOutDataSizeLimit[BulkOutPipeId] %d \n",BulkOutPipeId,pAd->BulkOutDataSizeLimit[BulkOutPipeId]));*/
pHTTXContext->ENextBulkOutPosition = TmpBulkEndPos;
break;
}
}
else if (((ThisBulkSize&0xffff8000) != 0) || ((ThisBulkSize&0x1000) == 0x1000))
{
/* Limit BulkOut size to about 4k bytes.*/
pHTTXContext->ENextBulkOutPosition = TmpBulkEndPos;
break;
}
#endif /* INF_AMAZON_SE */
#ifndef INF_AMAZON_SE
#ifndef USB_BULK_BUF_ALIGMENT
if (((ThisBulkSize&0xffff8000) != 0) || ((ThisBulkSize&0x1000) == 0x1000))
{
/* Limit BulkOut size to about 4k bytes.*/
pHTTXContext->ENextBulkOutPosition = TmpBulkEndPos;
break;
}
#else
if (((ThisBulkSize&0xffff8000) != 0) || ((ThisBulkSize&BULKOUT_SIZE) == BULKOUT_SIZE))
{
/* Limit BulkOut size to about 24k bytes.*/
pHTTXContext->ENextBulkOutPosition = TmpBulkEndPos;
/*
when bulk size is > 6000, it mean that this is the lasttround at this alignmnet section.
*/
bLasAlignmentsectiontRound = TRUE;
break;
}
#endif /* USB_BULK_BUF_ALIGMENT */
#endif /* INF_AMAZON_SE */
#ifndef USB_BULK_BUF_ALIGMENT
else if (((pAd->BulkOutMaxPacketSize < 512) && ((ThisBulkSize&0xfffff800) != 0) ) /*|| ( (ThisBulkSize != 0) && (pTxWI->AMPDU == 0))*/)
{
/* For USB 1.1 or peer which didn't support AMPDU, limit the BulkOut size. */
/* For performence in b/g mode, now just check for USB 1.1 and didn't care about the APMDU or not! 2008/06/04.*/
pHTTXContext->ENextBulkOutPosition = TmpBulkEndPos;
break;
}
#else
else if (((pAd->BulkOutMaxPacketSize < 512) && (((ThisBulkSize&0xffff8000) != 0) || ((ThisBulkSize&BULKOUT_SIZE) == BULKOUT_SIZE)) ))
{
/* Limit BulkOut size to about 24k bytes.*/
pHTTXContext->ENextBulkOutPosition = TmpBulkEndPos;
/*
when bulk size is > 6000, it mean that this is the lasttround at this alignmnet section.
*/
bLasAlignmentsectiontRound = TRUE;
break;
}
#endif /* USB_BULK_BUF_ALIGMENT */
}
/* end Iverson*/
else
{
#ifdef USB_BULK_BUF_ALIGMENT
if (((ThisBulkSize&0xffff8000) != 0) || ((ThisBulkSize&BULKOUT_SIZE) == BULKOUT_SIZE))
#else
if (((ThisBulkSize&0xffff8000) != 0) || ((ThisBulkSize&0x6000) == 0x6000))
#endif /* USB_BULK_BUF_ALIGMENT */
{ /* Limit BulkOut size to about 24k bytes.*/
pHTTXContext->ENextBulkOutPosition = TmpBulkEndPos;
#ifdef USB_BULK_BUF_ALIGMENT
/*
when bulk size is > 0x6000, it mean that this is the lasttround at this alignmnet section.
*/
bLasAlignmentsectiontRound = TRUE;
/* printk("data bulk out bLasAlignmentsectiontRound \n");*/
#endif /* USB_BULK_BUF_ALIGMENT */
break;
}
#ifdef INF_AMAZON_SE
else if (((ThisBulkSize&0xffff8000) != 0) || ((ThisBulkSize&pAd->BulkOutDataSizeLimit[BulkOutPipeId]) == pAd->BulkOutDataSizeLimit[BulkOutPipeId]))
{
/*printk("===Bulkout size limit :%d ===\n",ThisBulkSize);*/
pHTTXContext->ENextBulkOutPosition = TmpBulkEndPos;
break;
}
#endif /* INF_AMAZON_SE */
#ifndef USB_BULK_BUF_ALIGMENT
else if (((pAd->BulkOutMaxPacketSize < 512) && ((ThisBulkSize&0xfffff800) != 0) ) /*|| ( (ThisBulkSize != 0) && (pTxWI->AMPDU == 0))*/)
{ /* For USB 1.1 or peer which didn't support AMPDU, limit the BulkOut size. */
/* For performence in b/g mode, now just check for USB 1.1 and didn't care about the APMDU or not! 2008/06/04.*/
pHTTXContext->ENextBulkOutPosition = TmpBulkEndPos;
break;
}
#else
else if (((pAd->BulkOutMaxPacketSize < 512) && (((ThisBulkSize&0xffff8000) != 0) || ((ThisBulkSize&BULKOUT_SIZE) == BULKOUT_SIZE)) ))
{
/* Limit BulkOut size to about 24k bytes.*/
pHTTXContext->ENextBulkOutPosition = TmpBulkEndPos;
/*
when bulk size is > 6000, it mean that this is the lasttround at this alignmnet section.
*/
bLasAlignmentsectiontRound = TRUE;
break;
}
#endif /* USB_BULK_BUF_ALIGMENT */
}
#ifdef USB_BULK_BUF_ALIGMENT
if ((TmpBulkEndPos == pHTTXContext->CurWritePosition) && (pHTTXContext->NextBulkIdx == pHTTXContext->CurWriteIdx))
#else
if (TmpBulkEndPos == pHTTXContext->CurWritePosition)
#endif /* USB_BULK_BUF_ALIGMENT */
{
pHTTXContext->ENextBulkOutPosition = TmpBulkEndPos;
break;
}
#if !defined(CONFIG_MULTI_CHANNEL) && !defined(DOT11Z_TDLS_SUPPORT)
if (pTxInfo->QSEL != FIFO_EDCA)
{
DBGPRINT(RT_DEBUG_ERROR, ("%s(): ====> pTxInfo->QueueSel(%d)!= FIFO_EDCA!!!!\n",
__FUNCTION__, pTxInfo->QSEL));
DBGPRINT(RT_DEBUG_ERROR, ("\tCWPos=%ld, NBPos=%ld, ENBPos=%ld, bCopy=%d!\n",
pHTTXContext->CurWritePosition, pHTTXContext->NextBulkOutPosition,
pHTTXContext->ENextBulkOutPosition, pHTTXContext->bCopySavePad));
hex_dump("Wrong QSel Pkt:", (PUCHAR)&pWirelessPkt[TmpBulkEndPos], (pHTTXContext->CurWritePosition - pHTTXContext->NextBulkOutPosition));
}
#endif /* !defined(CONFIG_MULTI_CHANNEL) && !defined(DOT11Z_TDLS_SUPPORT) */
if (pTxInfo->USBDMATxPktLen <= 8)
{
BULK_OUT_UNLOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags2);
DBGPRINT(RT_DEBUG_ERROR /*RT_DEBUG_TRACE*/,("e2, USBDMATxPktLen==0, Size=%ld, bCSPad=%d, CWPos=%ld, NBPos=%ld, CWRPos=%ld!\n",
pHTTXContext->BulkOutSize, pHTTXContext->bCopySavePad, pHTTXContext->CurWritePosition, pHTTXContext->NextBulkOutPosition, pHTTXContext->CurWriteRealPos));
{
DBGPRINT_RAW(RT_DEBUG_ERROR /*RT_DEBUG_TRACE*/,("%x %x %x %x %x %x %x %x \n",
pHTTXContext->SavedPad[0], pHTTXContext->SavedPad[1], pHTTXContext->SavedPad[2],pHTTXContext->SavedPad[3]
,pHTTXContext->SavedPad[4], pHTTXContext->SavedPad[5], pHTTXContext->SavedPad[6],pHTTXContext->SavedPad[7]));
}
pAd->bForcePrintTX = TRUE;
BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
pAd->BulkOutPending[BulkOutPipeId] = FALSE;
BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
/*DBGPRINT(RT_DEBUG_LOUD,("Out:pTxInfo->USBDMATxPktLen=%d!\n", pTxInfo->USBDMATxPktLen));*/
return;
}
/* Increase Total transmit byte counter*/
pAd->RalinkCounters.OneSecTransmittedByteCount += pTxWI->MPDUtotalByteCount;
pAd->RalinkCounters.TransmittedByteCount += pTxWI->MPDUtotalByteCount;
pLastTxInfo = pTxInfo;
#if !defined(CONFIG_MULTI_CHANNEL) && !defined(DOT11Z_TDLS_SUPPORT)
/* Make sure we use EDCA QUEUE. */
pTxInfo->QSEL = FIFO_EDCA;
#endif /* !defined(CONFIG_MULTI_CHANNEL) && !defined(DOT11Z_TDLS_SUPPORT) */
ThisBulkSize += (pTxInfo->USBDMATxPktLen+4);
TmpBulkEndPos += (pTxInfo->USBDMATxPktLen+4);
if (TmpBulkEndPos != pHTTXContext->CurWritePosition)
pTxInfo->USBDMANextVLD = 1;
#ifdef USB_BULK_BUF_ALIGMENT
/*
this is for frag packet , because it will finish this section
when ((((pHTTXContext->CurWritePosition + 3906)& 0x00007fff) & 0xffff6000) == 0x00006000)
*/
if (pTxInfo->SwRingUseLastRound == 1)
{
bLasAlignmentsectiontRound = TRUE;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxInfo, TYPE_TXINFO);
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
#endif /* RT_BIG_ENDIAN */
break;
}
#else
if (pTxInfo->SwRingUseLastRound == 1)
{
if (pHTTXContext->CurWritePosition == 8)
pTxInfo->USBDMANextVLD = 0;
pTxInfo->SwRingUseLastRound = 0;
bTxQLastRound = TRUE;
pHTTXContext->ENextBulkOutPosition = 8;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxInfo, TYPE_TXINFO);
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
#endif /* RT_BIG_ENDIAN */
break;
}
#endif /* USB_BULK_BUF_ALIGMENT */
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxInfo, TYPE_TXINFO);
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
#endif /* RT_BIG_ENDIAN */
}while (TRUE);
/* adjust the pTxInfo->USBDMANextVLD value of last pTxInfo.*/
if (pLastTxInfo)
{
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pLastTxInfo, TYPE_TXINFO);
#endif /* RT_BIG_ENDIAN */
pLastTxInfo->USBDMANextVLD = 0;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pLastTxInfo, TYPE_TXINFO);
#endif /* RT_BIG_ENDIAN */
}
/*
We need to copy SavedPad when following condition matched!
1. Not the last round of the TxQueue and
2. any match of following cases:
(1). The End Position of this bulk out is reach to the Currenct Write position and
the TxInfo and related header already write to the CurWritePosition.
=>(ENextBulkOutPosition == CurWritePosition) && (CurWriteRealPos > CurWritePosition)
(2). The EndPosition of the bulk out is not reach to the Current Write Position.
=>(ENextBulkOutPosition != CurWritePosition)
*/
#ifndef USB_BULK_BUF_ALIGMENT
if ((bTxQLastRound == FALSE) &&
(((pHTTXContext->ENextBulkOutPosition == pHTTXContext->CurWritePosition) && (pHTTXContext->CurWriteRealPos > pHTTXContext->CurWritePosition)) ||
(pHTTXContext->ENextBulkOutPosition != pHTTXContext->CurWritePosition))
)
{
NdisMoveMemory(pHTTXContext->SavedPad, &pWirelessPkt[pHTTXContext->ENextBulkOutPosition], 8);
pHTTXContext->bCopySavePad = TRUE;
if (RTMPEqualMemory(pHTTXContext->SavedPad, allzero,4))
{
PUCHAR pBuf = &pHTTXContext->SavedPad[0];
DBGPRINT_RAW(RT_DEBUG_ERROR,("WARNING-Zero-3:%02x%02x%02x%02x%02x%02x%02x%02x,CWPos=%ld, CWRPos=%ld, bCW=%d, NBPos=%ld, TBPos=%ld, TBSize=%ld\n",
pBuf[0], pBuf[1], pBuf[2],pBuf[3],pBuf[4], pBuf[5], pBuf[6],pBuf[7], pHTTXContext->CurWritePosition, pHTTXContext->CurWriteRealPos,
pHTTXContext->bCurWriting, pHTTXContext->NextBulkOutPosition, TmpBulkEndPos, ThisBulkSize));
pBuf = &pWirelessPkt[pHTTXContext->CurWritePosition];
DBGPRINT_RAW(RT_DEBUG_ERROR,("\tCWPos=%02x%02x%02x%02x%02x%02x%02x%02x\n", pBuf[0], pBuf[1], pBuf[2],pBuf[3],pBuf[4], pBuf[5], pBuf[6],pBuf[7]));
}
/*DBGPRINT(RT_DEBUG_LOUD,("ENPos==CWPos=%ld, CWRPos=%ld, bCSPad=%d!\n", pHTTXContext->CurWritePosition, pHTTXContext->CurWriteRealPos, pHTTXContext->bCopySavePad));*/
}
#endif /* USB_BULK_BUF_ALIGMENT */
if (pAd->bForcePrintTX == TRUE)
DBGPRINT(RT_DEBUG_TRACE,("BulkOut-A:Size=%ld, CWPos=%ld, NBPos=%ld, ENBPos=%ld, bCopy=%d!\n", ThisBulkSize, pHTTXContext->CurWritePosition, pHTTXContext->NextBulkOutPosition, pHTTXContext->ENextBulkOutPosition, pHTTXContext->bCopySavePad));
/*DBGPRINT(RT_DEBUG_LOUD,("BulkOut-A:Size=%ld, CWPos=%ld, CWRPos=%ld, NBPos=%ld, ENBPos=%ld, bCopy=%d, bLRound=%d!\n", ThisBulkSize, pHTTXContext->CurWritePosition, pHTTXContext->CurWriteRealPos, pHTTXContext->NextBulkOutPosition, pHTTXContext->ENextBulkOutPosition, pHTTXContext->bCopySavePad, bTxQLastRound));*/
/* USB DMA engine requires to pad extra 4 bytes. This pad doesn't count into real bulkoutsize.*/
pAppendant = &pWirelessPkt[TmpBulkEndPos];
NdisZeroMemory(pAppendant, 8);
ThisBulkSize += 4;
pHTTXContext->LastOne = TRUE;
pHTTXContext->BulkOutSize = ThisBulkSize;
#ifdef USB_BULK_BUF_ALIGMENT
/*
if it is the last alignment section round,that we just need to add nextbulkindex,
otherwise we both need to add nextbulkindex and CurWriteIdx
(because when alignment section round happened, the CurWriteIdx is added at function writing resource.)
*/
if(bLasAlignmentsectiontRound == TRUE)
{
CUR_WRITE_IDX_INC(pHTTXContext->NextBulkIdx, BUF_ALIGMENT_RINGSIZE);
pHTTXContext->ENextBulkOutPosition = 0;
}
else
{
CUR_WRITE_IDX_INC(pHTTXContext->NextBulkIdx, BUF_ALIGMENT_RINGSIZE);
pHTTXContext->ENextBulkOutPosition = 0;
CUR_WRITE_IDX_INC(pHTTXContext->CurWriteIdx, BUF_ALIGMENT_RINGSIZE);
pHTTXContext->CurWritePosition = 0;
}
#endif /* USB_BULK_BUF_ALIGMENT */
pAd->watchDogTxPendingCnt[BulkOutPipeId] = 1;
BULK_OUT_UNLOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags2);
/* Init Tx context descriptor*/
RTUSBInitHTTxDesc(pAd, pHTTXContext, BulkOutPipeId, ThisBulkSize, (usb_complete_t)RtmpUsbBulkOutDataPacketComplete);
#ifdef USB_BULK_BUF_ALIGMENT
pUrb = pHTTXContext->pUrb[pHTTXContext->CurtBulkIdx];
#else
pUrb = pHTTXContext->pUrb;
#endif /* USB_BULK_BUF_ALIGMENT */
if((ret = RTUSB_SUBMIT_URB(pUrb))!=0)
{
DBGPRINT(RT_DEBUG_ERROR, ("RTUSBBulkOutDataPacket: Submit Tx URB failed %d\n", ret));
BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
pAd->BulkOutPending[BulkOutPipeId] = FALSE;
pAd->watchDogTxPendingCnt[BulkOutPipeId] = 0;
BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
return;
}
BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
pHTTXContext->IRPPending = TRUE;
BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
pAd->BulkOutReq++;
}
/*
========================================================================
Routine Description:
Process MGMT ring DMA done interrupt, running in DPC level
Arguments:
pAd Pointer to our adapter
Return Value:
None
IRQL = DISPATCH_LEVEL
Note:
========================================================================
*/
VOID RTMPHandleMgmtRingDmaDoneInterrupt(
IN PRTMP_ADAPTER pAd)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PNDIS_PACKET pPacket;
/* int i;*/
UCHAR FREE = 0;
PRTMP_MGMT_RING pMgmtRing = &pAd->MgmtRing;
UINT8 TXWISize = pAd->chipCap.TXWISize;
NdisAcquireSpinLock(&pAd->MgmtRingLock);
RTMP_IO_READ32(pAd, TX_MGMTDTX_IDX, &pMgmtRing->TxDmaIdx);
while (pMgmtRing->TxSwFreeIdx!= pMgmtRing->TxDmaIdx)
{
FREE++;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
#endif
/* pTxD->DMADONE = 0; */
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket;
if (pPacket == NULL)
{
INC_RING_INDEX(pMgmtRing->TxSwFreeIdx, MGMT_RING_SIZE);
continue;
}
#define LMR_FRAME_GET() (GET_OS_PKT_DATAPTR(pPacket) + TXWISize)
#ifdef UAPSD_SUPPORT
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
UAPSD_QoSNullTxMgmtTxDoneHandle(pAd,
pPacket,
LMR_FRAME_GET());
}
#endif /* CONFIG_AP_SUPPORT */
#endif /* UAPSD_SUPPORT */
#ifdef CONFIG_AP_SUPPORT
#endif /* CONFIG_AP_SUPPORT */
if (pPacket)
{
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, RTMP_PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket = NULL;
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket;
if (pPacket)
{
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, RTMP_PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket = NULL;
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocPa,
RXD_SIZE);
INC_RING_INDEX(pMgmtRing->TxSwFreeIdx, MGMT_RING_SIZE);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, TRUE, TYPE_TXD);
#endif
}
NdisReleaseSpinLock(&pAd->MgmtRingLock);
}
/*
========================================================================
Routine Description:
Arguments:
Return Value:
Note: MLME use BulkOutPipeId = 0
========================================================================
*/
VOID RTUSBBulkOutMLMEPacket(
IN PRTMP_ADAPTER pAd,
IN UCHAR Index)
{
PTX_CONTEXT pMLMEContext;
PURB pUrb;
int ret = 0;
unsigned long IrqFlags;
pMLMEContext = (PTX_CONTEXT)pAd->MgmtRing.Cell[pAd->MgmtRing.TxDmaIdx].AllocVa;
pUrb = pMLMEContext->pUrb;
if ((pAd->MgmtRing.TxSwFreeIdx >= MGMT_RING_SIZE) ||
(pMLMEContext->InUse == FALSE) ||
(pMLMEContext->bWaitingBulkOut == FALSE))
{
/* Clear MLME bulk flag*/
RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_MLME);
return;
}
RTMP_IRQ_LOCK(&pAd->BulkOutLock[MGMTPIPEIDX], IrqFlags);
if ((pAd->BulkOutPending[MGMTPIPEIDX] == TRUE) || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_TX))
{
RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[MGMTPIPEIDX], IrqFlags);
return;
}
pAd->BulkOutPending[MGMTPIPEIDX] = TRUE;
pAd->watchDogTxPendingCnt[MGMTPIPEIDX] = 1;
pMLMEContext->IRPPending = TRUE;
pMLMEContext->bWaitingBulkOut = FALSE;
RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[MGMTPIPEIDX], IrqFlags);
/* Increase Total transmit byte counter*/
pAd->RalinkCounters.TransmittedByteCount += pMLMEContext->BulkOutSize;
/* Clear MLME bulk flag*/
RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_MLME);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pMLMEContext->TransferBuffer, TYPE_TXINFO);
#endif /* RT_BIG_ENDIAN */
/* Init Tx context descriptor*/
RTUSBInitTxDesc(pAd, pMLMEContext, MGMTPIPEIDX, (usb_complete_t)RtmpUsbBulkOutMLMEPacketComplete);
RTUSB_URB_DMA_MAPPING(pUrb);
pUrb = pMLMEContext->pUrb;
if((ret = RTUSB_SUBMIT_URB(pUrb))!=0)
{
DBGPRINT(RT_DEBUG_ERROR, ("RTUSBBulkOutMLMEPacket: Submit MLME URB failed %d\n", ret));
RTMP_IRQ_LOCK(&pAd->BulkOutLock[MGMTPIPEIDX], IrqFlags);
pAd->BulkOutPending[MGMTPIPEIDX] = FALSE;
pAd->watchDogTxPendingCnt[MGMTPIPEIDX] = 0;
pMLMEContext->IRPPending = FALSE;
pMLMEContext->bWaitingBulkOut = TRUE;
RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[MGMTPIPEIDX], IrqFlags);
return;
}
}
PNDIS_PACKET GetPacketFromRxRing(
IN PRTMP_ADAPTER pAd,
OUT PRT28XX_RXD_STRUC pSaveRxD,
OUT BOOLEAN *pbReschedule,
IN OUT UINT32 *pRxPending)
{
PRXD_STRUC pRxD;
#ifdef RT_BIG_ENDIAN
PRXD_STRUC pDestRxD;
RXD_STRUC RxD;
#endif
PNDIS_PACKET pRxPacket = NULL;
PNDIS_PACKET pNewPacket;
PVOID AllocVa;
NDIS_PHYSICAL_ADDRESS AllocPa;
BOOLEAN bReschedule = FALSE;
RTMP_SEM_LOCK(&pAd->RxRingLock);
if (*pRxPending == 0)
{
RTMP_IO_READ32(pAd, RX_DRX_IDX , &pAd->RxRing.RxDmaIdx);
if (pAd->RxRing.RxSwReadIdx == pAd->RxRing.RxDmaIdx)
{
bReschedule = FALSE;
goto done;
}
if (pAd->RxRing.RxDmaIdx > pAd->RxRing.RxSwReadIdx)
*pRxPending = pAd->RxRing.RxDmaIdx - pAd->RxRing.RxSwReadIdx;
else
*pRxPending = pAd->RxRing.RxDmaIdx + RX_RING_SIZE - pAd->RxRing.RxSwReadIdx;
}
#ifdef RT_BIG_ENDIAN
pDestRxD = (PRXD_STRUC) pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].AllocVa;
RxD = *pDestRxD;
pRxD = &RxD;
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
#else
pRxD = (PRXD_STRUC) pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].AllocVa;
#endif
if (pRxD->DDONE == 0)
{
*pRxPending = 0;
bReschedule = TRUE;
goto done;
}
NdisMoveMemory(pSaveRxD, pRxD, RXD_SIZE);
pNewPacket = RTMP_AllocateRxPacketBuffer(pAd, RX_BUFFER_AGGRESIZE, FALSE, &AllocVa, &AllocPa);
if (pNewPacket)
{
PCI_UNMAP_SINGLE(pAd, pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].DmaBuf.AllocPa,
pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].DmaBuf.AllocSize, PCI_DMA_FROMDEVICE);
pRxPacket = pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].pNdisPacket;
pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].DmaBuf.AllocSize = RX_BUFFER_AGGRESIZE;
pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].pNdisPacket = (PNDIS_PACKET) pNewPacket;
pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].DmaBuf.AllocVa = AllocVa;
pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].DmaBuf.AllocPa = AllocPa;
pRxD->SDP0 = AllocPa;
}
else
{
pRxPacket = NULL;
bReschedule = TRUE;
}
pRxD->DDONE = 0;
*pRxPending = *pRxPending - 1;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxD, (PUCHAR)pRxD, FALSE, TYPE_RXD);
#endif
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
done:
RTMP_SEM_UNLOCK(&pAd->RxRingLock);
*pbReschedule = bReschedule;
return pRxPacket;
}
