/* freq is in MHz */
int
rtw_phy_init(struct rtw_regs *regs, struct rtw_rf *rf, uint8_t opaque_txpower,
uint8_t cs_threshold, u_int freq, int antdiv, int dflantb,
enum rtw_pwrstate power)
{
int rc;
RTW_DPRINTF(RTW_DEBUG_PHY,
("%s: txpower %u csthresh %u freq %u antdiv %u dflantb %u "
"pwrstate %s\n", __func__, opaque_txpower, cs_threshold, freq,
antdiv, dflantb, rtw_pwrstate_string(power)));
/* XXX is this really necessary? */
if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0)
return rc;
if ((rc = rtw_bbp_preinit(regs, rf->rf_bbpset.bb_antatten, dflantb,
freq)) != 0)
return rc;
if ((rc = rtw_rf_tune(rf, freq)) != 0)
return rc;
/* initialize RF */
if ((rc = rtw_rf_init(rf, freq, opaque_txpower, power)) != 0)
return rc;
#if 0 /* what is this redundant tx power setting here for? */
if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0)
return rc;
#endif
return rtw_bbp_init(regs, &rf->rf_bbpset, antdiv, dflantb,
cs_threshold, freq);
}
void
rtw_cardbus_power(struct rtw_softc *sc, int why)
{
RTW_DPRINTF(RTW_DEBUG_ATTACH,
("%s: rtw_cardbus_power\n", sc->sc_dev.dv_xname));
if (why == DVACT_RESUME)
rtw_enable(sc);
}
static int
rtw_grf5101_tune(struct rtw_rf *rf, u_int freq)
{
int channel;
struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
if (freq == 2484)
channel = 14;
else if ((channel = (freq - 2412) / 5 + 1) < 1 || channel > 13) {
RTW_DPRINTF(RTW_DEBUG_PHY,
("%s: invalid channel %d (freq %d)\n", __func__, channel,
freq));
return -1;
}
GCT_WRITE(gr, 0x07, 0, err);
GCT_WRITE(gr, 0x0b, channel - 1, err);
GCT_WRITE(gr, 0x07, 0x1000, err);
return 0;
err:
return -1;
}
void
rtw_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct rtw_cardbus_softc *csc = (void *)self;
struct rtw_softc *sc = &csc->sc_rtw;
struct rtw_regs *regs = &sc->sc_regs;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
bus_addr_t adr;
int rev;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_pc = ca->ca_pc;
/*
* Power management hooks.
*/
sc->sc_enable = rtw_cardbus_enable;
sc->sc_disable = rtw_cardbus_disable;
sc->sc_power = rtw_cardbus_power;
sc->sc_intr_ack = rtw_cardbus_intr_ack;
/* Get revision info. */
rev = PCI_REVISION(ca->ca_class);
RTW_DPRINTF(RTW_DEBUG_ATTACH,
("%s: pass %d.%d signature %08x\n", sc->sc_dev.dv_xname,
(rev >> 4) & 0xf, rev & 0xf,
pci_conf_read(ca->ca_pc, csc->sc_tag, 0x80)));
/*
* Map the device.
*/
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
if (Cardbus_mapreg_map(ct, RTW_PCI_MMBA,
PCI_MAPREG_TYPE_MEM, 0, ®s->r_bt, ®s->r_bh, &adr,
&csc->sc_mapsize) == 0) {
RTW_DPRINTF(RTW_DEBUG_ATTACH,
("%s: %s mapped %lu bytes mem space\n",
sc->sc_dev.dv_xname, __func__, (long)csc->sc_mapsize));
csc->sc_cben = CARDBUS_MEM_ENABLE;
csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
csc->sc_bar_reg = RTW_PCI_MMBA;
csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
} else if (Cardbus_mapreg_map(ct, RTW_PCI_IOBA,
PCI_MAPREG_TYPE_IO, 0, ®s->r_bt, ®s->r_bh, &adr,
&csc->sc_mapsize) == 0) {
RTW_DPRINTF(RTW_DEBUG_ATTACH,
("%s: %s mapped %lu bytes I/O space\n",
sc->sc_dev.dv_xname, __func__, (long)csc->sc_mapsize));
csc->sc_cben = CARDBUS_IO_ENABLE;
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
csc->sc_bar_reg = RTW_PCI_IOBA;
csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO;
} else {
printf("%s: unable to map device registers\n",
sc->sc_dev.dv_xname);
return;
}
/*
* Bring the chip out of powersave mode and initialize the
* configuration registers.
*/
rtw_cardbus_setup(csc);
/* Remember which interrupt line. */
csc->sc_intrline = ca->ca_intrline;
printf(": irq %d\n", csc->sc_intrline);
/*
* Finish off the attach.
*/
rtw_attach(sc);
rtw_cardbus_funcregen(regs, 1);
RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_INTR);
RTW_WRITE(regs, RTW_FER, RTW_FER_INTR);
/*
* Power down the socket.
*/
Cardbus_function_disable(csc->sc_ct);
}
