static void mmc_send_command(S5pc1xxMMCState *s)
{
SDRequest request;
uint8_t response[16];
int rlen;
s->errintsts = 0;
qemu_mod_timer(s->response_timer, qemu_get_clock(vm_clock));
if (!s->card)
return;
request.cmd = s->cmdreg >> 8;
request.arg = s->cmdarg;
DPRINTF("Command %d %08x\n", request.cmd, request.arg);
rlen = sd_do_command(s->card, &request, response);
if (rlen < 0)
goto error;
if ((s->cmdreg & CMD_RESPONSE) != 0) {
#define RWORD(n) ((n >= 0 ? (response[n] << 24) : 0) \
| (response[n + 1] << 16) \
| (response[n + 2] << 8) \
| response[n + 3])
if (rlen == 0)
goto error;
if (rlen != 4 && rlen != 16)
goto error;
s->response[0] = RWORD(0);
if (rlen == 4) {
s->response[1] = s->response[2] = s->response[3] = 0;
} else {
s->response[0] = RWORD(11);
s->response[1] = RWORD(7);
s->response[2] = RWORD(3);
s->response[3] = RWORD(-1);
}
DPRINTF("Response received\n");
#undef RWORD
} else {
DPRINTF("Command sent\n");
}
return;
error:
DPRINTF("Timeout\n");
s->errintsts |= S5C_HSMMC_EIS_CMDTIMEOUT;
}
static void pl181_send_command(pl181_state *s)
{
struct sd_request_s request;
uint8_t response[16];
int rlen;
request.cmd = s->cmd & PL181_CMD_INDEX;
request.arg = s->cmdarg;
DPRINTF("Command %d %08x\n", request.cmd, request.arg);
rlen = sd_do_command(s->card, &request, response);
if (rlen < 0)
goto error;
if (s->cmd & PL181_CMD_RESPONSE) {
#define RWORD(n) ((response[n] << 24) | (response[n + 1] << 16) \
| (response[n + 2] << 8) | response[n + 3])
if (rlen == 0 || (rlen == 4 && (s->cmd & PL181_CMD_LONGRESP)))
goto error;
if (rlen != 4 && rlen != 16)
goto error;
s->response[0] = RWORD(0);
if (rlen == 4) {
s->response[1] = s->response[2] = s->response[3] = 0;
} else {
s->response[1] = RWORD(4);
s->response[2] = RWORD(8);
s->response[3] = RWORD(12) & ~1;
}
DPRINTF("Response received\n");
s->status |= PL181_STATUS_CMDRESPEND;
#undef RWORD
} else {
DPRINTF("Command sent\n");
s->status |= PL181_STATUS_CMDSENT;
}
return;
error:
DPRINTF("Timeout\n");
s->status |= PL181_STATUS_CMDTIMEOUT;
}
static void t11_check_irqs(void)
{
const struct irq_table_entry *irq = &irq_table[t11.irq_state & 15];
int priority = PSW & 0xe0;
/* compare the priority of the interrupt to the PSW */
if (irq->priority > priority)
{
int vector = irq->vector;
int new_pc, new_psw;
/* call the callback; if we don't get -1 back, use the return value as our vector */
if (t11.irq_callback != NULL)
{
int new_vector = (*t11.irq_callback)(t11.irq_state & 15);
if (new_vector != -1)
vector = new_vector;
}
/* fetch the new PC and PSW from that vector */
assert((vector & 3) == 0);
new_pc = RWORD(vector);
new_psw = RWORD(vector + 2);
/* push the old state, set the new one */
PUSH(PSW);
PUSH(PC);
PCD = new_pc;
PSW = new_psw;
change_pc(PC);
t11_check_irqs();
/* count cycles and clear the WAIT flag */
t11.interrupt_cycles += 114;
t11.wait_state = 0;
}
}
static void t11_check_irqs(t11_state *cpustate)
{
const struct irq_table_entry *irq = &irq_table[cpustate->irq_state & 15];
int priority = cpustate->PSW & 0xe0;
/* compare the priority of the interrupt to the PSW */
if (irq->priority > priority)
{
int vector = irq->vector;
int new_pc, new_psw;
/* call the callback; if we don't get -1 back, use the return value as our vector */
if (cpustate->irq_callback != NULL)
{
int new_vector = (*cpustate->irq_callback)(cpustate->device, cpustate->irq_state & 15);
if (new_vector != -1)
vector = new_vector;
}
/* fetch the new PC and PSW from that vector */
assert((vector & 3) == 0);
new_pc = RWORD(cpustate, vector);
new_psw = RWORD(cpustate, vector + 2);
/* push the old state, set the new one */
PUSH(cpustate, cpustate->PSW);
PUSH(cpustate, cpustate->PC);
cpustate->PCD = new_pc;
cpustate->PSW = new_psw;
t11_check_irqs(cpustate);
/* count cycles and clear the WAIT flag */
cpustate->icount -= 114;
cpustate->wait_state = 0;
}
}
void dsp32c_device::dma_load()
{
// only process if DMA is enabled
if (m_pcr & PCR_DMA)
{
UINT32 addr = m_par | (m_pare << 16);
// 16-bit case
if (!(m_pcr & PCR_DMA32))
m_pdr = RWORD(addr & 0xfffffe);
// 32-bit case
else
{
UINT32 temp = RLONG(addr & 0xfffffc);
m_pdr = temp >> 16;
m_pdr2 = temp & 0xffff;
}
// set the PDF flag to indicate we have data ready
update_pcr(m_pcr | PCR_PDFs);
}
INLINE void dma_load(void)
{
/* only process if DMA is enabled */
if (dsp32.pcr & PCR_DMA)
{
UINT32 addr = dsp32.par | (dsp32.pare << 16);
/* 16-bit case */
if (!(dsp32.pcr & PCR_DMA32))
dsp32.pdr = RWORD(addr & 0xfffffe);
/* 32-bit case */
else
{
UINT32 temp = RLONG(addr & 0xfffffc);
dsp32.pdr = temp >> 16;
dsp32.pdr2 = temp & 0xffff;
}
/* set the PDF flag to indicate we have data ready */
update_pcr(dsp32.pcr | PCR_PDFs);
}
INLINE void dma_load(dsp32_state *cpustate)
{
/* only process if DMA is enabled */
if (cpustate->pcr & PCR_DMA)
{
UINT32 addr = cpustate->par | (cpustate->pare << 16);
/* 16-bit case */
if (!(cpustate->pcr & PCR_DMA32))
cpustate->pdr = RWORD(cpustate, addr & 0xfffffe);
/* 32-bit case */
else
{
UINT32 temp = RLONG(cpustate, addr & 0xfffffc);
cpustate->pdr = temp >> 16;
cpustate->pdr2 = temp & 0xffff;
}
/* set the PDF flag to indicate we have data ready */
update_pcr(cpustate, cpustate->pcr | PCR_PDFs);
}
INLINE int POP(void)
{
int result = RWORD(SPD);
SP += 2;
return result;
}
INLINE int POP(t11_state *cpustate)
{
int result = RWORD(cpustate, cpustate->SPD);
cpustate->SP += 2;
return result;
}
int t11_device::POP()
{
int result = RWORD(SPD);
SP += 2;
return result;
}