void SRamSPI::readstream(unsigned int address)
{
deselectSS; //deselect if still selected
selectSS; //select now
RWdata(0x03);//read from address
RWdata(address >> 8);//read from address
RWdata(address);
}//end of read stream
void SRAM2class::readstream1(int address)
{
deselectSS1; //deselect if still selected
deselectSS2; //deselect if still selected
selectSS1; //select now
RWdata(0x03);//read from address
RWdata(address >> 8);//read from address
RWdata(address);
}//end of read stream SRAM1
void SRAM2class::writestream2(int address)
{
deselectSS1; //deselect if still selected
deselectSS2; //deselect if still selected
selectSS2; //select now
RWdata(0x02);//write to address
RWdata(address >> 8);//msb address
RWdata(address);//lsb address
}//end of write stream SRAM 2
void SRAMclass::readstream(long address)
{
deselectSS; //deselect if still selected
selectSS; //select now
RWdata(0x03);//read from address
RWdata((address >> 16) & 0xFF);//read from address
RWdata((address >> 8) & 0xFF);//read from address
RWdata(address);
}//end of read stream
void SRamSPI::writestream(unsigned int address)
{
deselectSS; //deselect if still selected
selectSS; //select now
RWdata(0x02);//write to address
RWdata(address >> 8);//msb address
RWdata(address);//lsb address
}//end of write stream
void SRAMclass::writestream(long address)
{
deselectSS; //deselect if still selected
digitalWrite(10,HIGH);
selectSS; //select now
RWdata(0x02);//write to address
RWdata((address >> 16) & 0xFF);//read from address
RWdata((address >> 8) & 0xFF);//read from address
RWdata(address);//lsb address
}//end of write stream
SRAM2class::SRAM2class() //constructor
{
setupDDRB;
setupSPI;
deselectSS1; //deselect if selected
deselectSS2; //deselect if selected
selectSS1; //setup SRAM1
RWdata(0x05);//read status register
int Sreg = RWdata(0xff);//get status value
deselectSS1;
if(Sreg != 0x41) //are we in sequential mode
{
selectSS1;
RWdata(0x01); //write to status reg
RWdata(0x41); //set sequencial mode
deselectSS1;
}//end of set sequential mode for SRAM1
selectSS2; //setup SRAM2
RWdata(0x05);//read status register
Sreg = RWdata(0xff);//get status value
deselectSS2;
if(Sreg != 0x41) //are we in sequential mode
{
selectSS2;
RWdata(0x01); //write to status reg
RWdata(0x41); //set sequencial mode
deselectSS2;
}//end of set sequential mode for SRAM2
}//end of constructor
uint8_t SRamSPI::read(unsigned int address)
{
uint8_t c;
readstream(address);
c = RWdata(0xFF);
closeRWstream();
return c;
}
SRAMclass::SRAMclass() //constructor
{
setupDDRB;
setupSPI;
pinMode(SS9, OUTPUT);
selectSS;
RWdata(0x05);//read status register
int Sreg = RWdata(0xff);//get status value
deselectSS;
if(Sreg != 0x41) //are we in sequential mode
{
selectSS;
RWdata(0x01); //write to status reg
RWdata(0x41); //set sequencial mode
deselectSS;
}//end of set sequential mode
}//end of constructor
SRamSPI::SRamSPI(byte CSPin) //constructor
{
csPin = CSPin;
setupDDRB;
digitalWrite(10,HIGH); //required to setup SPI
setupSPI;
pinMode(csPin , OUTPUT);
selectSS;
RWdata(0x05);//read status register
int Sreg = RWdata(0xff);//get status value
deselectSS;
if(Sreg != 0x41) //are we in sequential mode
{
selectSS;
RWdata(0x01); //write to status reg
RWdata(0x41); //set sequencial mode
deselectSS;
}//end of set sequential mode
//deselectSS;
}//end of constructor
void SRamSPI::write(unsigned int address, uint8_t c)
{
writestream(address);
RWdata(c);
closeRWstream();
}
