void iep_set_deinterlace_mode(int mode, void *base)
{
int cfg;
if (mode > dein_mode_bypass) {
IEP_ERR("invalid deinterlace mode\n");
return;
}
cfg = ReadReg32(base, RAW_IEP_CONFIG0);
cfg = (cfg & (~(7<<8))) | (mode << 8);
WriteReg32(base, IEP_CONFIG0, cfg);
//IEP_REGB_DIL_MODE(base, mode);
}
void iep_soft_rst(void *base)
{
unsigned int rst_state = 0;
int i = 0;
WriteReg32(base, rIEP_SOFT_RST, 2);
WriteReg32(base, rIEP_SOFT_RST, 1);
while (i++ < IEP_RESET_TIMEOUT) {
rst_state = ReadReg32(base, IEP_STATUS);
if ((rst_state & 0x200) == 0x200) {
break;
}
udelay(1);
}
WriteReg32(base, IEP_SOFT_RST, 2);
if (i == IEP_RESET_TIMEOUT) IEP_DBG("soft reset timeout.\n");
}
void iep_switch_input_address(void *base) {
u32 src_addr_yrgb = ReadReg32(base, IEP_SRC_ADDR_YRGB);
u32 src_addr_cbcr = ReadReg32(base, IEP_SRC_ADDR_CBCR);
u32 src_addr_cr = ReadReg32(base, IEP_SRC_ADDR_CR);
u32 src_addr_y1 = ReadReg32(base, IEP_SRC_ADDR_Y1);
u32 src_addr_cbcr1 = ReadReg32(base, IEP_SRC_ADDR_CBCR1);
u32 src_addr_cr1 = ReadReg32(base, IEP_SRC_ADDR_CR1);
IEP_REGB_SRC_ADDR_YRGB (base, src_addr_y1);
IEP_REGB_SRC_ADDR_CBCR (base, src_addr_cbcr1);
IEP_REGB_SRC_ADDR_CR (base, src_addr_cr1);
IEP_REGB_SRC_ADDR_Y1 (base, src_addr_yrgb);
IEP_REGB_SRC_ADDR_CBCR1(base, src_addr_cbcr);
IEP_REGB_SRC_ADDR_CR1 (base, src_addr_cr);
}
bool BdPortInit(uint32 * BaseAddress, uint32 BaudRate)
{
#define PADCONF_CTS ((1 << 4) | (1 << 3) | (1 << 8))
#define PADCONF_RTS (0)
#define PADCONF_TX (0)
#define PADCONF_RX ((1 << 3) | (1 << 8))
uartBase = BaseAddress;
uint8 * HalpSCM = (uint8 *)OMAP_SCM_BASE;
uint8 * HalpCORE_CM = (uint8 *)OMAP_CORE_CM_BASE;
uint32 Value;
if (BaseAddress == (uint32 *)OMAP_UART1_BASE) {
// Power on the required function and interface units.
Value = ReadReg32(HalpCORE_CM + CM_FCLKEN1_CORE);
Value |= CM_CORE_EN_UART1;
WriteReg32(HalpCORE_CM + CM_FCLKEN1_CORE, Value);
Value = ReadReg32(HalpCORE_CM + CM_ICLKEN1_CORE);
Value |= CM_CORE_EN_UART1;
WriteReg32(HalpCORE_CM + CM_ICLKEN1_CORE, Value);
// Configure uart1 pads per documentation example
WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART1_TX,
PADCONF_TX | (PADCONF_RTS << 16));
WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART1_CTS,
PADCONF_CTS | (PADCONF_RX << 16));
}
else if (BaseAddress == (uint32 *)OMAP_UART2_BASE) {
// Power on the required function and interface units.
Value = ReadReg32(HalpCORE_CM + CM_FCLKEN1_CORE);
Value |= CM_CORE_EN_UART2;
WriteReg32(HalpCORE_CM + CM_FCLKEN1_CORE, Value);
Value = ReadReg32(HalpCORE_CM + CM_ICLKEN1_CORE);
Value |= CM_CORE_EN_UART2;
WriteReg32(HalpCORE_CM + CM_ICLKEN1_CORE, Value);
WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART2_CTS,
PADCONF_CTS | (PADCONF_RTS << 16));
WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART2_TX,
PADCONF_TX | (PADCONF_RX << 16));
}
// Set the default baudrate.
UartSetBaudRate(BaseAddress, BaudRate);
// Set DLAB to zero. DLAB controls the meaning of the first two
// registers. When zero, the first register is used for all byte transfer
// and the second register controls device interrupts.
//
WriteReg8(BaseAddress + COM_LCR,
ReadReg8(BaseAddress + COM_LCR) & ~LCR_DLAB);
// Disable device interrupts. This implementation will handle state
// transitions by request only.
//
WriteReg8(BaseAddress + COM_IEN, 0);
// Reset and disable the FIFO queue.
// N.B. FIFO will be reenabled before returning from this routine.
//
WriteReg8(BaseAddress + COM_FCR, FCR_CLEAR_TRANSMIT | FCR_CLEAR_RECEIVE);
// Configure the Modem Control Register. Disabled device interrupts,
// turn off loopback.
//
WriteReg8(BaseAddress + COM_MCR,
ReadReg8(BaseAddress + COM_MCR) & MCR_INITIALIZE);
// Initialize the Modem Control Register. Indicate to the device that
// we are able to send and receive data.
//
WriteReg8(BaseAddress + COM_MCR, MCR_INITIALIZE);
// Enable the FIFO queues.
WriteReg8(BaseAddress + COM_FCR, FCR_ENABLE);
return true;
}
int iep_probe_int(void *base)
{
return ReadReg32(base, rIEP_INT) & 1;
}
int iep_get_deinterlace_mode(void *base)
{
int cfg = ReadReg32(base, IEP_CONFIG0);
return (cfg >> 8) & 0x7;
}
