void ProcessTransmitLpduM2m(void) { register long i,j; register char *pSrc,*pDst; register void* pv; struct { //unsigned char uchTR_C; unsigned short uShIdxByte ; unsigned short ushSizeLDC; //unsigned char *pUchRV; } sLV; union { unsigned char uchAr [4]; unsigned short ushAr [2]; unsigned long ulVal; }unnV1; pv = (void*)&hldrM2mLpduTRUnit; pSrc = (char*)&hldrTpCnState; j = ((TRStateLpuM2mDsc*)pv)->uchLpuM2mState ; if (j!=0) return; //Start for Activating of Lpdu Units j = ((StateTpCnDsc*)pSrc)->uchTpState_CNL_M2m;// if (j==0) return; ((TRStateLpuM2mDsc*)pv)->uchCI = HDR_MODE_CNL_M2M;//HDR_MODE_CNL_1; ((TRStateLpuM2mDsc*)pv)->uchLpuM2mState = 1; i = ((StateTpCnDsc*)pSrc)->PayloadLPDU_M2m +(SIZE_LDC_FLD_CNL_M2M)+(SIZE_TOTAL_LDC); // - ((StateTpCnDsc*)pSrc)->lCapicity_CNL_HSU7; sLV.ushSizeLDC = i; ((TRStateLpuM2mDsc*)pv)->lCapicity = i+(SIZE_LPCI_FLD_CNL_M2M);//Real Size Pacet //.((StateTpCnDsc*)pSrc)->lCapicity_CNL_HSU7 =((StateTpCnDsc*)pSrc)->PayloadLPDU_HSU7; //Create Pacet ((TRStateLpuM2mDsc*)pv)->uchCI = (HDR_MODE_CNL_M2M); ((TRStateLpuM2mDsc*)pv)->ushSizeLDC = i;//((TRStateLpuM2mDsc*)pv)->lCapicity; j = 0; (((TRStateLpuM2mDsc*)pv)->arUch[0]) = ((TRStateLpuM2mDsc*)pv)->uchCI; i = ((TRStateLpuM2mDsc*)pv)->uchCI; i &= 0xf; i>>=1; switch (i) { case 0: j = 0; break; case 1: (((TRStateLpuM2mDsc*)pv)->arUch[j+1]) = ((TRStateLpuM2mDsc*)pv)->ushSizeLDC; j = 1; break; case 2: pDst = (char*)&(((TRStateLpuM2mDsc*)pv)->arUch[j+1]); unnV1.ushAr[0] = ((TRStateLpuM2mDsc*)pv)->ushSizeLDC; //*((short*)pDst) = pDst[0] = unnV1.uchAr[0]; pDst[1] = unnV1.uchAr[1]; j = 2; break; default: j=1; } sLV.uShIdxByte = j; ///////////////////PUT TOT LDC FIELD//////////////////// pDst = (char*)&(((TRStateLpuM2mDsc*)pv)->arUch[j+1]); *(pDst) = ((StateTpCnDsc*)pSrc)->chTotalLDC_CNL_M2m; //////////////////////////////////////////////////////// //....pSrc = (char*)&arCh[0];//Tempor Data !!! pDst = (char*) &(((TRStateLpuM2mDsc*)pv)->arUch[j+1]); //sLV.uShIdxByte += SIZE FIELD _TOTAL_LDC; .iNCLUDED IN ushSizeLDC j = ((TRStateLpuM2mDsc*)pv)->ushSizeLDC; //sLV.uShIdxByte += sLV.ushSizeLDC;//j; //for (i = 0; i< j; i++) //pDst[i] = pSrc[i]; //Check CS i = Eval_CS((char*)&(((RVStateLpuU3Dsc*)pv)->arUch[0]),((TRStateLpuM2mDsc*)pv)->lCapicity);//sLV.uShIdxByte ((TRStateLpuM2mDsc*)pv)-> lCs = i; j = ((TRStateLpuM2mDsc*)pv)->lCapicity;//sLV.uShIdxByte;<- Must be true Index at end of the data //Move Data to transmit (((TRStateLpuM2mDsc*)pv)->arUch[j]) = i; //j = outCY7((unsigned char *)&(((TRStateLpuM2mDsc*)pv)->arUch[0]),(int)j+(SIZE_CS_FLD_CNL_M2M)); j = outCY7V1((unsigned char *)&(((TRStateLpuM2mDsc*)pv)->arUch[0]),(int)j+(SIZE_CS_FLD_CNL_M2M)); hldrM2mLpduTRUnit.uchLpuM2mState = 0; Rst_LpduM2m_TpCnState(); }
void ici_hdw_init(void) { //register long i; UART_CBS_T cbs; UART_CONTROL_T ucntl; //- typedef enum //- { //- UART_PAR_NONE, //- UART_PAR_EVEN, //- UART_PAR_ODD //- } UART_PAR_T; //- //- /* UART control */ //- typedef struct //- { //- UNS_32 baud_rate; /* Device baud rate */ //- UART_PAR_T parity; /* Parity selection */ //- UNS_32 databits; /* Number of data bits */ //- UNS_32 stopbits; /* Number of stop bits */ //- } UART_CONTROL_T; timer0dev = Timer_open(TIMER_CNTR0, 0); TIMER_CNTR_REGS_T *pTimer = TIMER_CNTR0; /* //-* Reset timer *-/ pTimer->tcr = TIMER_CNTR_TCR_RESET; pTimer->tcr = 0; //-* Count mode is PCLK edge *-/ pTimer->ctcr = TIMER_CNTR_SET_MODE(TIMER_CNTR_CTCR_TIMER_MODE); //-* Set prescale counter value for a 1uS tick *-/ pTimer->pr = (UNS_32) Timer_usec_to_val( CLKPWR_TIMER0_CLK, 1); //case TMR_VALUE_ST: // status = pTimer->tc; // break; //-* Enable the timer *-/ pTimer->tcr = TIMER_CNTR_TCR_EN; //-* Stop timer *-/ //pTimer->tcr = 0; */ //Init Module New //-* Enable timer system clock *-/ //.clkpwr_clk_en_dis(timer_num_to_clk_enum[timernum], 1); //-* Reset timer *-/ pTimer->tcr = TIMER_CNTR_TCR_RESET; pTimer->tcr = 0;pTimer->tc = 0; //-* Clear and enable match function *-/ pTimer->ir = TIMER_CNTR_MTCH_BIT(0); //-* Count mode is PCLK edge *-/ pTimer->ctcr = TIMER_CNTR_SET_MODE(TIMER_CNTR_CTCR_TIMER_MODE); //-* Set prescale counter value for a 1uS tick *-/ pTimer->pr = (UNS_32) Timer_usec_to_val( CLKPWR_TIMER0_CLK, 1); //-* Set match for number of usecs *-/ pTimer->mr[0] = 20000;//-usec; //-* Interrupt on match 0 *-/ pTimer->mcr = TIMER_CNTR_MCR_MTCH(0)|TIMER_CNTR_MCR_RESET(0); //-* Install timer interrupts handlers as a IRQ interrupts *-/ int_install_irq_handler(IRQ_TIMER0, (PFV) timer0_user_interrupt); //~ ucntl.baud_rate = 115200; //~ ucntl.parity = UART_PAR_NONE; //~ ucntl.databits = 8; //~ ucntl.stopbits = 1; //~ uartdev = Uart_open((void *) UART3, (INT_32) & ucntl); //~ if (uartdev != 0) //~ { //~ /* Setup RX and TX callbacks */ //~ cbs.rxcb = recv_cb; //~ cbs.txcb = send_cb; //~ cbs.rxerrcb = NULL; //~ Uart_ioctl(uartdev, UART_INSTALL_CBS, (INT_32) &cbs); //~ //.int_enable(IRQ_UART_IIR3); //~ } //~ //~ /* Initialize TX and RX ring buffers */ //~ //txfill = txget = rxfill = rxget = txsize = rxsize = 0; //~ Rst_LpduHSU2_TpCnState(); //~ /* Enable interrupts */ //~ int_enable(IRQ_UART_IIR3); //~ hs7_uart_hdw_init(); //~ hs1_uart_hdw_init(); //~ hs2_uart_hdw_init(); //~ //~ enable_irq(); //~ //int_enable(IRQ_UART_IIR7); //~ int_enable(IRQ_UART_IIR1); //~ int_enable(IRQ_UART_IIR2); ssp1_hdr_init(); Rst_LpduM2m_TpCnState(); Rst_LpduSpi_TpCnState(); GPIO->p0_mux_clr = 0xff; GPIO->p0_dir_clr = 0xff; GPIO->p0_dir_set = 0xf0; GPIO->p0_outp_clr =0xf0; M16_J18_K18_A15_PioInit(); //p3_outp_state AppReqTransmitTotVerInfoBrBs = 1; Int_install_ext_irq_handler(IRQ_GPIO_01,P02Int,FALLING_EDGE,0);//Interrupt in this place never can be workd look p606 datasheet - Only pin sic[8] activated Int_install_ext_irq_handler(IRQ_P0_P1_IRQ,P02Int,FALLING_EDGE,0); CLKPWR ->clkpwr_p01_er = CLKPWR_INTSRC_GPIO_01_BIT;// *((long*)0x40004018) |= 2; Int_enable(IRQ_GPIO_01); Int_enable(IRQ_P0_P1_IRQ); MIC->er |= (1<<(IRQ_SUB2IRQ)); //~^ pTimer->tcr = TIMER_CNTR_TCR_EN;//timer_ioctl(timer0dev, TMR_ENABLE, 1); //~^ int_enable(IRQ_TIMER0); }