static void
spi_gpio_set(uint32_t *base, uint32_t pin, uint32_t val)
{
uint32_t mask, dat;
uint32_t *addr = (base + S3C2410_GPDAT(pin));
mask = 1 << S3C2410_GPIO_OFFSET(pin);
dat = (*addr & ~mask) | (val << S3C2410_GPIO_OFFSET(pin));
dprintf("%s: writing 0x%lx to 0x%lx\n", __func__, dat, (uint32_t)addr);
*addr = dat;
}
unsigned int s3c2410_gpio_getcfg(unsigned int pin)
{
void __iomem *base = S3C2410_GPIO_BASE(pin);
unsigned long mask;
if (pin < S3C2410_GPIO_BANKB) {
mask = 1 << S3C2410_GPIO_OFFSET(pin);
} else {
mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
}
return __raw_readl(base) & mask;
}
int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
{
void __iomem *base = S3C24XX_GPIO_BASE(pin);
unsigned long offs = S3C2410_GPIO_OFFSET(pin);
unsigned long flags;
unsigned long slpcon;
offs *= 2;
if (pin < S3C2410_GPIO_BANKB)
return -EINVAL;
if (pin >= S3C2410_GPIO_BANKF &&
pin <= S3C2410_GPIO_BANKG)
return -EINVAL;
if (pin > (S3C2410_GPIO_BANKH + 32))
return -EINVAL;
local_irq_save(flags);
slpcon = __raw_readl(base + 0x0C);
slpcon &= ~(3 << offs);
slpcon |= state << offs;
__raw_writel(slpcon, base + 0x0C);
local_irq_restore(flags);
return 0;
}
unsigned int s3c2410_gpio_getpin(unsigned int pin)
{
void __iomem *base = S3C2410_GPIO_BASE(pin);
unsigned long offs = S3C2410_GPIO_OFFSET(pin);
return __raw_readl(base + 0x04) & (1<< offs);
}
void gta02_gpb_setpin(unsigned int pin, unsigned to)
{
void __iomem *base = S3C24XX_GPIO_BASE(S3C2410_GPB0);
unsigned long offset = S3C2410_GPIO_OFFSET(pin);
unsigned long flags;
unsigned long dat;
BUG_ON(base != S3C24XX_GPIO_BASE(pin));
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
/* Add the shadow values */
dat &= ~gpb_mask;
dat |= gpb_state;
/* Do the operation like s3c2410_gpio_setpin */
dat &= ~(1L << offset);
dat |= to << offset;
/* Update the shadow state */
if ((1L << offset) & gpb_mask)
set_shadow_gpio(offset, to);
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
}
void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
{
void __iomem *base = S3C24XX_GPIO_BASE(pin);
unsigned long mask;
unsigned long con;
unsigned long flags;
if (pin < S3C2410_GPIO_BANKB) {
mask = 1 << S3C2410_GPIO_OFFSET(pin);
} else {
mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
}
switch (function) {
case S3C2410_GPIO_LEAVE:
mask = 0;
function = 0;
break;
case S3C2410_GPIO_INPUT:
case S3C2410_GPIO_OUTPUT:
case S3C2410_GPIO_SFN2:
case S3C2410_GPIO_SFN3:
if (pin < S3C2410_GPIO_BANKB) {
function -= 1;
function &= 1;
function <<= S3C2410_GPIO_OFFSET(pin);
} else {
function &= 3;
function <<= S3C2410_GPIO_OFFSET(pin)*2;
}
}
/* modify the specified register wwith IRQs off */
local_irq_save(flags);
con = __raw_readl(base + 0x00);
con &= ~mask;
con |= function;
__raw_writel(con, base + 0x00);
local_irq_restore(flags);
}
void gta02_gpb_add_shadow_gpio(unsigned int gpio)
{
unsigned long offset = S3C2410_GPIO_OFFSET(gpio);
unsigned long flags;
local_irq_save(flags);
gpb_mask |= 1L << offset;
local_irq_restore(flags);
}
unsigned int s3c2410_gpio_getcfg(unsigned int pin)
{
void __iomem *base = S3C24XX_GPIO_BASE(pin);
unsigned long val = __raw_readl(base);
if (pin < S3C2410_GPIO_BANKB) {
val >>= S3C2410_GPIO_OFFSET(pin);
val &= 1;
val += 1;
} else {
static void
spi_gpio_cfg(uint32_t *base, uint32_t pin, uint32_t func)
{
uint32_t mask, cfg;
uint32_t *addr = (base + S3C2410_GPCON(pin));
mask = 3 << S3C2410_GPIO_OFFSET(pin) * 2;
cfg = (*addr & ~mask) | func;
dprintf("%s: writing 0x%lx to 0x%lx\n", __func__, cfg, (uint32_t)addr);
*addr = cfg;
}
void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
{
void __iomem *base = S3C2410_GPIO_BASE(pin);
unsigned long offs = S3C2410_GPIO_OFFSET(pin);
unsigned long flags;
unsigned long dat;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offs);
dat |= to << offs;
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
}
void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
{
void __iomem *base = S3C2410_GPIO_BASE(pin);
unsigned long offs = S3C2410_GPIO_OFFSET(pin);
unsigned long flags;
unsigned long up;
if (pin < S3C2410_GPIO_BANKB)
return;
local_irq_save(flags);
up = __raw_readl(base + 0x08);
up &= ~(1L << offs);
up |= to << offs;
__raw_writel(up, base + 0x08);
local_irq_restore(flags);
}
static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
{
unsigned long irqstate;
unsigned long pinstate;
int irq = s3c2410_gpio_getirq(pin);
if (irqoffs < 4)
irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
else
irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
pinstate = s3c2410_gpio_getcfg(pin);
pinstate >>= S3C2410_GPIO_OFFSET(pin)*2;
if (!irqstate) {
if (pinstate == 0x02)
DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
} else {
if (pinstate == 0x02) {
DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
s3c2410_gpio_cfgpin(pin, 0x00);
}
}
}
