.regs = {
.lcdcon1 = S3C2410_LCDCON1_TFT16BPP | \
S3C2410_LCDCON1_TFT | \
S3C2410_LCDCON1_CLKVAL(0x04),
.lcdcon2 = S3C2410_LCDCON2_VBPD(1) | \
S3C2410_LCDCON2_LINEVAL(319) | \
S3C2410_LCDCON2_VFPD(5) | \
S3C2410_LCDCON2_VSPW(1),
.lcdcon3 = S3C2410_LCDCON3_HBPD(36) | \
S3C2410_LCDCON3_HOZVAL(239) | \
S3C2410_LCDCON3_HFPD(19),
.lcdcon4 = S3C2410_LCDCON4_MVAL(13) | \
S3C2410_LCDCON4_HSPW(5),
.lcdcon5 = S3C2410_LCDCON5_FRM565 |
S3C2410_LCDCON5_INVVLINE |
S3C2410_LCDCON5_INVVFRAME |
S3C2410_LCDCON5_PWREN |
S3C2410_LCDCON5_HWSWP,
},
.gpccon = 0xaaaaaaaa,
.gpccon_mask = 0xffffffff,
.gpcup = 0xffffffff,
.gpcup_mask = 0xffffffff,
.gpdcon = 0xaaaaaaaa,
.gpdcon_mask = 0xffffffff,
.regs = {
.lcdcon1 = S3C2410_LCDCON1_TFT16BPP | \
S3C2410_LCDCON1_TFT | \
S3C2410_LCDCON1_CLKVAL(0x0C),
.lcdcon2 = S3C2410_LCDCON2_VBPD(5) | \
S3C2410_LCDCON2_LINEVAL(319) | \
S3C2410_LCDCON2_VFPD(6) | \
S3C2410_LCDCON2_VSPW(2),
.lcdcon3 = S3C2410_LCDCON3_HBPD(35) | \
S3C2410_LCDCON3_HOZVAL(239) | \
S3C2410_LCDCON3_HFPD(35),
.lcdcon4 = S3C2410_LCDCON4_MVAL(0) | \
S3C2410_LCDCON4_HSPW(7),
.lcdcon5 = S3C2410_LCDCON5_INVVLINE |
S3C2410_LCDCON5_FRM565 |
S3C2410_LCDCON5_HWSWP,
},
.lpcsel = 0xf82,
.gpccon = 0xaa955699,
.gpccon_mask = 0xffc003cc,
.gpcup = 0x0000ffff,
.gpcup_mask = 0xffffffff,
.gpdcon = 0xaa95aaa1,
.gpdcon_mask = 0xffc0fff0,
.oversampling_shift = 2,
};
/* LCD driver info */
//===================================================================
// NEC LCD parameter: add by lili <bit.lili@gmail>
//===================================================================
#if defined(CONFIG_FB_S3C2410_240X320_NEC)
static struct s3c2410fb_mach_info bit2440_lcdcfg __initdata = {
.regs = {
.lcdcon1 = S3C2410_LCDCON1_TFT16BPP |S3C2410_LCDCON1_TFT |S3C2410_LCDCON1_CLKVAL(0x04),
.lcdcon2 = S3C2410_LCDCON2_VBPD(1) |S3C2410_LCDCON2_VFPD(5) |S3C2410_LCDCON2_VSPW(1),
.lcdcon3 = S3C2410_LCDCON3_HBPD(13) |S3C2410_LCDCON3_HFPD(15),
.lcdcon4 = S3C2410_LCDCON4_MVAL(13) |S3C2410_LCDCON4_HSPW(5),
.lcdcon5 = S3C2410_LCDCON5_FRM565 |S3C2410_LCDCON5_INVVLINE |S3C2410_LCDCON5_INVVFRAME |S3C2410_LCDCON5_PWREN |S3C2410_LCDCON5_HWSWP,
},
.lpcsel = 0xf82,
.gpccon = 0xaa955699,
.gpccon_mask = 0xffc003cc,
.gpcup = 0x0000ffff,
.gpcup_mask = 0xffffffff,
.gpdcon = 0xaa95aaa1,
.gpdcon_mask = 0xffc0fff0,
.gpdup = 0x0000faff,
.gpdup_mask = 0xffffffff,
.lcdcon1 = S3C2410_LCDCON1_TFT16BPP | S3C2410_LCDCON1_TFT | S3C2410_LCDCON1_CLKVAL(0x04), .lcdcon2 = S3C2410_LCDCON2_VBPD(7) | S3C2410_LCDCON2_LINEVAL(319) | S3C2410_LCDCON2_VFPD(6) | S3C2410_LCDCON2_VSPW(3), .lcdcon3 = S3C2410_LCDCON3_HBPD(19) | S3C2410_LCDCON3_HOZVAL(239) | S3C2410_LCDCON3_HFPD(7), .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | S3C2410_LCDCON4_HSPW(3), .lcdcon5 = S3C2410_LCDCON5_FRM565 | S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVFRAME | S3C2410_LCDCON5_PWREN | S3C2410_LCDCON5_HWSWP, }, #if 0 /* currently setup by downloader */ .gpccon = 0xaa940659, .gpccon_mask = 0xffffffff, .gpcup = 0x0000ffff, .gpcup_mask = 0xffffffff, .gpdcon = 0xaa84aaa0,
static void s3c2410fb_activate_var(struct s3c2410fb_info *fbi,
struct fb_var_screeninfo *var)
{
int hs;
fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT;
dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
fbi->regs.lcdcon1 |= fbi->mach_info->type;
if (fbi->mach_info->type == S3C2410_LCDCON1_TFT)
switch (var->bits_per_pixel) {
case 1:
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
break;
case 2:
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
break;
case 4:
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
break;
case 8:
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
break;
case 16:
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
break;
default:
/* invalid pixel depth */
dev_err(fbi->dev, "invalid bpp %d\n", var->bits_per_pixel);
}
else
switch (var->bits_per_pixel) {
case 1:
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
break;
case 2:
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
break;
case 4:
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
break;
case 8:
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
break;
case 12:
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
break;
default:
/* invalid pixel depth */
dev_err(fbi->dev, "invalid bpp %d\n", var->bits_per_pixel);
}
/* check to see if we need to update sync/borders */
if (!fbi->mach_info->fixed_syncs) {
dprintk("setting vert: up=%d, low=%d, sync=%d\n",
var->upper_margin, var->lower_margin,
var->vsync_len);
dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
var->left_margin, var->right_margin,
var->hsync_len);
fbi->regs.lcdcon2 =
S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
fbi->regs.lcdcon3 =
S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
S3C2410_LCDCON3_HFPD(var->left_margin - 1);
fbi->regs.lcdcon4 &= ~S3C2410_LCDCON4_HSPW(0xff);
fbi->regs.lcdcon4 |= S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
}
/* update X/Y info */
fbi->regs.lcdcon2 &= ~S3C2410_LCDCON2_LINEVAL(0x3ff);
fbi->regs.lcdcon2 |= S3C2410_LCDCON2_LINEVAL(var->yres - 1);
switch(fbi->mach_info->type) {
case S3C2410_LCDCON1_DSCAN4:
case S3C2410_LCDCON1_STN8:
hs = var->xres / 8;
break;
case S3C2410_LCDCON1_STN4:
hs = var->xres / 4;
break;
default:
case S3C2410_LCDCON1_TFT:
hs = var->xres;
break;
}
/* Special cases : STN color displays */
if ( ((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN8BPP) \
|| ((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN12BPP) ) {
hs = hs * 3;
}
fbi->regs.lcdcon3 &= ~S3C2410_LCDCON3_HOZVAL(0x7ff);
fbi->regs.lcdcon3 |= S3C2410_LCDCON3_HOZVAL(hs - 1);
if (var->pixclock > 0) {
int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
if (fbi->mach_info->type == S3C2410_LCDCON1_TFT) {
clkdiv = (clkdiv / 2) -1;
if (clkdiv < 0)
clkdiv = 0;
}
else {
clkdiv = (clkdiv / 2);
if (clkdiv < 2)
clkdiv = 2;
}
fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
}
/* write new registers */
dprintk("new register set:\n");
dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1);
writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
/* set lcd address pointers */
s3c2410fb_set_lcdaddr(fbi);
writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
}