unsigned long long notrace sched_clock(void)
{
u32 cyc;
unsigned long offset = 0;
switch (timer_source.source_id) {
case S5P_PWM0:
case S5P_PWM1:
case S5P_PWM2:
case S5P_PWM3:
offset = (timer_source.source_id * 0x0c) + 0x14;
break;
case S5P_PWM4:
offset = 0x40;
break;
default:
printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
return 0;
}
cyc = ~__raw_readl(S3C_TIMERREG(offset));
return cyc_to_sched_clock(&cd, cyc, (u32)~0);
}
static void __iomem *s5p_timer_reg(void)
{
unsigned long offset = 0;
switch (timer_source.source_id) {
case S5P_PWM0:
case S5P_PWM1:
case S5P_PWM2:
case S5P_PWM3:
offset = (timer_source.source_id * 0x0c) + 0x14;
break;
case S5P_PWM4:
offset = 0x40;
break;
default:
printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
return NULL;
}
return S3C_TIMERREG(offset);
}
static cycle_t s5p_timer_read(struct clocksource *cs)
{
unsigned long offset = 0;
switch (timer_source.source_id) {
case S5P_PWM0:
case S5P_PWM1:
case S5P_PWM2:
case S5P_PWM3:
offset = (timer_source.source_id * 0x0c) + 0x14;
break;
case S5P_PWM4:
offset = 0x40;
break;
default:
printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
return 0;
}
return (cycle_t) ~__raw_readl(S3C_TIMERREG(offset));
}
static cycle_t sec_sched_timer_read(void)
{
return (cycle_t)~__raw_readl(S3C_TIMERREG(0x2c));
}
static cycle_t sec_sched_timer_read(void)
{
return (cycle_t)~__raw_readl(S3C_TIMERREG(0x38)); // timer3 observ. reg
}
static cycle_t s5pv310_pwm4_read(struct clocksource *cs)
{
return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
}
static cycle_t sec_sched_timer_read(void)
{
return (cycle_t)~__raw_readl(S3C_TIMERREG(0x38)); /* timer 3 observation register */
}
