void s3c6410_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) { unsigned int gpio; switch (width) { /* Channel 2 supports 4 and 8-bit bus width */ case 8: /* Set all the necessary GPIO function and pull up/down */ for (gpio = S5PC11X_GPG3(3); gpio <= S5PC11X_GPG3(6); gpio++) { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); } writel(0x3fc0, S5PC11X_GPG3DRV); case 0: case 1: case 4: /* Set all the necessary GPIO function and pull up/down */ for (gpio = S5PC11X_GPG2(0); gpio <= S5PC11X_GPG2(6); gpio++) { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); } writel(0x3fff, S5PC11X_GPG2DRV); /* Chip detect pin Pull up*/ s3c_gpio_setpull(S5PC11X_GPG2(2), S3C_GPIO_PULL_UP); break; default: printk(KERN_ERR "Wrong SD/MMC bus width : %d\n", width); } }
.ngpio = S5PC11X_GPIO_G0_NR, .label = "GPG0", }, }, { .base = S5PC11X_GPG1_BASE, .config = &gpio_cfg, .chip = { .base = S5PC11X_GPG1(0), .ngpio = S5PC11X_GPIO_G1_NR, .label = "GPG1", }, }, { .base = S5PC11X_GPG2_BASE, .config = &gpio_cfg, .chip = { .base = S5PC11X_GPG2(0), .ngpio = S5PC11X_GPIO_G2_NR, .label = "GPG2", }, }, { .base = S5PC11X_GPG3_BASE, .config = &gpio_cfg, .chip = { .base = S5PC11X_GPG3(0), .ngpio = S5PC11X_GPIO_G3_NR, .label = "GPG3", }, }, { .base = S5PC11X_GPH0_BASE, .config = &gpio_cfg_noint, .chip = {
.modalias = "mmc_spi", /* MMC SPI */ .mode = SPI_MODE_0, /* CPOL=0, CPHA=0 */ .max_speed_hz = 400000, /* Connected to SPI-2 as 1st Slave */ .bus_num = 2, .irq = IRQ_SPI2, .chip_select = 0, }, #endif #endif }; #if defined(CONFIG_MMC_SPI_GPIO) #define SPI_GPIO_ID 2 struct spi_gpio_platform_data s3c_spigpio_pdata = { .sck = S5PC11X_GPG2(0), .miso = S5PC11X_GPG2(2), .mosi = S5PC11X_GPG2(3), .num_chipselect = 1, }; /* Generic GPIO Bitbanging contoller */ struct platform_device s3c_device_spi_bitbang = { .name = "spi_gpio", .id = SPI_GPIO_ID, .dev = { .platform_data = &s3c_spigpio_pdata, } }; #endif