static int gpio_configure(void) { int ret; printk("%s()\n", __func__); ret = gpio_request(S5PC1XX_GPH1(1), "GPH1"); if (ret) { printk("%s: gpio(GPH1(2) request error: %d\n", __func__, ret); } else { s3c_gpio_cfgpin(S5PC1XX_GPH1(1), S5PC1XX_GPH1_2_WAKEUP_INT_10); s3c_gpio_setpull(S5PC1XX_GPH1(1), S3C_GPIO_PULL_NONE); } ret = gpio_request(S5PC1XX_GPH3(7), "GPH3"); if (ret) { printk("%s: gpio(GPH3(7) request error: %d\n", __func__, ret); } else { s3c_gpio_cfgpin(S5PC1XX_GPH3(7), S5PC1XX_GPH3_7_WAKEUP_INT_31); s3c_gpio_setpull(S5PC1XX_GPH3(7), S3C_GPIO_PULL_NONE); } ret = gpio_request(S5PC1XX_GPG1(0), "GPG1"); if (ret) { printk("%s: gpio(GPG1(0) request error: %d\n", __func__, ret); } else { s3c_gpio_cfgpin(S5PC1XX_GPG1(0), S5PC1XX_GPG1_0_GPIO_INT12_0); s3c_gpio_setpull(S5PC1XX_GPG1(0), S3C_GPIO_PULL_NONE); } ret = gpio_request(S5PC1XX_GPA1(1), "GPA1"); if (ret) { printk("%s: gpio(GPA1(1) request error: %d\n", __func__, ret); } else { s3c_gpio_cfgpin(S5PC1XX_GPA1(1), S5PC1XX_GPA1_1_GPIO_INT1_1); s3c_gpio_setpull(S5PC1XX_GPA1(1), S3C_GPIO_PULL_NONE); } ret = gpio_request(S5PC1XX_GPA1(0), "GPA1"); if (ret) { printk("%s: gpio(GPA1(0) request error: %d\n", __func__, ret); } else { s3c_gpio_cfgpin(S5PC1XX_GPA1(0), S5PC1XX_GPA1_0_GPIO_INT1_0); s3c_gpio_setpull(S5PC1XX_GPA1(0), S3C_GPIO_PULL_NONE); } ret = gpio_request(S5PC1XX_GPB(0), "GPB0"); if (ret) { printk("%s: gpio(GPB0(0) request error: %d\n", __func__, ret); } else { s3c_gpio_cfgpin(S5PC1XX_GPB(0), S5PC1XX_GPB0_GPIO_INT2_0); s3c_gpio_setpull(S5PC1XX_GPB(0), S3C_GPIO_PULL_NONE); } return 0; }
static int tl2796_reset(struct platform_device *dev) { /* set gpio pin for MLCD_RST to LOW */ gpio_direction_output(S5PC1XX_GPH1(7), 0); udelay(1); /* Shorter than 5 usec */ /* set gpio pin for MLCD_RST to HIGH */ gpio_direction_output(S5PC1XX_GPH1(7), 1); mdelay(10); return 0; }
static int tl2796_power_on(struct platform_device *dev) { /* set gpio data for MLCD_RST to HIGH */ gpio_direction_output(S5PC1XX_GPH1(7), 1); /* set gpio data for MLCD_ON to HIGH */ gpio_direction_output(S5PC1XX_GPJ1(3), 1); mdelay(25); /* set gpio data for MLCD_RST to LOW */ gpio_direction_output(S5PC1XX_GPH1(7), 0); udelay(20); /* set gpio data for MLCD_RST to HIGH */ gpio_direction_output(S5PC1XX_GPH1(7), 1); mdelay(20); return 0; }
static void tl2796_gpio_setup(void) { gpio_request(S5PC1XX_GPH1(7), "MLCD_RST"); gpio_request(S5PC1XX_GPJ1(3), "MLCD_ON"); }
static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) { int offs = eint_offset(irq); int shift; u32 ctrl, mask; u32 newvalue = 0; switch (type) { case IRQ_TYPE_NONE: printk(KERN_WARNING "No edge setting!\n"); break; case IRQ_TYPE_EDGE_RISING: newvalue = S3C2410_EXTINT_RISEEDGE; break; case IRQ_TYPE_EDGE_FALLING: newvalue = S3C2410_EXTINT_FALLEDGE; break; case IRQ_TYPE_EDGE_BOTH: newvalue = S3C2410_EXTINT_BOTHEDGE; break; case IRQ_TYPE_LEVEL_LOW: newvalue = S3C2410_EXTINT_LOWLEV; break; case IRQ_TYPE_LEVEL_HIGH: newvalue = S3C2410_EXTINT_HILEV; break; default: printk(KERN_ERR "No such irq type %d", type); return -1; } shift = (offs & 0x7) * 4; mask = 0x7 << shift; #if 0 int flt_shift; int target_offset; flt_shift = (offs & 0x7)*8; target_offset = flt_shift/32; flt_shift = flt_shift%32; ctrl = __raw_readl((S5PC1XX_EINT30FLTCON0+target_offset)); ctrl &= ~(0xff<<flt_shift); ctrl |= (0x80 | 0x40 | 0x1) << flt_shift; //0x80:filter enable, 0x40:digital filter, 0x1: delay clocks __raw_writel(ctrl, (S5PC1XX_EINT30FLTCON0+target_offset)); #endif ctrl = __raw_readl(S5PC1XX_EINTCON(eint_conf_reg(irq))); ctrl &= ~mask; ctrl |= newvalue << shift; __raw_writel(ctrl, S5PC1XX_EINTCON(eint_conf_reg(irq))); #if defined(CONFIG_CPU_S5PC100) if((0 <= offs) && (offs < 8)) s3c_gpio_cfgpin(S5PC1XX_GPH0(offs&0x7), 0x2<<((offs&0x7)*4)); else if((8 <= offs) && (offs < 16)) s3c_gpio_cfgpin(S5PC1XX_GPH1(offs&0x7), 0x2<<((offs&0x7)*4)); else if((16 <= offs) && (offs < 24)) s3c_gpio_cfgpin(S5PC1XX_GPH2(offs&0x7), 0x2<<((offs&0x7)*4)); else if((24 <= offs) && (offs < 32)) s3c_gpio_cfgpin(S5PC1XX_GPH3(offs&0x7), 0x2<<((offs&0x7)*4)); else printk(KERN_ERR "No such irq number %d", offs); #elif defined(CONFIG_CPU_S5PC110) if((0 <= offs) && (offs < 8)) s3c_gpio_cfgpin(S5PC1XX_GPH0(offs&0x7), 0xf<<((offs&0x7)*4)); else if((8 <= offs) && (offs < 16)) s3c_gpio_cfgpin(S5PC1XX_GPH1(offs&0x7), 0xf<<((offs&0x7)*4)); else if((16 <= offs) && (offs < 24)) s3c_gpio_cfgpin(S5PC1XX_GPH2(offs&0x7), 0xf<<((offs&0x7)*4)); else if((24 <= offs) && (offs < 32)) s3c_gpio_cfgpin(S5PC1XX_GPH3(offs&0x7), 0xf<<((offs&0x7)*4)); else printk(KERN_ERR "No such irq number %d", offs); #endif return 0; }
static int __init s5pc100_leds_init(void) { if (machine_is_smdkc100()) leds_event = s5pc100_leds_event; else return -1; if (machine_is_smdkc100()) { gpio_request(S5PC1XX_GPH1(4), "GPH1"); gpio_direction_output(S5PC1XX_GPH1(4), 1); if(gpio_get_value(S5PC1XX_GPH1(4)) == 0) { printk(KERN_WARNING "LED: can't set GPH1(4) to output mode\n"); } gpio_request(S5PC1XX_GPH1(5), "GPH1"); gpio_direction_output(S5PC1XX_GPH1(5), 1); if(gpio_get_value(S5PC1XX_GPH1(5)) == 0) { printk(KERN_WARNING "LED: can't set GPH1(5) to output mode\n"); } gpio_request(S5PC1XX_GPH1(6), "GPH1"); gpio_direction_output(S5PC1XX_GPH1(6), 1); if(gpio_get_value(S5PC1XX_GPH1(6)) == 0) { printk(KERN_WARNING "LED: can't set GPH1(6) to output mode\n"); } gpio_request(S5PC1XX_GPH1(7), "GPH1"); gpio_direction_output(S5PC1XX_GPH1(7), 1); if(gpio_get_value(S5PC1XX_GPH1(7)) == 0) { printk(KERN_WARNING "LED: can't set GPH1(7) to output mode\n"); } } /* Get irqs */ set_irq_type(IRQ_EINT11, IRQ_TYPE_EDGE_FALLING); s3c_gpio_setpull(S5PC1XX_GPH1(3), S3C_GPIO_PULL_NONE); if (request_irq(IRQ_EINT11, eint11_switch, IRQF_DISABLED, "EINT11", NULL)) { return -EIO; } leds_event(led_start); return 0; }