__MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
"0 to reboot (default 0)");
MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
static struct device *wdt_dev; /* platform device attached to */
static struct resource *wdt_mem;
static struct resource *wdt_irq;
static struct clk *wdt_clock;
static unsigned int wdt_count;
static DEFINE_SPINLOCK(wdt_lock);
static struct sleep_save wdt_save[] = {
SAVE_ITEM(S3C2410_WTCON),
};
/* watchdog control routines */
#define DBG(fmt, ...) \
do { \
if (debug) \
pr_info(fmt, ##__VA_ARGS__); \
} while (0)
/* functions */
static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
{
spin_lock(&wdt_lock);
{ .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
{ .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
{ .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
{ .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
{ .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
{ .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
{ .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
};
static struct sleep_save exynos4210_set_clksrc[] = {
{ .reg = EXYNOS4_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
};
static struct sleep_save exynos4_core_save[] = {
/* GIC side */
SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/dev-sysmmu.h>
#include <mach/exynos-clock.h>
#include <mach/dev-sysmmu.h>
static struct clksrc_clk *sysclks[] = {
/* nothing here yet */
};
#ifdef CONFIG_PM
static struct sleep_save exynos4210_clock_save[] = {
/* CMU side */
SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD1),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_IMAGE_4210),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD1),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIR_4210),
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
SAVE_ITEM(EXYNOS4_CLKDIV_LCD1),
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
SAVE_ITEM(EXYNOS4_CLKSRC_LCD1),
};
static struct sleep_save exynos4210_epll_save[] = {
SAVE_ITEM(EXYNOS4_EPLL_LOCK),
SAVE_ITEM(EXYNOS4_EPLL_CON0),
SAVE_ITEM(EXYNOS4_EPLL_CON1),
};
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/exynos4.h>
#include <plat/pm.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/dev-sysmmu.h>
#include <mach/exynos-clock.h>
#include <mach/dev-sysmmu.h>
#ifdef CONFIG_PM
static struct sleep_save exynos4212_clock_save[] = {
/* CMU side */
SAVE_ITEM(EXYNOS4_DMC_PAUSE_CTRL),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_ISP),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC1),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_IMAGE_4212),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIR_4212),
SAVE_ITEM(EXYNOS4_CLKGATE_BUS_LEFTBUS),
SAVE_ITEM(EXYNOS4_CLKGATE_BUS_IMAGE),
SAVE_ITEM(EXYNOS4_CLKGATE_BUS_RIGHTBUS),
SAVE_ITEM(EXYNOS4_CLKGATE_BUS_PERIR),
SAVE_ITEM(EXYNOS4_CLKGATE_BUS_PERIL),
SAVE_ITEM(EXYNOS4_CLKGATE_BUS_DMC0),
SAVE_ITEM(EXYNOS4_CLKGATE_BUS_DMC1),
SAVE_ITEM(EXYNOS4_CLKGATE_SCLK_DMC),
SAVE_ITEM(EXYNOS4_CLKDIV_CAM1),
SAVE_ITEM(EXYNOS4_CLKDIV_ISP),
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
// MIDAS@SPINLOCK
DEFINE_SPINLOCK(power_gating_lock);
extern void s3c_config_sleep_gpio(void );
/* for external use */
int s5pc11x_pm_eint_registered =0;
unsigned long s5pc1xx_pm_flags;
void __iomem *weint_base;
#define PFX "s5pc11x-pm: "
static struct sleep_save core_save[] = {
/* Clock source */
SAVE_ITEM(S5P_CLK_SRC0),
SAVE_ITEM(S5P_CLK_SRC1),
SAVE_ITEM(S5P_CLK_SRC2),
SAVE_ITEM(S5P_CLK_SRC3),
SAVE_ITEM(S5P_CLK_SRC4),
SAVE_ITEM(S5P_CLK_SRC5),
SAVE_ITEM(S5P_CLK_SRC6),
/* Clock source Mask */
SAVE_ITEM(S5P_CLK_SRC_MASK0),
SAVE_ITEM(S5P_CLK_SRC_MASK1),
/* Clock Divider */
SAVE_ITEM(S5P_CLK_DIV0),
SAVE_ITEM(S5P_CLK_DIV1),
SAVE_ITEM(S5P_CLK_DIV2),
SAVE_ITEM(S5P_CLK_DIV3),
SAVE_ITEM(S5P_CLK_DIV4),
irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM);
if (!state)
s3c_irqwake_intmask |= irqbit;
else
s3c_irqwake_intmask &= ~irqbit;
break;
default:
return -ENOENT;
}
return 0;
}
/* this lot should be really saved by the IRQ code */
/* VICXADDRESSXX initilaization to be needed */
static struct sleep_save irq_save[] = {
SAVE_ITEM(S5PV210_VIC0REG(VIC_INT_SELECT)),
SAVE_ITEM(S5PV210_VIC1REG(VIC_INT_SELECT)),
SAVE_ITEM(S5PV210_VIC2REG(VIC_INT_SELECT)),
SAVE_ITEM(S5PV210_VIC3REG(VIC_INT_SELECT)),
SAVE_ITEM(S5PV210_VIC0REG(VIC_INT_ENABLE)),
SAVE_ITEM(S5PV210_VIC1REG(VIC_INT_ENABLE)),
SAVE_ITEM(S5PV210_VIC2REG(VIC_INT_ENABLE)),
SAVE_ITEM(S5PV210_VIC3REG(VIC_INT_ENABLE)),
SAVE_ITEM(S5PV210_VIC0REG(VIC_INT_SOFT)),
SAVE_ITEM(S5PV210_VIC1REG(VIC_INT_SOFT)),
SAVE_ITEM(S5PV210_VIC2REG(VIC_INT_SOFT)),
SAVE_ITEM(S5PV210_VIC3REG(VIC_INT_SOFT)),
};
static struct sleep_save eint_save[] = {
SAVE_ITEM(S5PV2XX_EINT30CON),
#include <mach/map.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <plat/cpu.h>
#include <plat/pm.h>
/* We handled all the IRQ types in this code, to save having to make several
* small files to handle each different type separately. Having the EINT_GRP
* code here shouldn't be as much bloat as the IRQ table space needed when
* they are enabled. The added benefit is we ensure that these registers are
* in the same state as we suspended.
*/
static struct sleep_save irq_save[] = {
SAVE_ITEM(S3C64XX_PRIORITY),
SAVE_ITEM(S3C64XX_EINT0CON0),
SAVE_ITEM(S3C64XX_EINT0CON1),
SAVE_ITEM(S3C64XX_EINT0FLTCON0),
SAVE_ITEM(S3C64XX_EINT0FLTCON1),
SAVE_ITEM(S3C64XX_EINT0FLTCON2),
SAVE_ITEM(S3C64XX_EINT0FLTCON3),
SAVE_ITEM(S3C64XX_EINT0MASK),
};
static struct irq_grp_save {
u32 fltcon;
u32 con;
u32 mask;
} eint_grp_save[5];
#include <mach/regs-irq.h>
#include <linux/gpio.h>
#include <mach/gpio-bank-eint.h>
#include <mach/gpio-bank-gpioint.h>
#include <asm/mach/time.h>
#include <plat/pm.h>
#if defined CONFIG_S5PV210_VICTORY
#include <mach/victory/irqs.h>
#elif defined CONFIG_S5PV210_ATLAS
#include <mach/atlas/irqs.h>
#endif
#define PFX "s5p pm: "
static struct sleep_save core_save[] = {
/* PLL Control */
SAVE_ITEM(S5P_APLL_CON),
SAVE_ITEM(S5P_MPLL_CON),
SAVE_ITEM(S5P_EPLL_CON),
SAVE_ITEM(S5P_VPLL_CON),
/* Clock source */
SAVE_ITEM(S5P_CLK_SRC0),
SAVE_ITEM(S5P_CLK_SRC1),
SAVE_ITEM(S5P_CLK_SRC2),
SAVE_ITEM(S5P_CLK_SRC3),
SAVE_ITEM(S5P_CLK_SRC4),
SAVE_ITEM(S5P_CLK_SRC5),
SAVE_ITEM(S5P_CLK_SRC6),
/* Clock source Mask */
SAVE_ITEM(S5P_CLK_SRC_MASK0),
SAVE_ITEM(S5P_CLK_SRC_MASK1),
/* Clock Divider */
if (timeout == 0) {
printk(KERN_ERR "config %x: blk power never ready.\n", config);
ret = 1;
goto s3c_wait_blk_pwr_ready_end;
}
timeout--;
mdelay(1);
}
s3c_wait_blk_pwr_ready_end:
return ret;
}
EXPORT_SYMBOL(s3c_wait_blk_pwr_ready);
#endif /* CONFIG_S3C64XX_DOMAIN_GATING */
static struct sleep_save core_save[] = {
SAVE_ITEM(S3C_SDMA_SEL),
SAVE_ITEM(S3C_HCLK_GATE),
SAVE_ITEM(S3C_PCLK_GATE),
SAVE_ITEM(S3C_SCLK_GATE),
SAVE_ITEM(S3C_MEM0_CLK_GATE),
SAVE_ITEM(S3C_CLK_SRC),
SAVE_ITEM(S3C_CLK_DIV0),
SAVE_ITEM(S3C_CLK_DIV1),
SAVE_ITEM(S3C_CLK_DIV2),
SAVE_ITEM(S3C_APLL_CON),
SAVE_ITEM(S3C_MPLL_CON),
SAVE_ITEM(S3C_EPLL_CON0),
SAVE_ITEM(S3C_EPLL_CON1),
SAVE_ITEM(S3C_NORMAL_CFG),
SAVE_ITEM(S3C_AHB_CON0),
};
#include "regs-mem.h"
#define PFX "s3c24xx-pm: "
#ifdef CONFIG_PM_SLEEP
static struct sleep_save core_save[] = {
/* we restore the timings here, with the proviso that the board
* brings the system up in an slower, or equal frequency setting
* to the original system.
*
* if we cannot guarantee this, then things are going to go very
* wrong here, as we modify the refresh and both pll settings.
*/
SAVE_ITEM(S3C2410_BWSCON),
SAVE_ITEM(S3C2410_BANKCON0),
SAVE_ITEM(S3C2410_BANKCON1),
SAVE_ITEM(S3C2410_BANKCON2),
SAVE_ITEM(S3C2410_BANKCON3),
SAVE_ITEM(S3C2410_BANKCON4),
SAVE_ITEM(S3C2410_BANKCON5),
};
#endif
/* s3c_pm_check_resume_pin
*
* check to see if the pin is configured correctly for sleep mode, and
* make any necessary adjustments if it is not
*/
writel(val, S3C_HCLK_GATE);
val = readl(S3C64XX_SPC_BASE);
val &= ~0x3;
val |= (1 << 0);
writel(val, S3C64XX_SPC_BASE);
return 0;
}
#if defined(CONFIG_PM)
static struct sleep_save s3c_lcd_save[] = {
SAVE_ITEM(S3C_VIDCON0),
SAVE_ITEM(S3C_VIDCON1),
SAVE_ITEM(S3C_VIDTCON0),
SAVE_ITEM(S3C_VIDTCON1),
SAVE_ITEM(S3C_VIDTCON2),
SAVE_ITEM(S3C_VIDTCON3),
SAVE_ITEM(S3C_WINCON0),
SAVE_ITEM(S3C_WINCON1),
SAVE_ITEM(S3C_WINCON2),
SAVE_ITEM(S3C_WINCON3),
SAVE_ITEM(S3C_WINCON4),
SAVE_ITEM(S3C_VIDOSD0A),
SAVE_ITEM(S3C_VIDOSD0B),
#define EXYNOS5420_CPU_STATE 0x28
/**
* struct exynos_wkup_irq - PMU IRQ to mask mapping
* @hwirq: Hardware IRQ signal of the PMU
* @mask: Mask in PMU wake-up mask register
*/
struct exynos_wkup_irq {
unsigned int hwirq;
u32 mask;
};
static struct sleep_save exynos_core_save[] = {
/* SROM side */
SAVE_ITEM(S5P_SROM_BW),
SAVE_ITEM(S5P_SROM_BC0),
SAVE_ITEM(S5P_SROM_BC1),
SAVE_ITEM(S5P_SROM_BC2),
SAVE_ITEM(S5P_SROM_BC3),
};
struct exynos_pm_data {
const struct exynos_wkup_irq *wkup_irq;
unsigned int wake_disable_mask;
unsigned int *release_ret_regs;
void (*pm_prepare)(void);
void (*pm_resume_prepare)(void);
void (*pm_resume)(void);
int (*pm_suspend)(void);
/* linux/arch/arm/mach-exynos/clock-4210.c
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - 4210 Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifdef CONFIG_PM
static struct sleep_save exynos4_clock_save_4210[] = {
/* CMU side */
SAVE_ITEM(S5P_CLKSRC_IMAGE),
SAVE_ITEM(S5P_CLKSRC_LCD1),
SAVE_ITEM(S5P_CLKDIV_IMAGE),
SAVE_ITEM(S5P_CLKDIV_LCD1),
SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
};
#endif
static struct clk init_clocks_off_4210[] = {
{
.name = "sataphy",
.id = -1,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
#endif
/* Temporary replacement as PCLK isn't used anyway. */
#if defined CONFIG_CPU_FREQ && defined CONFIG_S3C24XX_DFS_CPUFREQ
cfg->clocks=s3c2412_uart_clocks;
cfg->clocks_size=(sizeof( s3c2412_uart_clocks )/sizeof( s3c2412_uart_clocks[0] ));
#endif
}
s3c24xx_uart_count = count;
}
#ifdef CONFIG_PM
struct sleep_save s3c2412_sleep[] = {
SAVE_ITEM(S3C2412_DSC0),
SAVE_ITEM(S3C2412_DSC1)
};
static int s3c2412_suspend(struct sys_device *dev, pm_message_t state)
{
s3c_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
return 0;
}
static int s3c2412_resume(struct sys_device *dev)
{
s3c_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
return 0;
}
if (!(s3c_irqwake_intallow & irqbit))
return -ENOENT;
printk(KERN_INFO "wake %s for irq %d\n",
state ? "enabled" : "disabled", data->irq);
if (!state)
s3c_irqwake_intmask |= irqbit;
else
s3c_irqwake_intmask &= ~irqbit;
return 0;
}
static struct sleep_save irq_save[] = {
SAVE_ITEM(S3C2410_INTMSK),
SAVE_ITEM(S3C2410_INTSUBMSK),
};
/* the extint values move between the s3c2410/s3c2440 and the s3c2412
* so we use an array to hold them, and to calculate the address of
* the register at run-time
*/
static unsigned long save_extint[3];
static unsigned long save_eintflt[4];
static unsigned long save_eintmask;
int s3c24xx_irq_suspend(void)
{
unsigned int i;
#if DEBUG_WAKEUP_STATUS
#define DEBUG_WAKEUP(fmt,args...) printk(fmt, ##args)
#else
#define DEBUG_WAKEUP(fmt,args...) do {} while(0)
#endif
extern unsigned int PM_STATE_PHY;
extern int call_state;
#define PFX "s5p6442-pm: "
void s5p_config_sleep_gpio(void);
static struct sleep_save core_save[] = {
SAVE_ITEM(S5P_APLL_CON),
SAVE_ITEM(S5P_MPLL_CON),
SAVE_ITEM(S5P_EPLL_CON),
SAVE_ITEM(S5P_VPLL_CON),
SAVE_ITEM(S5P_CLK_SRC0),
SAVE_ITEM(S5P_CLK_SRC1),
SAVE_ITEM(S5P_CLK_SRC2),
SAVE_ITEM(S5P_CLK_SRC3),
SAVE_ITEM(S5P_CLK_SRC4),
SAVE_ITEM(S5P_CLK_SRC5),
SAVE_ITEM(S5P_CLK_SRC6),
SAVE_ITEM(S5P_CLK_SRC_MASK0),
SAVE_ITEM(S5P_CLK_SRC_MASK1),
EXYNOS_COMMON_GPD(exynos3_spd_gsc1, NULL, "pd-gsc1");
#endif
#if defined CONFIG_EXYNOS5_DEV_SCALER || defined CONFIG_DRM_EXYNOS_SC
EXYNOS_COMMON_GPD(exynos3_spd_mscl, NULL, "pd-mscl");
#endif
#ifdef CONFIG_VIDEO_EXYNOS_MIPI_CSIS
EXYNOS_COMMON_GPD(exynos3_spd_csis0, NULL, "pd-csis0");
EXYNOS_COMMON_GPD(exynos3_spd_csis1, NULL, "pd-csis1");
#endif
#ifdef CONFIG_VIDEO_EXYNOS_JPEG_HX
EXYNOS_COMMON_GPD(exynos3_spd_jpeg, NULL, "pd-jpeg");
#endif
EXYNOS_COMMON_GPD(exynos3_pd_isp, EXYNOS3_ISP_CONFIGURATION, "pd-isp");
static struct sleep_save exynos_pd_g3d_clk_save[] = {
SAVE_ITEM(EXYNOS3_CLKGATE_BUS_G3D),
SAVE_ITEM(EXYNOS3_CLKGATE_IP_G3D),
};
static struct sleep_save exynos_pd_mfc_clk_save[] = {
SAVE_ITEM(EXYNOS3_CLKGATE_BUS_MFC),
SAVE_ITEM(EXYNOS3_CLKGATE_IP_MFC),
};
static struct sleep_save exynos_pd_lcd0_clk_save[] = {
SAVE_ITEM(EXYNOS3_CLKSRC_MASK_LCD),
SAVE_ITEM(EXYNOS3_CLKGATE_BUS_LCD),
SAVE_ITEM(EXYNOS3_CLKGATE_SCLK_LCD),
SAVE_ITEM(EXYNOS3_CLKGATE_IP_LCD),
};
#include <asm/mach/time.h>
#include "pm.h"
/* for external use */
unsigned long s3c_pm_flags;
/* cache functions from arch/arm/mm/proc-arm920.S */
extern void arm920_flush_kern_cache_all(void);
#define PFX "s3c24xx-pm: "
static struct sleep_save core_save[] = {
SAVE_ITEM(S3C2410_LOCKTIME),
SAVE_ITEM(S3C2410_CLKCON),
/* we restore the timings here, with the proviso that the board
* brings the system up in an slower, or equal frequency setting
* to the original system.
*
* if we cannot guarantee this, then things are going to go very
* wrong here, as we modify the refresh and both pll settings.
*/
SAVE_ITEM(S3C2410_BWSCON),
SAVE_ITEM(S3C2410_BANKCON0),
SAVE_ITEM(S3C2410_BANKCON1),
SAVE_ITEM(S3C2410_BANKCON2),
SAVE_ITEM(S3C2410_BANKCON3),
irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM);
if (!state)
s3c_irqwake_intmask |= irqbit;
else
s3c_irqwake_intmask &= ~irqbit;
break;
default:
return -ENOENT;
}
return 0;
}
static struct sleep_save eint_save[] = {
#if TO_DO
SAVE_ITEM(S5P_EINT_CON(0)),
SAVE_ITEM(S5P_EINT_CON(1)),
SAVE_ITEM(S5P_EINT_CON(2)),
SAVE_ITEM(S5P_EINT_CON(3)),
SAVE_ITEM(S5P_EINT_FLTCON(0)),
SAVE_ITEM(S5P_EINT_FLTCON(1)),
SAVE_ITEM(S5P_EINT_FLTCON(2)),
SAVE_ITEM(S5P_EINT_FLTCON(3)),
SAVE_ITEM(S5P_EINT_FLTCON(4)),
SAVE_ITEM(S5P_EINT_FLTCON(5)),
SAVE_ITEM(S5P_EINT_FLTCON(6)),
SAVE_ITEM(S5P_EINT_FLTCON(7)),
SAVE_ITEM(S5P_EINT_MASK(0)),
SAVE_ITEM(S5P_EINT_MASK(1)),
input_unregister_device(input_dev);
iounmap(key_base);
kfree(pdev->dev.platform_data);
free_irq(IRQ_KEYPAD, (void *)pdev);
del_timer(&keypad_timer);
printk(DEVICE_NAME " Removed.\n");
return 0;
}
#ifdef CONFIG_PM
static struct sleep_save s3c_keypad_save[] = {
SAVE_ITEM(KEYPAD_ROW_GPIOCON),
SAVE_ITEM(KEYPAD_COL_GPIOCON),
SAVE_ITEM(KEYPAD_ROW_GPIOPUD),
SAVE_ITEM(KEYPAD_COL_GPIOPUD),
};
static unsigned int keyifcon, keyiffc;
static int s3c_keypad_suspend(struct platform_device *dev, pm_message_t state)
{
keyifcon = readl(key_base + S3C_KEYIFCON);
keyiffc = readl(key_base + S3C_KEYIFFC);
s3c6410_pm_do_save(s3c_keypad_save, ARRAY_SIZE(s3c_keypad_save));
//writel(~(0xfffffff), KEYPAD_ROW_GPIOCON);
//writel(~(0xfffffff), KEYPAD_COL_GPIOCON);
{ .reg = S5P_CLKSRC_MAUDIO , .val = 0x00000006, },
#endif
{ .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
{ .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
{ .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
{ .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
{ .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
{ .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
{ .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
{ .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
{ .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
};
static struct sleep_save s5pv310_core_save[] = {
SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
SAVE_ITEM(S5P_EPLL_CON0),
SAVE_ITEM(S5P_EPLL_CON1),
SAVE_ITEM(S5P_VPLL_CON0),
SAVE_ITEM(S5P_VPLL_CON1),
SAVE_ITEM(S5P_CLKSRC_TOP0),
SAVE_ITEM(S5P_CLKSRC_TOP1),
SAVE_ITEM(S5P_CLKSRC_CAM),
SAVE_ITEM(S5P_CLKSRC_MFC),
SAVE_ITEM(S5P_CLKSRC_IMAGE),
SAVE_ITEM(S5P_CLKSRC_LCD0),
SAVE_ITEM(S5P_CLKSRC_LCD1),
SAVE_ITEM(S5P_CLKSRC_MAUDIO),
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/pm.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>
#include <mach/exynos4-clock.h>
#include "common.h"
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4_clock_save[] = {
SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
SAVE_ITEM(S5P_CLKSRC_TOP0),
SAVE_ITEM(S5P_CLKSRC_TOP1),
SAVE_ITEM(S5P_CLKSRC_CAM),
SAVE_ITEM(S5P_CLKSRC_TV),
SAVE_ITEM(S5P_CLKSRC_MFC),
SAVE_ITEM(S5P_CLKSRC_G3D),
SAVE_ITEM(S5P_CLKSRC_LCD0),
SAVE_ITEM(S5P_CLKSRC_MAUDIO),
SAVE_ITEM(S5P_CLKSRC_FSYS),
SAVE_ITEM(S5P_CLKSRC_PERIL0),
SAVE_ITEM(S5P_CLKSRC_PERIL1),
SAVE_ITEM(S5P_CLKDIV_CAM),
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/pm.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include "common.h"
#include "clock-exynos4.h"
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4210_clock_save[] = {
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
};
#endif
static struct clksrc_clk *sysclks[] = {
};
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-irq.h>
#include <asm/mach/time.h>
#include <plat/pm.h>
/* for external use */
unsigned long s3c_pm_flags;
#define PFX "s3c24xx-pm: "
static struct sleep_save core_save[] = {
SAVE_ITEM(S3C2410_LOCKTIME),
SAVE_ITEM(S3C2410_CLKCON),
/* we restore the timings here, with the proviso that the board
* brings the system up in an slower, or equal frequency setting
* to the original system.
*
* if we cannot guarantee this, then things are going to go very
* wrong here, as we modify the refresh and both pll settings.
*/
SAVE_ITEM(S3C2410_BWSCON),
SAVE_ITEM(S3C2410_BANKCON0),
SAVE_ITEM(S3C2410_BANKCON1),
SAVE_ITEM(S3C2410_BANKCON2),
SAVE_ITEM(S3C2410_BANKCON3),
#include <plat/regs-serial.h>
#include <plat/regs-timer.h>
#include <mach/regs-clock.h>
#include <plat/gpio-cfg.h>
#include <mach/regs-mem.h>
#include <mach/regs-irq.h>
#include <linux/gpio.h>
#include <asm/mach/time.h>
#include <plat/pm.h>
#define PFX "s5p pm: "
static struct sleep_save core_save[] = {
/* PLL Control */
SAVE_ITEM(S5P_APLL_CON),
SAVE_ITEM(S5P_MPLL_CON),
SAVE_ITEM(S5P_EPLL_CON),
SAVE_ITEM(S5P_VPLL_CON),
/* Clock source */
SAVE_ITEM(S5P_CLK_SRC0),
SAVE_ITEM(S5P_CLK_SRC1),
SAVE_ITEM(S5P_CLK_SRC2),
SAVE_ITEM(S5P_CLK_SRC3),
SAVE_ITEM(S5P_CLK_SRC4),
SAVE_ITEM(S5P_CLK_SRC5),
SAVE_ITEM(S5P_CLK_SRC6),
/* Clock source Mask */
SAVE_ITEM(S5P_CLK_SRC_MASK0),
SAVE_ITEM(S5P_CLK_SRC_MASK1),
/* Clock Divider */
#include <asm/arch/registers.h>
#include <asm/mach/time.h>
#include "pm-s3c6400.h"
/* cache functions from arch/arm/mm/cache-v6.S */
extern void v6_flush_kern_cache_all(void);
/* for external use */
unsigned long s3c_pm_flags;
#define PFX "s3c-pm: "
static struct sleep_save core_save[] = {
SAVE_ITEM(S3C_SDMA_SEL),
};
/* this lot should be really saved by the IRQ code */
/* VICXADDRESSXX initilaization to be needed */
static struct sleep_save irq_save[] = {
SAVE_ITEM(S3C_VIC0INTSELECT),
SAVE_ITEM(S3C_VIC1INTSELECT),
SAVE_ITEM(S3C_VIC0INTENABLE),
SAVE_ITEM(S3C_VIC1INTENABLE),
SAVE_ITEM(S3C_VIC0SOFTINT),
SAVE_ITEM(S3C_VIC1SOFTINT),
};
static struct sleep_save sromc_save[] = {
SAVE_ITEM(S3C_SROM_BW),
}
static void s3c2412_pm_prepare(void)
{
}
static int s3c2412_pm_add(struct sys_device *sysdev)
{
pm_cpu_prep = s3c2412_pm_prepare;
pm_cpu_sleep = s3c2412_cpu_suspend;
return 0;
}
static struct sleep_save s3c2412_sleep[] = {
SAVE_ITEM(S3C2412_DSC0),
SAVE_ITEM(S3C2412_DSC1),
SAVE_ITEM(S3C2413_GPJDAT),
SAVE_ITEM(S3C2413_GPJCON),
SAVE_ITEM(S3C2413_GPJUP),
/* save the PWRCFG to get back to original sleep method */
SAVE_ITEM(S3C2412_PWRCFG),
/* save the sleep configuration anyway, just in case these
* get damaged during wakeup */
SAVE_ITEM(S3C2412_GPBSLPCON),
SAVE_ITEM(S3C2412_GPCSLPCON),
SAVE_ITEM(S3C2412_GPDSLPCON),
static struct sleep_save core_save[] = {
SAVE_ITEM(S3C_APLL_LOCK),
SAVE_ITEM(S3C_MPLL_LOCK),
SAVE_ITEM(S3C_EPLL_LOCK),
SAVE_ITEM(S3C_CLK_SRC),
SAVE_ITEM(S3C_CLK_DIV0),
SAVE_ITEM(S3C_CLK_DIV1),
SAVE_ITEM(S3C_CLK_DIV2),
SAVE_ITEM(S3C_CLK_OUT),
SAVE_ITEM(S3C_HCLK_GATE),
SAVE_ITEM(S3C_PCLK_GATE),
SAVE_ITEM(S3C_SCLK_GATE),
SAVE_ITEM(S3C_MEM0_GATE),
SAVE_ITEM(S3C_EPLL_CON1),
SAVE_ITEM(S3C_EPLL_CON0),
SAVE_ITEM(S3C64XX_MEM0DRVCON),
SAVE_ITEM(S3C64XX_MEM1DRVCON),
#ifndef CONFIG_CPU_FREQ
SAVE_ITEM(S3C_APLL_CON),
SAVE_ITEM(S3C_MPLL_CON),
#endif
};
return subsys_system_register(&s3c2440_subsys, NULL);
}
core_initcall(s3c2440_core_init);
static int __init s3c2442_core_init(void)
{
return subsys_system_register(&s3c2442_subsys, NULL);
}
core_initcall(s3c2442_core_init);
#ifdef CONFIG_PM
static struct sleep_save s3c244x_sleep[] = {
SAVE_ITEM(S3C2440_DSC0),
SAVE_ITEM(S3C2440_DSC1),
SAVE_ITEM(S3C2440_GPJDAT),
SAVE_ITEM(S3C2440_GPJCON),
SAVE_ITEM(S3C2440_GPJUP)
};
static int s3c244x_suspend(void)
{
s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
return 0;
}
static void s3c244x_resume(void)
{
s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
#endif
static struct sleep_save exynos5_set_clksrc[] = {
{ .reg = EXYNOS5_CLKSRC_MASK_TOP , .val = 0xffffffff, },
{ .reg = EXYNOS5_CLKSRC_MASK_GSCL , .val = 0xffffffff, },
{ .reg = EXYNOS5_CLKSRC_MASK_DISP1_0 , .val = 0xffffffff, },
{ .reg = EXYNOS5_CLKSRC_MASK_MAUDIO , .val = 0xffffffff, },
{ .reg = EXYNOS5_CLKSRC_MASK_FSYS , .val = 0xffffffff, },
{ .reg = EXYNOS5_CLKSRC_MASK_PERIC0 , .val = 0xffffffff, },
{ .reg = EXYNOS5_CLKSRC_MASK_PERIC1 , .val = 0xffffffff, },
{ .reg = EXYNOS5_CLKSRC_MASK_ISP , .val = 0xffffffff, },
};
static struct sleep_save exynos5_core_save[] = {
/* GIC side */
SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x10C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x110),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x30C),
SAVE_ITEM(S5P_VA_GIC_DIST + 0x310),
