/** * \brief Send single buffer data through DMA */ static void _UsartDmaTx(uint32_t dwDestAddr, void *pBuffer, uint16_t wSize) { sXdmad *pDmad = &dmad; /* Setup transfer */ sXdmadCfg xdmadCfg; xdmadCfg.mbr_ubc = wSize; xdmadCfg.mbr_sa = (uint32_t) pBuffer; xdmadCfg.mbr_da = (uint32_t) dwDestAddr; xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | XDMAC_CC_MEMSET_NORMAL_MODE | XDMAC_CC_DSYNC_MEM2PER | XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_BYTE | XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF1 | XDMAC_CC_SAM_INCREMENTED_AM | XDMAC_CC_DAM_FIXED_AM | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(ID_USART, XDMAD_TRANSFER_TX)); xdmadCfg.mbr_bc = 0; XDMAD_ConfigureTransfer(pDmad, usartDmaTxChannel, &xdmadCfg, 0, 0, ( XDMAC_CIE_BIE | XDMAC_CIE_DIE | XDMAC_CIE_FIE | XDMAC_CIE_RBIE | XDMAC_CIE_WBIE | XDMAC_CIE_ROIE)); SCB_CleanDCache_by_Addr((uint32_t *)pBuffer, wSize); XDMAD_StartTransfer(pDmad, usartDmaTxChannel); }
/** * \brief DMA TX callback */ static void _SscTxCallback(uint8_t status, void *pArg) { sXdmad *pDmad = &dmad; Xdmac *pXdmac = pDmad->pXdmacs; /*dummy */ status = status; pArg = pArg; if (numBuffersToSend == 0) { /* End of transmission */ isDacActive = 0; return; } /* Load next buffer */ memory_sync(); XDMAC_SetSourceAddr(pXdmac, sscDmaTxChannel, (uint32_t) buffers[outBufferIndex]); XDMAC_SetMicroblockControl(pXdmac, sscDmaTxChannel, bufferSizes[outBufferIndex]); SCB_CleanDCache_by_Addr((uint32_t *) buffers[outBufferIndex], bufferSizes[outBufferIndex]); outBufferIndex = (outBufferIndex + 1) % BUFFER_NUMBER; numBuffersToSend --; XDMAD_StartTransfer(pDmad, sscDmaTxChannel); }
uint8_t ILI9488_EbiDmaRxTransfer(uint32_t *pRxBuffer, uint32_t wRxSize) { SCB_CleanDCache_by_Addr((uint32_t *)pRxBuffer, wRxSize * 4); _ILI9488_EbiDmaUpdateBuffer(dummyTxBuffer, wRxSize, pRxBuffer, wRxSize); if (XDMAD_StartTransfer(ili9488EbiDma.xdmaD, ili9488EbiDma.ili9488DmaRxChannel)) return ILI9488_ERROR_DMA_TRANSFER; return 0; }
/** * \brief Starts a USART master transfer. This is a non blocking function. It * will return as soon as the transfer is started. * * \param pUSARTD Pointer to a USARTDma instance. * \returns 0 if the transfer has been started successfully; otherwise returns * USARTD_ERROR_LOCK is the driver is in use, or USARTD_ERROR if the command is * not valid. */ uint32_t USARTD_SendData(UsartDma *pUsartd) { /* Start DMA 0(RX) && 1(TX) */ pUsartd->pTxChannel->dmaProgress = 0; SCB_CleanDCache_by_Addr((uint32_t *)pUsartd->pTxChannel->pBuff, pUsartd->pTxChannel->BuffSize); if (XDMAD_StartTransfer(pUsartd->pXdmad, pUsartd->pTxChannel->ChNum)) return USARTD_ERROR_LOCK; return 0; }
DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) { DRESULT res = RES_ERROR; WriteStatus = 0; uint32_t timeout; #if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1) uint32_t alignedAddr; /* the SCB_CleanDCache_by_Addr() requires a 32-Bit aligned address adjust the address and the D-Cache size to clean accordingly. */ alignedAddr = (uint32_t)buff & ~3; SCB_CleanDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr)); #endif if(BSP_SD_WriteBlocks_DMA((uint32_t*)buff, (uint32_t)(sector), count) == MSD_OK) { /* Wait for the Rading process is completed or a timeout occurs */ timeout = HAL_GetTick(); while((WriteStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT)) { } /* incase of a timeout return error */ if (WriteStatus == 0) { res = RES_ERROR; } else { WriteStatus = 0; timeout = HAL_GetTick(); while((HAL_GetTick() - timeout) < SD_TIMEOUT) { if (BSP_SD_GetCardState() == SD_TRANSFER_OK) { res = RES_OK; break; } } } } return res; }
/** * \brief Starts a SPI master transfer. This is a non blocking function. It will * return as soon as the transfer is started. * * \param pSpid Pointer to a Spid instance. * \param pCommand Pointer to the SPI command to execute. * \returns 0 if the transfer has been started successfully; otherwise returns * SPID_ERROR_LOCK is the driver is in use, or SPID_ERROR if the command is not * valid. */ uint32_t SPID_SendCommand(Spid *pSpid, SpidCmd *pCommand) { Spi *pSpiHw = pSpid->pSpiHw; /* Try to get the dataflash semaphore */ if (pSpid->semaphore == 0) return SPID_ERROR_LOCK; pSpid->semaphore--; /* Enable the SPI Peripheral */ PMC_EnablePeripheral (pSpid->spiId); /* SPI chip select */ SPI_ChipSelect (pSpiHw, 1 << pCommand->spiCs); // Initialize the callback pSpid->pCurrentCommand = pCommand; /* Initialize DMA controller using channel 0 for RX, 1 for TX. */ if (_spid_configureDmaChannels(pSpid)) return SPID_ERROR_LOCK; /* Configure and enable interrupt on RC compare */ NVIC_ClearPendingIRQ(XDMAC_IRQn); NVIC_SetPriority(XDMAC_IRQn , 1); NVIC_EnableIRQ(XDMAC_IRQn); if (_spid_configureLinkList(pSpiHw, pSpid->pXdmad, pCommand)) return SPID_ERROR_LOCK; /* Enables the SPI to transfer and receive data. */ SPI_Enable (pSpiHw); SCB_CleanDCache_by_Addr((uint32_t *)pCommand->pTxBuff, pCommand->TxSize); /* Start DMA 0(RX) && 1(TX) */ if (XDMAD_StartTransfer(pSpid->pXdmad, spiDmaRxChannel)) return SPID_ERROR_LOCK; if (XDMAD_StartTransfer(pSpid->pXdmad, spiDmaTxChannel)) return SPID_ERROR_LOCK; return 0; }
/** * \brief Start ILI9488 DMA transfer in SMC mode. * \param pTxBuffer point to Tx buffer address * \param wTxSize Tx buffer size in byte * \returns 0 if the xDMA configuration successfully; otherwise returns * ILI9488_DMA_ERROR_XXX. */ uint8_t ILI9488_EbiDmaTxTransfer(uint16_t *pTxBuffer, uint32_t wTxSize) { _ILI9488_EbiDmaUpdateBuffer(pTxBuffer, wTxSize, 0, 0); //SCB_CleanDCache_by_Addr((uint32_t *)&ili9488EbiDma,sizeof(ili9488EbiDma)); SCB_CleanDCache_by_Addr((uint32_t *)pTxBuffer, wTxSize * 2); if (XDMAD_StartTransfer(ili9488EbiDma.xdmaD, ili9488EbiDma.ili9488DmaTxChannel)) { printf("111"); return ILI9488_ERROR_DMA_TRANSFER; } while (!ili9488DmaCtlInEbiMode.txDoneFlag); ili9488DmaCtlInEbiMode.txDoneFlag = 0; return 0; }
/** * \brief Start DMA sending/waiting data. */ static void _SscDma(volatile uint32_t *pReg, uint32_t dmaChannel, void *pBuffer, uint16_t wSize) { sXdmad *pDmad = &dmad; sXdmadCfg xdmadCfg; xdmadCfg.mbr_ubc = wSize; xdmadCfg.mbr_sa = (uint32_t) pBuffer; xdmadCfg.mbr_da = (uint32_t) pReg; xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | XDMAC_CC_MBSIZE_SINGLE | XDMAC_CC_DSYNC_MEM2PER | XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_HALFWORD | XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF1 | XDMAC_CC_SAM_INCREMENTED_AM | XDMAC_CC_DAM_FIXED_AM | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( ID_SSC, XDMAD_TRANSFER_TX)); xdmadCfg.mbr_bc = 0; xdmadCfg.mbr_ds = 0; xdmadCfg.mbr_sus = 0; xdmadCfg.mbr_dus = 0; memory_sync(); XDMAD_ConfigureTransfer(pDmad, dmaChannel, &xdmadCfg, 0, 0, ( XDMAC_CIE_BIE | XDMAC_CIE_DIE | XDMAC_CIE_FIE | XDMAC_CIE_RBIE | XDMAC_CIE_WBIE | XDMAC_CIE_ROIE)); SCB_CleanDCache_by_Addr((uint32_t *)pBuffer, wSize); XDMAD_StartTransfer(pDmad, dmaChannel); SSC_EnableTransmitter(SSC); }
/** * \brief Start USART sending data. */ static void _DmaUsartTx(void) { sXdmadCfg xdmadCfg; xdmadCfg.mbr_ubc = BUFFER_SIZE; xdmadCfg.mbr_sa = (uint32_t)Buffer; xdmadCfg.mbr_da = (uint32_t)&USART->US_THR; xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | XDMAC_CC_MBSIZE_SINGLE | XDMAC_CC_DSYNC_MEM2PER | XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_BYTE | XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF1 | XDMAC_CC_SAM_INCREMENTED_AM | XDMAC_CC_DAM_FIXED_AM | XDMAC_CC_PERID( XDMAIF_Get_ChannelNumber(ID_USART, XDMAD_TRANSFER_TX) ); xdmadCfg.mbr_bc = 0; xdmadCfg.mbr_ds = 0; xdmadCfg.mbr_sus = 0; xdmadCfg.mbr_dus = 0; XDMAD_ConfigureTransfer( &dmad, usartDmaTxChannel, &xdmadCfg, 0, 0, XDMAC_CIE_BIE | XDMAC_CIE_DIE | XDMAC_CIE_FIE | XDMAC_CIE_RBIE | XDMAC_CIE_WBIE | XDMAC_CIE_ROIE); SCB_CleanDCache_by_Addr((uint32_t*)Buffer, BUFFER_SIZE); XDMAD_StartTransfer(&dmad, usartDmaTxChannel); }
void checkForBootLoaderRequest(void) { uint32_t bt; __PWR_CLK_ENABLE(); __BKPSRAM_CLK_ENABLE(); HAL_PWR_EnableBkUpAccess(); bt = (*(__IO uint32_t *) (BKPSRAM_BASE + 4)) ; if ( bt == 0xDEADBEEF ) { (*(__IO uint32_t *) (BKPSRAM_BASE + 4)) = 0xCAFEFEED; // Reset our trigger // Backup SRAM is write-back by default, ensure value actually reaches memory // Another solution would be marking BKPSRAM as write-through in Memory Protection Unit settings SCB_CleanDCache_by_Addr((uint32_t *) (BKPSRAM_BASE + 4), sizeof(uint32_t)); void (*SysMemBootJump)(void); __SYSCFG_CLK_ENABLE(); SYSCFG->MEMRMP |= SYSCFG_MEM_BOOT_ADD0 ; uint32_t p = (*((uint32_t *) 0x1ff00000)); __set_MSP(p); //Set the main stack pointer to its defualt values SysMemBootJump = (void (*)(void)) (*((uint32_t *) 0x1ff00004)); // Point the PC to the System Memory reset vector (+4) SysMemBootJump(); while (1); } }
/** * \brief Configure the USART tx DMA source with Linker List mode. * * \param UsartChannel Pointer to USART dma channel * \returns 0 if the dma multibuffer configuration successfully; otherwise returns * USARTD_ERROR_XXX. */ static uint8_t _configureTxDma(UsartDma *pUsart, UsartChannel *pUsartTx) { sXdmadCfg xdmadTxCfg; uint32_t xdmaCndc, xdmaInt, LLI_Size, i; uint8_t *pBuff = 0; Usart *pUsartHwTx = pUsart->pUsartHw; sXdmad *pXdmadTx = pUsart->pXdmad; /* Setup TX Link List */ if (pUsartTx->dmaProgrammingMode < XDMAD_LLI) { /* Number of Data */ xdmadTxCfg.mbr_ubc = pUsartTx->BuffSize; /* Source and Destination address of DMA */ xdmadTxCfg.mbr_sa = (uint32_t)pUsartTx->pBuff; xdmadTxCfg.mbr_da = (uint32_t)&pUsartHwTx->US_THR; /* DMA Channel configuration */ xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | XDMAC_CC_MBSIZE_SIXTEEN | XDMAC_CC_DSYNC_MEM2PER | XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_BYTE | XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF1 | XDMAC_CC_SAM_INCREMENTED_AM | XDMAC_CC_DAM_FIXED_AM | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber (pUsart->usartId, XDMAD_TRANSFER_TX)); xdmadTxCfg.mbr_bc = 0; if (pUsartTx->dmaProgrammingMode == XDMAD_MULTI) xdmadTxCfg.mbr_bc = pUsartTx->dmaBlockSize; xdmadTxCfg.mbr_sus = 0; xdmadTxCfg.mbr_dus = 0; xdmadTxCfg.mbr_ds = 0; xdmaCndc = 0; /* Enable End of Block; Read Bus error; Write Bus Error; Overflow Error interrupt */ xdmaInt = (XDMAC_CIE_BIE | XDMAC_CIE_RBIE | XDMAC_CIE_WBIE | XDMAC_CIE_ROIE); } else if (pUsartTx->dmaProgrammingMode == XDMAD_LLI) { LLI_Size = pUsartTx->dmaBlockSize; pBuff = pUsartTx->pBuff; /* If channel's LLI is already configured and application want to reconfigured it, free before re-allocating memory */ if (pUsartTx->pLLIview != NULL) { free(pUsartTx->pLLIview); pUsartTx->pLLIview = NULL; } pUsartTx->pLLIview = malloc(sizeof(LinkedListDescriporView1) * LLI_Size); if (pUsartTx->pLLIview == NULL) { TRACE_ERROR(" Can not allocate memory to Tx LLI"); return USARTD_ERROR; } xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | XDMAC_CC_MBSIZE_SIXTEEN | XDMAC_CC_DSYNC_MEM2PER | XDMAC_CC_MEMSET_NORMAL_MODE | XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_BYTE | XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF1 | XDMAC_CC_SAM_INCREMENTED_AM | XDMAC_CC_DAM_FIXED_AM | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber (pUsart->usartId, XDMAD_TRANSFER_TX)); xdmadTxCfg.mbr_bc = 0; for (i = 0; i < LLI_Size; i++) { pUsartTx->pLLIview[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 | XDMA_UBC_NSEN_UPDATED | XDMA_UBC_NDEN_UNCHANGED | ((i == LLI_Size - 1) ? ((pUsartTx->dmaRingBuffer) ? XDMA_UBC_NDE_FETCH_EN : 0) : XDMA_UBC_NDE_FETCH_EN) | pUsartTx->BuffSize; pUsartTx->pLLIview[i].mbr_sa = (uint32_t)pBuff; pUsartTx->pLLIview[i].mbr_da = (uint32_t)&pUsartHwTx->US_THR; pUsartTx->pLLIview[i].mbr_nda = (i == (LLI_Size - 1)) ? ((pUsartTx->dmaRingBuffer) ? (uint32_t)pUsartTx->pLLIview : 0) : (uint32_t)&pUsartTx->pLLIview[ i + 1 ]; pBuff += pUsartTx->BuffSize; } SCB_CleanDCache_by_Addr((uint32_t *)(pUsartTx->pLLIview), sizeof(LinkedListDescriporView1)*LLI_Size); xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 | XDMAC_CNDC_NDE_DSCR_FETCH_EN | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED; xdmaInt = ((pUsartTx->dmaRingBuffer) ? XDMAC_CIE_BIE : XDMAC_CIE_LIE); } else { TRACE_ERROR("DmaProgState is incorrect \n\r"); return 1; } if (XDMAD_ConfigureTransfer(pXdmadTx, pUsartTx->ChNum, &xdmadTxCfg, xdmaCndc, (uint32_t)pUsartTx->pLLIview, xdmaInt)) return USARTD_ERROR; return 0; }
/** * \brief Configure the USART Rx DMA Destination with Linker List mode. * * \param UsartChannel Pointer to USART dma channel * \returns 0 if the dma multibuffer configuration successfully; otherwise * returnsUSARTD_ERROR_XXX. */ static uint8_t _configureRxDma(UsartDma *pUsart, UsartChannel *pUsartRx) { sXdmadCfg xdmadRxCfg; uint32_t xdmaCndc, xdmaInt; uint32_t i, LLI_Size; Usart *pUsartHwRx = pUsart->pUsartHw; sXdmad *pXdmadRx = pUsart->pXdmad; uint8_t *pBuff = 0; /* Setup RX Single block */ if (pUsartRx->dmaProgrammingMode < XDMAD_LLI) { xdmadRxCfg.mbr_ubc = pUsartRx->BuffSize; xdmadRxCfg.mbr_da = (uint32_t)pUsartRx->pBuff; xdmadRxCfg.mbr_sa = (uint32_t)&pUsartHwRx->US_RHR; xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | XDMAC_CC_MBSIZE_SIXTEEN | XDMAC_CC_DSYNC_PER2MEM | XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_BYTE | XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF1 | XDMAC_CC_SAM_FIXED_AM | XDMAC_CC_DAM_INCREMENTED_AM | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber (pUsart->usartId, XDMAD_TRANSFER_RX)); xdmadRxCfg.mbr_bc = 0; if (pUsartRx->dmaProgrammingMode == XDMAD_MULTI) xdmadRxCfg.mbr_bc = pUsartRx->dmaBlockSize; xdmadRxCfg.mbr_sus = 0; xdmadRxCfg.mbr_dus = 0; xdmaCndc = 0; xdmaInt = (XDMAC_CIE_BIE | XDMAC_CIE_DIE | XDMAC_CIE_FIE | XDMAC_CIE_RBIE | XDMAC_CIE_WBIE | XDMAC_CIE_ROIE); } else if (pUsartRx->dmaProgrammingMode == XDMAD_LLI) { /* Setup RX Link List */ LLI_Size = pUsartRx->dmaBlockSize; pBuff = pUsartRx->pBuff; if (pUsartRx->pLLIview != NULL) { free(pUsartRx->pLLIview); pUsartRx->pLLIview = NULL; } pUsartRx->pLLIview = malloc(sizeof(LinkedListDescriporView1) * LLI_Size); if (pUsartRx->pLLIview == NULL) { TRACE_ERROR(" Can not allocate memory to Rx LLI"); return USARTD_ERROR; } xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | XDMAC_CC_MBSIZE_SIXTEEN | XDMAC_CC_DSYNC_PER2MEM | XDMAC_CC_MEMSET_NORMAL_MODE | XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_BYTE | XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF1 | XDMAC_CC_SAM_FIXED_AM | XDMAC_CC_DAM_INCREMENTED_AM | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber (pUsart->usartId, XDMAD_TRANSFER_RX)); xdmadRxCfg.mbr_bc = 0; for (i = 0; i < LLI_Size; i++) { pUsartRx->pLLIview[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 | XDMA_UBC_NSEN_UNCHANGED | XDMA_UBC_NDEN_UPDATED | ((i == LLI_Size - 1) ? ( (pUsartRx->dmaRingBuffer) ? XDMA_UBC_NDE_FETCH_EN : 0) : XDMA_UBC_NDE_FETCH_EN) | pUsartRx->BuffSize; pUsartRx->pLLIview[i].mbr_sa = (uint32_t)&pUsartHwRx->US_RHR; pUsartRx->pLLIview[i].mbr_da = (uint32_t)pBuff; pUsartRx->pLLIview[i].mbr_nda = (i == (LLI_Size - 1)) ? ((pUsartRx->dmaRingBuffer) ? (uint32_t)pUsartRx->pLLIview : 0) : (uint32_t)&pUsartRx->pLLIview[ i + 1 ]; pBuff += pUsartRx->BuffSize; } SCB_CleanDCache_by_Addr((uint32_t *)(pUsartRx->pLLIview), sizeof(LinkedListDescriporView1)*LLI_Size); xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 | XDMAC_CNDC_NDE_DSCR_FETCH_EN | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED; xdmaInt = ((pUsartRx->dmaRingBuffer) ? XDMAC_CIE_BIE : XDMAC_CIE_LIE); } else return 1; if (XDMAD_ConfigureTransfer( pXdmadRx, pUsartRx->ChNum, &xdmadRxCfg, xdmaCndc, (uint32_t)pUsartRx->pLLIview, xdmaInt)) return USARTD_ERROR; return 0; }
int main(void) { uint32_t i; uint32_t deviceId; uint8_t ucKey; uint8_t TestPassed = 0; /* Disable watchdog */ WDT_Disable(WDT); /* Output example information */ printf("-- QSPI Serialflash Example %s --\n\r", SOFTPACK_VERSION); printf("-- %s\n\r", BOARD_NAME); printf("-- Compiled: %s %s With %s--\n\r", __DATE__, __TIME__ , COMPILER_NAME); SCB_EnableICache(); SCB_EnableDCache(); TimeTick_Configure(); PIO_Configure(Qspi_pins, PIO_LISTSIZE(Qspi_pins)); ENABLE_PERIPHERAL(ID_QSPI); QSPI_UserMenu(); while (1) { ucKey = DBG_GetChar(); switch (ucKey) { case '1' : S25FL1D_InitFlashInterface(1); TRACE_INFO("QSPI drivers initialized "); /* enable quad mode */ S25FL1D_QuadMode(ENABLE); PeripheralInit = 1; break; case '2' : S25FL1D_InitFlashInterface(0); TRACE_INFO("QSPI Initialized in SPI mode"); S25FL1D_QuadMode(DISABLE); PeripheralInit = 2; break; case '3' : QSPI_UserMenu(); PeripheralInit = 0; break; default: break; } if (PeripheralInit) { while (1) { deviceId = S25FL1D_ReadJedecId(); printf("ID read: Manufacture ID = 0x%x, Device Type = 0x%x, \ Capacity = 0x%x\n\r", (uint8_t)(deviceId), (uint8_t)(deviceId >> 8), (uint8_t)(deviceId >> 16)); break; } /* erase entire chip */ S25FL1D_EraseChip(); /* fill up the buffer*/ _fillupbuffer(TestBuffer, BUFFER_SIZE); printf("Writing buffer to Flash memory...... \n\r"); /* write the buffer to flash memory */ for (i = 0; i < 0x200000; ) { S25FL1D_Write(TestBuffer, BUFFER_SIZE, i, 0); i += BUFFER_SIZE; } TestPassed = _VerifyData(0, 0x200000, TestBuffer, 0); printf("Erasing a block(64 KB) @ Add 0x10000 \n\r"); S25FL1D_Erase64KBlock(0x10000); memset(TestBuffer, 0xFFFFFF, BUFFER_SIZE); SCB_CleanDCache_by_Addr((uint32_t *)TestBuffer, sizeof(TestBuffer)); TestPassed = _VerifyData(0x10000, (0x10000 + 64 * 1024), TestBuffer, 0); if (TestPassed) printf(" \n\r**** Test Failed ***** \n\r"); else printf(" \n\r### Test Passed ###\n\r"); } PeripheralInit = 0; QSPI_UserMenu(); } }