uint8_t mmc_read_sector(uint32_t sector, uint16_t count, uint8_t* buffer)
{
static int nCount=0, nLED=0;
if (0 == (nCount%128))
{
OEMWriteDebugLED(0, (nLED%4));
nLED++;
}
nCount++;
return (uint8_t)SDHC_READ(sector, (UINT32)count, (UINT32)buffer);
}
static void
obiosdhc_attach(device_t parent, device_t self, void *aux)
{
struct obiosdhc_softc * const sc = device_private(self);
struct obio_attach_args * const oa = aux;
prop_dictionary_t prop = device_properties(self);
uint32_t clkd, stat;
int error, timo, clksft, n;
bool support8bit = false;
const char *transfer_mode = "PIO";
#ifdef TI_AM335X
size_t i;
#endif
prop_dictionary_get_bool(prop, "8bit", &support8bit);
sc->sc.sc_dmat = oa->obio_dmat;
sc->sc.sc_dev = self;
sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS;
sc->sc.sc_flags |= SDHC_FLAG_NO_LED_ON;
sc->sc.sc_flags |= SDHC_FLAG_RSP136_CRC;
sc->sc.sc_flags |= SDHC_FLAG_SINGLE_ONLY;
if (support8bit)
sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE;
#ifdef TI_AM335X
sc->sc.sc_flags |= SDHC_FLAG_WAIT_RESET;
sc->sc.sc_flags &= ~SDHC_FLAG_SINGLE_ONLY;
#endif
#if defined(OMAP_3530)
sc->sc.sc_flags &= ~SDHC_FLAG_SINGLE_ONLY;
#endif
sc->sc.sc_host = sc->sc_hosts;
sc->sc.sc_clkbase = 96000; /* 96MHZ */
if (!prop_dictionary_get_uint32(prop, "clkmask", &sc->sc.sc_clkmsk))
sc->sc.sc_clkmsk = 0x0000ffc0;
sc->sc.sc_vendor_rod = obiosdhc_rod;
sc->sc.sc_vendor_write_protect = obiosdhc_write_protect;
sc->sc.sc_vendor_card_detect = obiosdhc_card_detect;
sc->sc.sc_vendor_bus_clock = obiosdhc_bus_clock;
sc->sc_bst = oa->obio_iot;
clksft = ffs(sc->sc.sc_clkmsk) - 1;
error = bus_space_map(sc->sc_bst, oa->obio_addr, oa->obio_size, 0,
&sc->sc_bsh);
if (error) {
aprint_error_dev(self,
"can't map registers: %d\n", error);
return;
}
bus_space_subregion(sc->sc_bst, sc->sc_bsh, OMAP3_SDMMC_SDHC_OFFSET,
OMAP3_SDMMC_SDHC_SIZE, &sc->sc_sdhc_bsh);
#if NEDMA > 0
if (oa->obio_edmabase != -1) {
cv_init(&sc->sc_edma_cv, "sdhcedma");
sc->sc_edma_fifo = oa->obio_addr +
OMAP3_SDMMC_SDHC_OFFSET + SDHC_DATA;
obiosdhc_edma_init(sc, oa->obio_edmabase);
sc->sc.sc_flags |= SDHC_FLAG_USE_DMA;
sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA;
sc->sc.sc_flags |= SDHC_FLAG_EXTDMA_DMAEN;
sc->sc.sc_flags &= ~SDHC_FLAG_SINGLE_ONLY;
sc->sc.sc_vendor_transfer_data_dma = obiosdhc_edma_xfer_data;
transfer_mode = "EDMA";
}
#endif
aprint_naive("\n");
aprint_normal(": SDHC controller (%s)\n", transfer_mode);
#ifdef TI_AM335X
/* XXX Not really AM335X-specific. */
for (i = 0; i < __arraycount(am335x_sdhc); i++)
if ((oa->obio_addr == am335x_sdhc[i].as_base_addr) &&
(oa->obio_intr == am335x_sdhc[i].as_intr)) {
prcm_module_enable(&am335x_sdhc[i].as_module);
break;
}
KASSERT(i < __arraycount(am335x_sdhc));
#endif
/* XXXXXX: Turn-on regulator via I2C. */
/* XXXXXX: And enable ICLOCK/FCLOCK. */
/* MMCHS Soft reset */
bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG,
SYSCONFIG_SOFTRESET);
timo = 3000000; /* XXXX 3 sec. */
while (timo--) {
if (bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSSTATUS) &
SYSSTATUS_RESETDONE)
break;
delay(1);
}
if (timo == 0)
aprint_error_dev(self, "Soft reset timeout\n");
bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG,
SYSCONFIG_ENAWAKEUP | SYSCONFIG_AUTOIDLE | SYSCONFIG_SIDLEMODE_AUTO |
SYSCONFIG_CLOCKACTIVITY_FCLK | SYSCONFIG_CLOCKACTIVITY_ICLK);
sc->sc_ih = intr_establish(oa->obio_intr, IPL_VM, IST_LEVEL,
sdhc_intr, &sc->sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "failed to establish interrupt %d\n",
oa->obio_intr);
goto fail;
}
error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_sdhc_bsh,
oa->obio_size - OMAP3_SDMMC_SDHC_OFFSET);
if (error != 0) {
aprint_error_dev(self, "couldn't initialize host, error=%d\n",
error);
goto fail;
}
/* Set SDVS 1.8v and DTW 1bit mode */
SDHC_WRITE(sc, SDHC_HOST_CTL,
SDHC_VOLTAGE_1_8V << (SDHC_VOLTAGE_SHIFT + 8));
bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | CON_OD);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_INTCLK_ENABLE |
SDHC_SDCLK_ENABLE);
SDHC_WRITE(sc, SDHC_HOST_CTL,
SDHC_READ(sc, SDHC_HOST_CTL) | SDHC_BUS_POWER << 8);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft);
/*
* 22.6.1.3.1.5 MMCHS Controller INIT Procedure Start
* from 'OMAP35x Applications Processor Technical Reference Manual'.
*
* During the INIT procedure, the MMCHS controller generates 80 clock
* periods. In order to keep the 1ms gap, the MMCHS controller should
* be configured to generate a clock whose frequency is smaller or
* equal to 80 KHz.
*/
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk);
clkd = CLKD(80);
n = 1;
while (clkd & ~(sc->sc.sc_clkmsk >> clksft)) {
clkd >>= 1;
n <<= 1;
}
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) | (clkd << clksft));
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | CON_INIT);
for (; n > 0; n--) {
SDHC_WRITE(sc, SDHC_TRANSFER_MODE, 0x00000000);
timo = 3000000; /* XXXX 3 sec. */
stat = 0;
while (!(stat & SDHC_COMMAND_COMPLETE)) {
stat = SDHC_READ(sc, SDHC_NINTR_STATUS);
if (--timo == 0)
break;
delay(1);
}
if (timo == 0) {
aprint_error_dev(self, "INIT Procedure timeout\n");
break;
}
SDHC_WRITE(sc, SDHC_NINTR_STATUS, stat);
}
bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) & ~CON_INIT);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE);
return;
fail:
if (sc->sc_ih) {
intr_disestablish(sc->sc_ih);
sc->sc_ih = NULL;
}
bus_space_unmap(sc->sc_bst, sc->sc_bsh, oa->obio_size);
}
