static int qrk_aonpt_resume(struct device *dev)
{
SET_INTERRUPT_HANDLER(SOC_AONPT_INTERRUPT, aonpt_ISR);
SOC_UNMASK_INTERRUPTS(SCSS_AON_TIMER_MASK);
MMIO_REG_VAL_FROM_BASE(SCSS_REGISTER_BASE, SCSS_AONPT_STAT);
return 0;
}
DRIVER_API_RC qrk_cxxxx_rtc_set_alarm(struct qrk_cxxxx_rtc_alarm *alarm){
MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_CCR) &= ~QRK_RTC_INTERRUPT_ENABLE;
if(false != alarm->alarm_enable)
{
if(alarm->callback_fn)
{
callback_fn = alarm->callback_fn;
callback_param = alarm->callback_param;
}
MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_EOI);
MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_CMR) = alarm->alarm_rtc_val;
SET_INTERRUPT_HANDLER(SOC_RTC_INTERRUPT, rtc_isr);
/* unmask RTC interrupts to qrk */
MMIO_REG_VAL_FROM_BASE(SCSS_REGISTER_BASE, SCSS_INT_RTC_MASK_OFFSET) =
QRK_INT_RTC_UNMASK_QRK;
MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_CCR) |= QRK_RTC_INTERRUPT_ENABLE;
MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_CCR) &= ~QRK_RTC_INTERRUPT_MASK;
}
else
{
MMIO_REG_VAL_FROM_BASE(SCSS_REGISTER_BASE, SCSS_INT_RTC_MASK_OFFSET) = ~(0);
}
pm_wakelock_release(&rtc_wakelock);
pm_wakelock_acquire(&rtc_wakelock, RTC_WAKELOCK_TIMEOUT);
return DRV_RC_OK;
}
/*---------------------------------------------------------------------------*/
void
irq_init(void)
{
pic_init();
/* Set a 'fake' handler for the Spurious IRQ7 interrupts.
* Refer to http://wiki.osdev.org/PIC .
*/
SET_INTERRUPT_HANDLER(IRQ7_INT, 0, spurious_irq7_handler);
}
/* Driver API */
DRIVER_API_RC soc_i2s_init()
{
int i;
uint32_t reg;
// Prep info struct
for (i = 0; i < I2S_NUM_CHANNELS; i++)
{
i2s_info->en[i] = 0;
i2s_info->cfgd[i] = 0;
i2s_info->cfg[i].cb_done = NULL;
i2s_info->cfg[i].cb_err = NULL;
}
// Enable global clock, use local clock gating per channel instead
set_clock_gate(i2s_info->clk_gate_info, CLK_GATE_ON);
// Setup ISR (and enable)
SET_INTERRUPT_HANDLER(i2s_info->int_vector, i2s_interrupt_handler);
SOC_UNMASK_INTERRUPTS(i2s_info->int_mask);
// Set up control register
reg = MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_CTRL);
reg |= (1 << SOC_I2S_CTRL_TR_CFG_0);
reg &= ~(1 << SOC_I2S_CTRL_TSYNC_LOOP_BACK);
reg &= ~(1 << SOC_I2S_CTRL_RSYNC_LOOP_BACK);
MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_CTRL) = reg;
// Set the watermark levels
MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_TFIFO_CTRL) &= 0xFFFCFFFF;
MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_TFIFO_CTRL) |= (I2S_TFIFO_THR << SOC_I2S_TFIFO_CTRL_TAFULL_THRS);
MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_RFIFO_CTRL) &= 0xFFFCFFFF;
MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_RFIFO_CTRL) |= (I2S_RFIFO_THR << SOC_I2S_RFIFO_CTRL_RAFULL_THRS);
// Enable global interrupt mask
reg = MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_CID_CTRL);
reg |= (1 << SOC_I2S_CID_CTRL_INTREQ_MASK);
MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_CID_CTRL) = reg;
// Initially, have all channels disabled
for (i = 0; i < I2S_NUM_CHANNELS; i++)
{
i2s_disable(i);
}
return DRV_RC_OK;
}
static int comp_init(struct device *dev)
{
int i;
struct cmp_cb *cmp_cb_tmp = (struct cmp_cb*)dev->priv;
for (i = 0; i < CMP_COUNT; i++) {
cmp_cb_tmp[i].cb = NULL;
cmp_cb_tmp[i].cb_data = NULL;
}
dev->priv = cmp_cb_tmp;
#ifdef CONFIG_QUARK
MMIO_REG_VAL_FROM_BASE(SCSS_REGISTER_BASE, INT_COMPARATORS_HOST_MASK) |=
INT_COMPARATORS_MASK;
#elif CONFIG_ARC
MMIO_REG_VAL_FROM_BASE(SCSS_REGISTER_BASE, INT_COMPARATORS_SS_MASK) |=
INT_COMPARATORS_MASK;
#endif
MMIO_REG_VAL(CMP_STAT_CLR) |= INT_COMPARATORS_MASK;
MMIO_REG_VAL(CMP_EN) &= ~(INT_COMPARATORS_MASK);
MMIO_REG_VAL(CMP_PWR) &= ~(INT_COMPARATORS_MASK);
/* enable interrupt trap for comparator driver */
SET_INTERRUPT_HANDLER(SOC_CMP_INTERRUPT, comp_isr);
return 0;
}
