static int tegra_dapm_event_int_mic(struct snd_soc_dapm_widget* w,
struct snd_kcontrol* k, int event)
{
#if 1
int CtrlReg = 0;
struct snd_soc_codec *codec = w->codec;
ASOC_FUNCTION("");
ASOC_DBG("SND_SOC_DAPM_EVENT_ON ? %d\n", SND_SOC_DAPM_EVENT_ON(event));
if (SND_SOC_DAPM_EVENT_ON(event))
{
CtrlReg = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_0);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B06_AIF_ADCR, 0x1);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B07_AIF_ADCL, 0x1);
snd_soc_write(codec, WM8903_AUDIO_INTERFACE_0, CtrlReg);
}
#else
if (s_wired_jack_conf._wired_jack_conf.en_mic_int != -1)
gpio_set_value_cansleep(s_wired_jack_conf._wired_jack_conf.en_mic_int,
SND_SOC_DAPM_EVENT_ON(event) ? 1 : 0);
#endif
return 0;
}
void DIO_vidWritePortData(unsigned char u8PortName,unsigned char u8PortMask,unsigned char u8Data)
{
switch(u8PortName)
{
case PA:
{
SET_REG_VAL(PORTA,u8Data,u8PortMask);
}
break;
case PB:
{
SET_REG_VAL(PORTB,u8Data,u8PortMask);
}
break;
case PC:
{
SET_REG_VAL(PORTC,u8Data,u8PortMask);
}
break;
case PD:
{
SET_REG_VAL(PORTD,u8Data,u8PortMask);
}
break;
}
}
void DIO_vidWritePortDirection(unsigned char u8PortName,unsigned char u8PortMask,unsigned char u8Direction)
{
switch(u8PortName)
{
case PA:
{
SET_REG_VAL(DDRA,u8Direction,u8PortMask);
}
break;
case PB:
{
SET_REG_VAL(DDRB,u8Direction,u8PortMask);
}
break;
case PC:
{
SET_REG_VAL(DDRC,u8Direction,u8PortMask);
}
break;
case PD:
{
SET_REG_VAL(DDRD,u8Direction,u8PortMask);
}
break;
}
}
static int tegra_dapm_event_int_spk(struct snd_soc_dapm_widget* w,
struct snd_kcontrol* k, int event)
{
struct snd_soc_codec *codec = w->codec;
int CtrlReg = 0;
ASOC_FUNCTION("");
ASOC_DBG("SND_SOC_DAPM_EVENT_ON ? %d\n", SND_SOC_DAPM_EVENT_ON(event));
if (s_wired_jack_conf._wired_jack_conf.en_spkr != -1)
{
if (SND_SOC_DAPM_EVENT_ON(event) &&
!s_wired_jack_conf.amp_reg_enabled)
{
s_wired_jack_conf.amp_reg_enabled = 1;
if (!LUNA_SPEAKER_CORRECT_DACL_PHASE_EVT3_1())
{
CtrlReg = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_0);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, WM8903_DACL_DATINV_SHIFT, 0x1);
snd_soc_write(codec, WM8903_AUDIO_INTERFACE_0, CtrlReg);
}
}
else if (!SND_SOC_DAPM_EVENT_ON(event) &&
s_wired_jack_conf.amp_reg_enabled)
{
s_wired_jack_conf.amp_reg_enabled = 0;
if (!LUNA_SPEAKER_CORRECT_DACL_PHASE_EVT3_1())
{
CtrlReg = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_0);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, WM8903_DACL_DATINV_SHIFT, 0x0);
snd_soc_write(codec, WM8903_AUDIO_INTERFACE_0, CtrlReg);
}
}
gpio_set_value_cansleep(s_wired_jack_conf._wired_jack_conf.en_spkr,
SND_SOC_DAPM_EVENT_ON(event) ? 1 : 0);
/* the amplifier needs 100ms to enable. wait 100ms after
* gpio EN triggered */
if (SND_SOC_DAPM_EVENT_ON(event))
msleep(100);
}
return 0;
}
static int tegra_hifi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
struct snd_soc_codec *codec = codec_dai->codec;
struct tegra_audio_data* audio_data = rtd->socdev->codec_data;
enum dac_dap_data_format data_fmt;
int dai_flag = 0, sys_clk;
int err;
ASOC_FUNCTION("");
if (tegra_das_is_port_master(tegra_audio_codec_type_hifi))
dai_flag |= SND_SOC_DAIFMT_CBM_CFM;
else
dai_flag |= SND_SOC_DAIFMT_CBS_CFS;
data_fmt = tegra_das_get_codec_data_fmt(tegra_audio_codec_type_hifi);
/* We are supporting DSP and I2s format for now */
if (data_fmt & dac_dap_data_format_i2s)
dai_flag |= SND_SOC_DAIFMT_I2S;
else
dai_flag |= SND_SOC_DAIFMT_DSP_A;
err = snd_soc_dai_set_fmt(codec_dai, dai_flag);
if (err < 0) {
pr_err("codec_dai fmt not set \n");
return err;
}
err = snd_soc_dai_set_fmt(cpu_dai, dai_flag);
if (err < 0) {
pr_err("cpu_dai fmt not set \n");
return err;
}
sys_clk = clk_get_rate(audio_data->dap_mclk);
err = snd_soc_dai_set_sysclk(codec_dai, 0, sys_clk, SND_SOC_CLOCK_IN);
if (err < 0) {
pr_err("codec_dai clock not set\n");
return err;
}
err = snd_soc_dai_set_sysclk(cpu_dai, 0, sys_clk, SND_SOC_CLOCK_IN);
if (err < 0) {
pr_err("cpu_dai clock not set\n");
return err;
}
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) {
int CtrlReg = 0;
int VolumeCtrlReg = 0;
int SidetoneCtrlReg = 0;
int SideToneAtenuation = 0;
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0, 0X7);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0, 0X7);
/* Mic Bias enable */
CtrlReg = (0x1<<B00_MICBIAS_ENA) | (0x1<<B01_MICDET_ENA);
snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, CtrlReg);
/* Enable DRC */
CtrlReg = snd_soc_read(codec, WM8903_DRC_0);
CtrlReg |= (1<<B15_DRC_ENA);
snd_soc_write(codec, WM8903_DRC_0, CtrlReg);
CtrlReg = LUNA_INTERNAL_MIC_SETTING_R1R2;
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_1, CtrlReg);
CtrlReg = LUNA_EXTERNAL_MIC_SETTING_L2L1;
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_1, CtrlReg);
VolumeCtrlReg = (0x1C << B00_IN_VOL);
/* Mic Setting */
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0,
VolumeCtrlReg);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0,
VolumeCtrlReg);
CtrlReg = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_0);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B06_AIF_ADCR, 0x0);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B07_AIF_ADCL, 0x0);
snd_soc_write(codec, WM8903_AUDIO_INTERFACE_0, CtrlReg);
/* Enable analog inputs */
CtrlReg = (0x1<<B01_INL_ENA) | (0x1<<B00_INR_ENA);
snd_soc_write(codec, WM8903_POWER_MANAGEMENT_0, CtrlReg);
/* ADC Settings */
CtrlReg = snd_soc_read(codec, WM8903_ADC_DIGITAL_0);
CtrlReg |= (0x1<<B04_ADC_HPF_ENA);
snd_soc_write(codec, WM8903_ADC_DIGITAL_0, CtrlReg);
#if 0
SidetoneCtrlReg = 0;
snd_soc_write(codec, R20_SIDETONE_CTRL, SidetoneCtrlReg);
#endif
/* Enable ADC */
CtrlReg = snd_soc_read(codec, WM8903_POWER_MANAGEMENT_6);
CtrlReg |= (0x1<<B00_ADCR_ENA)|(0x1<<B01_ADCL_ENA);
snd_soc_write(codec, WM8903_POWER_MANAGEMENT_6, CtrlReg);
#if 0
SidetoneCtrlReg = (0x1<<2) | (0x2<<0);
SideToneAtenuation = 12 ;
SidetoneCtrlReg |= (SideToneAtenuation<<8)
| (SideToneAtenuation<<4);
snd_soc_write(codec, R20_SIDETONE_CTRL, SidetoneCtrlReg);
#endif
CtrlReg = snd_soc_read(codec, R29_DRC_1);
CtrlReg |= 0x3; /*mic volume 18 db */
snd_soc_write(codec, R29_DRC_1, CtrlReg);
}
return 0;
}
static int tegra_hifi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
struct snd_soc_codec *codec = codec_dai->codec;
struct tegra_audio_data* audio_data = rtd->socdev->codec_data;
enum dac_dap_data_format data_fmt;
int dai_flag = 0, sys_clk;
int err;
int hs_type;
int CtrlReg = 0;
if (tegra_das_is_port_master(tegra_audio_codec_type_hifi))
dai_flag |= SND_SOC_DAIFMT_CBM_CFM;
else
dai_flag |= SND_SOC_DAIFMT_CBS_CFS;
data_fmt = tegra_das_get_codec_data_fmt(tegra_audio_codec_type_hifi);
/* We are supporting DSP and I2s format for now */
if (data_fmt & dac_dap_data_format_i2s)
dai_flag |= SND_SOC_DAIFMT_I2S;
else
dai_flag |= SND_SOC_DAIFMT_DSP_A;
err = snd_soc_dai_set_fmt(codec_dai, dai_flag);
if (err < 0) {
pr_err("codec_dai fmt not set \n");
return err;
}
err = snd_soc_dai_set_fmt(cpu_dai, dai_flag);
if (err < 0) {
pr_err("cpu_dai fmt not set \n");
return err;
}
sys_clk = clk_get_rate(audio_data->dap_mclk);
err = snd_soc_dai_set_sysclk(codec_dai, 0, sys_clk, SND_SOC_CLOCK_IN);
if (err < 0) {
pr_err("codec_dai clock not set\n");
return err;
}
err = snd_soc_dai_set_sysclk(cpu_dai, 0, sys_clk, SND_SOC_CLOCK_IN);
if (err < 0) {
pr_err("cpu_dai clock not set\n");
return err;
}
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) {
int VolumeCtrlReg = 0;
hs_type = check_hs_type();
if(jack_alive && hs_type){
printk("Headset connected, enable external Mic(AMIC)\n");
/* Disable Digital Microphone(DMIC) for audio input function */
CtrlReg = (0x0 << B08_GPIO_FN) |(0x1 << B07_GPIO_DIR) |(0x1 << B05_GPIO_IP_CFG) |(0x1 << B03_GPIO_PD);
snd_soc_write(codec, R74_GPIO_CTRL_1, CtrlReg); /*0x00A8*/
CtrlReg = (0x0 << B08_GPIO_FN) |(0x1 << B07_GPIO_DIR) |(0x1 << B05_GPIO_IP_CFG) |(0x1 << B03_GPIO_PD);
snd_soc_write(codec, R75_GPIO_CTRL_2, CtrlReg); /*0x00A8*/
CtrlReg = (0x0 << B09_DIGMIC);
snd_soc_write(codec, RA4_ADC_DIG_MIC, CtrlReg);/*0x0000*/
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0, 0X7);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0, 0X7);
// Mic Bias enable
CtrlReg = (0x1<<B00_MICBIAS_ENA) | (0x1<<B01_MICDET_ENA);
snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, CtrlReg);
// Enable DRC
CtrlReg = snd_soc_read(codec, WM8903_DRC_0);
CtrlReg |= (1<<B15_DRC_ENA);
snd_soc_write(codec, WM8903_DRC_0, CtrlReg);
// Single Ended Mic
CtrlReg = (0x0<<B06_IN_CM_ENA) |
(0x0<<B00_MODE) | (0x0<<B04_IP_SEL_N)
| (0x1<<B02_IP_SEL_P);
VolumeCtrlReg = (audio_params[EP101].analog_headset_mic_volume << B00_IN_VOL);
// Mic Setting
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_1, CtrlReg);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_1, CtrlReg);
// voulme for single ended mic
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0,
VolumeCtrlReg);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0,
VolumeCtrlReg);
/* Left ADC data on both channels */
CtrlReg = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_0);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B06_AIF_ADCR, 0x0);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B06_AIF_ADCL, 0x0);
snd_soc_write(codec, WM8903_AUDIO_INTERFACE_0, CtrlReg);
}else{
printk("Headset disconnected, enable internal Mic(DMIC)\n");
/* Enable Digital Microphone(DMIC) for audio input function */
CtrlReg = (0x1 << B06_AIFADCR_SRC) |(0x1 << B04_AIFDACR_SRC);
snd_soc_write(codec, WM8903_AUDIO_INTERFACE_0, CtrlReg); /*0x0050*/
CtrlReg = (0x6 << B08_GPIO_FN) |(0x0 << B07_GPIO_DIR) |(0x1 << B05_GPIO_IP_CFG) |(0x1 << B03_GPIO_PD);
snd_soc_write(codec, WM8903_GPIO_CONTROL_1, CtrlReg); /*0x0628*/
CtrlReg = (0x6 << B08_GPIO_FN) |(0x1 << B07_GPIO_DIR) |(0x1 << B05_GPIO_IP_CFG) |(0x1 << B03_GPIO_PD);
snd_soc_write(codec, WM8903_GPIO_CONTROL_2, CtrlReg); /*0x06A8*/
CtrlReg = (0x1 << B09_DIGMIC);
snd_soc_write(codec, WM8903_CLOCK_RATE_TEST_4, CtrlReg);/*0x2A38*/
snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, audio_params[EP101].analog_DMIC_ADC_volume | 0x100); /* ADC Digital volume left: 17.625dB*/
snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, audio_params[EP101].analog_DMIC_ADC_volume | 0x100); /* ADC Digital volume right: 17.625dB*/
}
//--------------------------------------
// Enable analog inputs
CtrlReg = (0x1<<B01_INL_ENA);
snd_soc_write(codec, WM8903_POWER_MANAGEMENT_0, CtrlReg);
// ADC Settings
CtrlReg = snd_soc_read(codec, WM8903_ADC_DIGITAL_0);
CtrlReg |= (0x1<<B04_ADC_HPF_ENA);
snd_soc_write(codec, WM8903_ADC_DIGITAL_0, CtrlReg);
/* Disable sidetone */
CtrlReg = 0;
snd_soc_write(codec, R20_SIDETONE_CTRL, CtrlReg);
// Enable ADC
CtrlReg = snd_soc_read(codec, WM8903_POWER_MANAGEMENT_6);
CtrlReg |= (0x1<<B01_ADCL_ENA);
snd_soc_write(codec, WM8903_POWER_MANAGEMENT_6, CtrlReg);
CtrlReg = snd_soc_read(codec, R29_DRC_1);
CtrlReg |= 0x3; //mic volume 18 db
snd_soc_write(codec, R29_DRC_1, CtrlReg);
}else{
/* Mic Bias disable */
CtrlReg = (0x0<<0) | (0x0<<1);
snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, CtrlReg);
fm34_config_DSP();
}
return 0;
}
static int tegra_hifi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
int err;
#if 0
struct snd_soc_codec *codec = codec_dai->codec;
int CtrlReg = 0;
int VolumeCtrlReg = 0;
int SidetoneCtrlReg = 0;
int SideToneAtenuation = 0;
#endif
err = snd_soc_dai_set_fmt(codec_dai,
SND_SOC_DAIFMT_I2S | \
SND_SOC_DAIFMT_NB_NF | \
SND_SOC_DAIFMT_CBS_CFS);
if (err < 0) {
printk(KERN_ERR "codec_dai fmt not set \n");
return err;
}
err = snd_soc_dai_set_fmt(cpu_dai,
SND_SOC_DAIFMT_I2S | \
SND_SOC_DAIFMT_NB_NF | \
SND_SOC_DAIFMT_CBS_CFS);
if (err < 0) {
printk(KERN_ERR "cpu_dai fmt not set \n");
return err;
}
err = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_MCLK1,
I2S1_CLK, SND_SOC_CLOCK_IN);
if (err < 0) {
printk(KERN_ERR "codec_dai clock not set\n");
return err;
}
err = snd_soc_dai_set_sysclk(cpu_dai, 0, I2S1_CLK, SND_SOC_CLOCK_IN);
if (err < 0) {
printk(KERN_ERR "cpu_dai clock not set\n");
return err;
}
#if 0
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) {
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0, 0X7);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0, 0X7);
// Mic Bias enable
CtrlReg = (0x1<<B00_MICBIAS_ENA) | (0x1<<B01_MICDET_ENA);
snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, CtrlReg);
// Enable DRC
CtrlReg = snd_soc_read(codec, WM8903_DRC_0);
CtrlReg |= (1<<B15_DRC_ENA);
snd_soc_write(codec, WM8903_DRC_0, CtrlReg);
// Single Ended Mic
CtrlReg = (0x0<<B06_IN_CM_ENA) |
(0x0<<B00_MODE) | (0x0<<B04_IP_SEL_N)
| (0x1<<B02_IP_SEL_P);
VolumeCtrlReg = (0x1C << B00_IN_VOL);
// Mic Setting
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_1, CtrlReg);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_1, CtrlReg);
// voulme for single ended mic
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0,
VolumeCtrlReg);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0,
VolumeCtrlReg);
// replicate mic setting on both channels
CtrlReg = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_0);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B06_AIF_ADCR, 0x0);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B06_AIF_ADCL, 0x0);
snd_soc_write(codec, WM8903_AUDIO_INTERFACE_0, CtrlReg);
// Enable analog inputs
CtrlReg = (0x1<<B01_INL_ENA) | (0x1<<B00_INR_ENA);
snd_soc_write(codec, WM8903_POWER_MANAGEMENT_0, CtrlReg);
// ADC Settings
CtrlReg = snd_soc_read(codec, WM8903_ADC_DIGITAL_0);
CtrlReg |= (0x1<<B04_ADC_HPF_ENA);
snd_soc_write(codec, WM8903_ADC_DIGITAL_0, CtrlReg);
SidetoneCtrlReg = 0;
snd_soc_write(codec, R20_SIDETONE_CTRL, SidetoneCtrlReg);
// Enable ADC
CtrlReg = snd_soc_read(codec, WM8903_POWER_MANAGEMENT_6);
CtrlReg |= (0x1<<B00_ADCR_ENA)|(0x1<<B01_ADCL_ENA);
snd_soc_write(codec, WM8903_POWER_MANAGEMENT_6, CtrlReg);
// Enable Sidetone
SidetoneCtrlReg = (0x1<<2) | (0x2<<0);
SideToneAtenuation = 12 ; // sidetone 0 db
SidetoneCtrlReg |= (SideToneAtenuation<<8)
| (SideToneAtenuation<<4);
snd_soc_write(codec, R20_SIDETONE_CTRL, SidetoneCtrlReg);
CtrlReg = snd_soc_read(codec, R29_DRC_1);
CtrlReg |= 0x3; //mic volume 18 db
snd_soc_write(codec, R29_DRC_1, CtrlReg);
}
#endif
return 0;
}
static int tegra_hifi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
struct snd_soc_codec *codec = codec_dai->codec;
struct tegra_audio_data* audio_data = rtd->socdev->codec_data;
enum dac_dap_data_format data_fmt;
int dai_flag = 0, sys_clk;
int err;
//printk(KERN_INFO "####### tegra_hifi_hw_params type:%d\n", substream->stream);
if (tegra_das_is_port_master(tegra_audio_codec_type_hifi))
dai_flag |= SND_SOC_DAIFMT_CBM_CFM;
else
dai_flag |= SND_SOC_DAIFMT_CBS_CFS;
data_fmt = tegra_das_get_codec_data_fmt(tegra_audio_codec_type_hifi);
/* We are supporting DSP and I2s format for now */
if (data_fmt & dac_dap_data_format_i2s)
dai_flag |= SND_SOC_DAIFMT_I2S;
else
dai_flag |= SND_SOC_DAIFMT_DSP_A;
err = snd_soc_dai_set_fmt(codec_dai, dai_flag);
if (err < 0) {
pr_err("codec_dai fmt not set \n");
return err;
}
err = snd_soc_dai_set_fmt(cpu_dai, dai_flag);
if (err < 0) {
pr_err("cpu_dai fmt not set \n");
return err;
}
sys_clk = clk_get_rate(audio_data->dap_mclk);
err = snd_soc_dai_set_sysclk(codec_dai, 0, sys_clk, SND_SOC_CLOCK_IN);
if (err < 0) {
pr_err("codec_dai clock not set\n");
return err;
}
err = snd_soc_dai_set_sysclk(cpu_dai, 0, sys_clk, SND_SOC_CLOCK_IN);
if (err < 0) {
pr_err("cpu_dai clock not set\n");
return err;
}
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) {
int CtrlReg = 0;
int VolumeCtrlReg = 0;
//int SidetoneCtrlReg = 0;
#if 0
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0, 0X7);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0, 0X7);
/* Mic Bias enable */
CtrlReg = (0x1<<B00_MICBIAS_ENA) | (0x1<<B01_MICDET_ENA);
snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, CtrlReg);
/* Enable DRC */
CtrlReg = snd_soc_read(codec, WM8903_DRC_0);
CtrlReg |= (1<<B15_DRC_ENA);
snd_soc_write(codec, WM8903_DRC_0, CtrlReg);
#endif
/* Single Ended Mic */
CtrlReg = (0x1<<B06_IN_CM_ENA) |
(0x0<<B00_MODE) | (0x1<<B04_IP_SEL_N)
| (0x1<<B02_IP_SEL_P);
VolumeCtrlReg = (0x1B << B00_IN_VOL);
/* Mic Setting */
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_1, CtrlReg);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_1, CtrlReg);
/* voulme for single ended mic */
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0,
VolumeCtrlReg);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0,
VolumeCtrlReg);
/* replicate mic setting on both channels */
CtrlReg = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_0);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B06_AIF_ADCR, 0x0);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B06_AIF_ADCL, 0x0);
snd_soc_write(codec, WM8903_AUDIO_INTERFACE_0, CtrlReg);
/* Enable analog inputs */
CtrlReg = (0x1<<B01_INL_ENA) | (0x1<<B00_INR_ENA);
snd_soc_write(codec, WM8903_POWER_MANAGEMENT_0, CtrlReg);
/* ADC Settings */
//CtrlReg = snd_soc_read(codec, WM8903_ADC_DIGITAL_0);
CtrlReg = (0x01<<WM8903_ADC_HPF_CUT_SHIFT) | WM8903_ADC_HPF_ENA;
snd_soc_write(codec, WM8903_ADC_DIGITAL_0, CtrlReg);
//SidetoneCtrlReg = 0;
//snd_soc_write(codec, R20_SIDETONE_CTRL, SidetoneCtrlReg);
/* Enable ADC */
CtrlReg = snd_soc_read(codec, WM8903_POWER_MANAGEMENT_6);
CtrlReg |= (0x1<<B01_ADCL_ENA);
snd_soc_write(codec, WM8903_POWER_MANAGEMENT_6, CtrlReg);
#if 0
CtrlReg = snd_soc_read(codec, R29_DRC_1);
CtrlReg |= 0x3; /*mic volume 18 db */
snd_soc_write(codec, R29_DRC_1, CtrlReg);
#endif
mic_mute_state = 0;
}
return 0;
}
static int tegra_hifi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
struct snd_soc_codec *codec = codec_dai->codec;
struct tegra_audio_data* audio_data = rtd->socdev->codec_data;
enum dac_dap_data_format data_fmt;
int dai_flag = 0, sys_clk;
int err;
if (tegra_das_is_port_master(tegra_audio_codec_type_hifi))
dai_flag |= SND_SOC_DAIFMT_CBM_CFM;
else
dai_flag |= SND_SOC_DAIFMT_CBS_CFS;
data_fmt = tegra_das_get_codec_data_fmt(tegra_audio_codec_type_hifi);
/* We are supporting DSP and I2s format for now */
if (data_fmt & dac_dap_data_format_i2s)
dai_flag |= SND_SOC_DAIFMT_I2S;
else
dai_flag |= SND_SOC_DAIFMT_DSP_A;
err = snd_soc_dai_set_fmt(codec_dai, dai_flag);
if (err < 0) {
pr_err("codec_dai fmt not set \n");
return err;
}
err = snd_soc_dai_set_fmt(cpu_dai, dai_flag);
if (err < 0) {
pr_err("cpu_dai fmt not set \n");
return err;
}
sys_clk = clk_get_rate(audio_data->dap_mclk);
err = snd_soc_dai_set_sysclk(codec_dai, 0, sys_clk, SND_SOC_CLOCK_IN);
if (err < 0) {
pr_err("codec_dai clock not set\n");
return err;
}
err = snd_soc_dai_set_sysclk(cpu_dai, 0, sys_clk, SND_SOC_CLOCK_IN);
if (err < 0) {
pr_err("cpu_dai clock not set\n");
return err;
}
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) {
int CtrlReg = 0;
int VolumeCtrlReg = 0;
int SidetoneCtrlReg = 0;
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0, 0X7);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0, 0X7);
/* Mic Bias enable */
CtrlReg = (0x1<<B00_MICBIAS_ENA) | (0x1<<B01_MICDET_ENA);
snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, CtrlReg);
/* Enable DRC */
CtrlReg = snd_soc_read(codec, WM8903_DRC_0);
CtrlReg |= (1<<B15_DRC_ENA);
snd_soc_write(codec, WM8903_DRC_0, CtrlReg);
/* Single Ended Mic */
#if defined(CONFIG_MACH_ACER_PICASSO) || defined(CONFIG_MACH_ACER_MAYA)
if (wired_jack_state() == 1) {
CtrlReg = (0x0<<B06_IN_CM_ENA) |
(0x0<<B00_MODE) | (0x1<<B04_IP_SEL_N)
| (0x1<<B02_IP_SEL_P);
} else {
CtrlReg = (0x0<<B06_IN_CM_ENA) |
(0x0<<B00_MODE) | (0x0<<B04_IP_SEL_N)
| (0x1<<B02_IP_SEL_P);
}
#elif defined(CONFIG_MACH_ACER_VANGOGH)
if (wired_jack_state() == 1) {
select_mic_input(1);
} else {
select_mic_input(2);
}
CtrlReg = (0x0<<B06_IN_CM_ENA) |
(0x0<<B00_MODE) | (0x0<<B04_IP_SEL_N)
| (0x1<<B02_IP_SEL_P);
#else
CtrlReg = (0x0<<B06_IN_CM_ENA) |
(0x0<<B00_MODE) | (0x0<<B04_IP_SEL_N)
| (0x1<<B02_IP_SEL_P);
#endif
#if defined(CONFIG_MACH_ACER_PICASSO) || defined(CONFIG_MACH_ACER_MAYA) || defined(CONFIG_MACH_ACER_VANGOGH)
VolumeCtrlReg = (0x10 << B00_IN_VOL);
#else
VolumeCtrlReg = (0x1C << B00_IN_VOL);
#endif
/* Mic Setting */
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_1, CtrlReg);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_1, CtrlReg);
/* voulme for single ended mic */
snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0,
VolumeCtrlReg);
snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0,
VolumeCtrlReg);
/* Left ADC data on both channels */
CtrlReg = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_0);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B06_AIF_ADCR, 0x0);
CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B06_AIF_ADCL, 0x0);
snd_soc_write(codec, WM8903_AUDIO_INTERFACE_0, CtrlReg);
/* Enable analog inputs */
#if defined(CONFIG_MACH_ACER_PICASSO) || defined(CONFIG_MACH_ACER_MAYA) || defined(CONFIG_MACH_ACER_VANGOGH)
if (audio_data->isMicMuted)
CtrlReg = (0x0<<B01_INL_ENA);
else
CtrlReg = (0x1<<B01_INL_ENA);
#else
CtrlReg = (0x1<<B01_INL_ENA);
#endif
snd_soc_write(codec, WM8903_POWER_MANAGEMENT_0, CtrlReg);
/* ADC Settings */
CtrlReg = snd_soc_read(codec, WM8903_ADC_DIGITAL_0);
CtrlReg |= (0x1<<B04_ADC_HPF_ENA);
snd_soc_write(codec, WM8903_ADC_DIGITAL_0, CtrlReg);
/* Disable sidetone */
CtrlReg = 0;
snd_soc_write(codec, R20_SIDETONE_CTRL, CtrlReg);
/* Enable ADC */
CtrlReg = snd_soc_read(codec, WM8903_POWER_MANAGEMENT_6);
CtrlReg |= (0x1<<B01_ADCL_ENA);
snd_soc_write(codec, WM8903_POWER_MANAGEMENT_6, CtrlReg);
CtrlReg = snd_soc_read(codec, R29_DRC_1);
CtrlReg |= 0x3; /*mic volume 18 db */
snd_soc_write(codec, R29_DRC_1, CtrlReg);
configure_dmic(codec);
}
#if defined(CONFIG_MACH_ACER_PICASSO) || defined(CONFIG_MACH_ACER_MAYA)
snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, 0xB7);
snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, 0xB7);
#elif defined(CONFIG_MACH_ACER_VANGOGH)
snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, 0xB3);
snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, 0xB3);
#else
snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, 0xB7);
snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, 0xB7);
#endif
return 0;
}