tmp = (enter ? tmp | ENABLE_ASYNC_PMU : tmp & ~ENABLE_ASYNC_PMU);
__raw_writel(tmp, EXYNOS_PMU_PMU_SYNC_CTRL);
tmp = __raw_readl(EXYNOS_PMU_CENTRAL_SEQ_MIF_OPTION);
tmp = (enter ? tmp | USE_AUD_NOT_ACCESS_MIF : tmp & ~USE_AUD_NOT_ACCESS_MIF);
__raw_writel(tmp, EXYNOS_PMU_CENTRAL_SEQ_MIF_OPTION);
tmp = __raw_readl(EXYNOS_PMU_WAKEUP_MASK_MIF);
tmp = (enter ? tmp & ~WAKEUP_MASK_AUD : tmp | WAKEUP_MASK_AUD);
__raw_writel(tmp, EXYNOS_PMU_WAKEUP_MASK_MIF);
}
/* The setting clock list to enter system power mode */
static struct sfr_save save_clk_regs[] = {
#if defined(CONFIG_SOC_EXYNOS5433)
SFR_SAVE(EXYNOS5430_ISP_PLL_CON0),
SFR_SAVE(EXYNOS5430_ISP_PLL_CON1),
SFR_SAVE(EXYNOS5430_AUD_PLL_CON0),
SFR_SAVE(EXYNOS5430_AUD_PLL_CON1),
SFR_SAVE(EXYNOS5430_AUD_PLL_CON2),
SFR_SAVE(EXYNOS5430_MEM0_PLL_CON0),
SFR_SAVE(EXYNOS5430_MEM0_PLL_CON1),
SFR_SAVE(EXYNOS5430_MEM1_PLL_CON0),
SFR_SAVE(EXYNOS5430_MEM1_PLL_CON1),
SFR_SAVE(EXYNOS5430_BUS_PLL_CON0),
SFR_SAVE(EXYNOS5430_BUS_PLL_CON1),
SFR_SAVE(EXYNOS5430_MFC_PLL_CON0),
SFR_SAVE(EXYNOS5430_MFC_PLL_CON1),
SFR_SAVE(EXYNOS5430_SRC_SEL_EGL0),
SFR_SAVE(EXYNOS5430_SRC_SEL_EGL1),
} else if (exynos_asv_member[i].asv_type == ID_G3D) {
exynos_asv_member[i].dvfs_level_nr =
asv_inform->ops_cal->get_min_lv(ID_G3D);
exynos_asv_member[i].max_volt_value =
asv_inform->ops_cal->get_max_volt(ID_G3D);
} else if (exynos_asv_member[i].asv_type == ID_ISP) {
exynos_asv_member[i].dvfs_level_nr =
asv_inform->ops_cal->get_min_lv(ID_ISP);
exynos_asv_member[i].max_volt_value =
asv_inform->ops_cal->get_max_volt(ID_ISP);
}
}
#if defined (CONFIG_PM) && defined (CONFIG_EXYNOS_ASV_DYNAMIC_ABB)
static struct sfr_save exynos_abb_save[] = {
SFR_SAVE(EXYNOS_PMU_BODY_BIAS_CON0),
SFR_SAVE(EXYNOS_PMU_BODY_BIAS_CON1),
SFR_SAVE(EXYNOS_PMU_BODY_BIAS_CON2),
SFR_SAVE(EXYNOS_PMU_BODY_BIAS_CON3),
SFR_SAVE(EXYNOS_PMU_BODY_BIAS_CON4),
};
static int exynos_asv_suspend(void)
{
struct asv_info *exynos_asv_info;
int i;
exynos_save_sfr(exynos_abb_save,
ARRAY_SIZE(exynos_abb_save));
for (i = 0; i < ARRAY_SIZE(exynos_asv_member); i++) {
regs[i].addr = ioremap(be32_to_cpup(reg_list++), SZ_32);
BUG_ON(!regs[i].addr);
regs[i].mask = be32_to_cpup(val_list++);
}
}
static void exynos_lpm_dt_init(void)
{
struct device_node *np = of_find_node_by_name(NULL, "low-power-mode");
parse_dt_reg_list(np, "lpc-reg", "lpc-val", lpc_regs, &lpc_reg_num);
parse_dt_reg_list(np, "lpm-reg", "lpm-val", lpm_regs, &lpm_reg_num);
}
static struct sfr_save save_clk_regs[] = {
SFR_SAVE(EXYNOS7580_DIV_BUS0),
SFR_SAVE(EXYNOS7580_DIV_BUS1),
SFR_SAVE(EXYNOS7580_DIV_BUS2),
SFR_SAVE(EXYNOS7580_DIV_MIF0),
SFR_SAVE(EXYNOS7580_DIV_MIF1),
SFR_SAVE(EXYNOS7580_DIV_TOP0),
SFR_SAVE(EXYNOS7580_DIV_TOP1),
SFR_SAVE(EXYNOS7580_DIV_TOP_FSYS0),
SFR_SAVE(EXYNOS7580_DIV_TOP_FSYS1),
SFR_SAVE(EXYNOS7580_DIV_TOP_FSYS2),
SFR_SAVE(EXYNOS7580_DIV_TOP_PERI0),
SFR_SAVE(EXYNOS7580_DIV_TOP_PERI1),
SFR_SAVE(EXYNOS7580_DIV_TOP_PERI2),
