/*FUNCTION**********************************************************************
*
* Function Name : POWER_SYS_Init
* Description : Initializes the Power manager for operation.
* This function initializes the Power manager and its run-time state structure.
* Reference to an array of Power mode configuration structures has to be passed
* as parameter along with parameter specifying its size. At least one power mode
* configuration is required. Optionally, reference to array of predefined
* call-backs can be passed with its size parameter.
* For details about call-backs refer to the power_manager_callback_user_config_t.
* As Power manager stores only references to array of these structures they have
* to exist while Power manager is used.
* It is expected that prior POWER_SYS_Init() call the write-once protection
* register was configured appropriately allowing to enter all required low power
* modes.
* The following is an example of how to set up two power modes and three
* call-backs and initialize the Power manager with structures containing their settings.
* The example shows two possible ways how where the configuration structures can be stored
* (ROM or RAM) although it is expected that they will be placed rather in the read-only
* memory to save the RAM space. (Note: In the example it is assumed that the programmed chip
* doesn't support any optional power options described in the power_manager_user_config_t)
*
*END**************************************************************************/
power_manager_error_code_t POWER_SYS_Init(power_manager_user_config_t const ** powerConfigsPtr,
uint8_t configsNumber,
power_manager_callback_user_config_t ** callbacksPtr,
uint8_t callbacksNumber)
{
/* Check input parameter - at least one power mode configuration is required */
if ((powerConfigsPtr == NULL) || (configsNumber == 0U))
{
return kPowerManagerError;
}
/* Initialize internal state structure lock */
POWER_SYS_LOCK_INIT();
/* Initialize internal state structure */
memset(&gPowerManagerState, 0, sizeof(power_manager_state_t));
/* Store references to user-defined power mode configurations */
gPowerManagerState.configs = powerConfigsPtr;
gPowerManagerState.configsNumber = configsNumber;
/* Store references to user-defined callback configurations and increment call-back handle counter */
if (callbacksPtr != NULL)
{
gPowerManagerState.staticCallbacks = callbacksPtr;
gPowerManagerState.staticCallbacksNumber = callbacksNumber;
/* Default value of handle of last call-back that returned error */
gPowerManagerState.errorCallbackIndex = callbacksNumber;
}
/* Enables clock gate for LLWU */
#if FSL_FEATURE_SIM_HAS_SCGC_LLWU
SIM_HAL_EnableClock(SIM,kSimClockGateLlwu0);
#endif
return kPowerManagerSuccess;
}
void hardware_init(void) {
/* Enable clock for PORTs */
SIM_HAL_EnableClock(SIM,kSimClockGatePortA);
SIM_HAL_EnableClock(SIM,kSimClockGatePortB);
/* Setup board clock source. */
g_xtal0ClkFreq = 0U; /* System oscillator 0 is not enabled */
init_coredebug_pins(CoreDebug_IDX);
init_gpio_pins(GPIOA_IDX);
init_gpio_pins(GPIOB_IDX);
init_i2c_pins(I2C0_IDX);
init_rcm_pins(RCM_IDX);
init_uart0_pins(UART0_IDX);
}
// Public Methods //////////////////////////////////////////////////////////////
void TwoWire::begin(uint8_t address)
{
rxBufferIndex = 0;
rxBufferLength = 0;
txBufferIndex = 0;
txBufferLength = 0;
slaveBufferIndex = 0;
slaveBufferLength = 0;
transmitting_master = false;
transmitting_slave = false;
receiving_slave = false;
SIM_HAL_EnableClock(SIM, gate_name);
PORT_CLOCK_ENABLE(sda);
PORT_CLOCK_ENABLE(scl);
PORT_BWR_PCR_ODE(PERIPH_PORT(sda), PINS_PIN(sda), true); //set as open drain
PORT_BWR_PCR_ODE(PERIPH_PORT(scl), PINS_PIN(scl), true); //set as open drain
PORT_SET_MUX_I2C(sda);
PORT_SET_MUX_I2C(scl);
I2C_HAL_Init(instance);
I2C_HAL_SetAddress7bit(instance, address);
I2C_HAL_SetStartStopIntCmd(instance, true);
I2C_HAL_SetIntCmd(instance, true);
NVIC_EnableIRQ(irqNumber);
I2C_HAL_Enable(instance);
setClock(100000);
}
void Uart::begin(uint32_t baudrate)
{
SIM_HAL_EnableClock(SIM, gate_name);
PORT_CLOCK_ENABLE(rx);
PORT_CLOCK_ENABLE(tx);
PORT_SET_MUX_UART(rx);
PORT_SET_MUX_UART(tx);
#if FSL_FEATURE_SOC_UART_COUNT
UART_HAL_Init(instance);
UART_HAL_SetBaudRate(instance, clock, baudrate);
UART_HAL_SetBitCountPerChar(instance, kUart8BitsPerChar);
UART_HAL_SetParityMode(instance, kUartParityDisabled);
#if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
UART_HAL_SetStopBitCount(instance, kUartOneStopBit);
#endif
UART_HAL_SetIntMode(instance, kUartIntRxDataRegFull, true);
NVIC_EnableIRQ(irqNumber);
UART_HAL_EnableTransmitter(instance);
UART_HAL_EnableReceiver(instance);
#endif
}
/*!
* @brief Function ltc_timer_init initialize PIT timer
* to measure time.
*/
static void ltc_timer_init(void)
{
SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
PIT_HAL_Enable(pitBase[0]);
PIT_HAL_StopTimer(pitBase[0], LTC_TIMER_PIT_CHANNEL);
PIT_HAL_SetTimerPeriodByCount(pitBase[0], LTC_TIMER_PIT_CHANNEL, RELOAD);
PIT_HAL_SetIntCmd(pitBase[0], LTC_TIMER_PIT_CHANNEL, false);
PIT_HAL_SetTimerRunInDebugCmd(pitBase[0], false); /* timer stop counting in debug mode */
PIT_HAL_ClearIntFlag(pitBase[0], LTC_TIMER_PIT_CHANNEL);
}
/*!
* @Brief enable the trigger source of LPTimer
*/
void init_trigger_source(uint32_t adcInstance)
{
uint32_t freqUs;
lptmr_user_config_t lptmrUserConfig =
{
.timerMode = kLptmrTimerModeTimeCounter,
.freeRunningEnable = false,
.prescalerEnable = false, // bypass perscaler
#if (CLOCK_INIT_CONFIG == CLOCK_VLPR)
// use MCGIRCCLK, 4M or 32KHz
.prescalerClockSource = kClockLptmrSrcMcgIrClk,
#else
// Use LPO clock 1KHz
.prescalerClockSource = kClockLptmrSrcLpoClk,
#endif
.isInterruptEnabled = false
};
// Init LPTimer driver
LPTMR_DRV_Init(0, &gLPTMRState, &lptmrUserConfig);
// Set the LPTimer period
freqUs = 1000000U/(INPUT_SIGNAL_FREQ*NR_SAMPLES)*2;
LPTMR_DRV_SetTimerPeriodUs(0, freqUs);
// Start the LPTimer
LPTMR_DRV_Start(0);
// Configure SIM for ADC hw trigger source selection
#if defined(KM34Z7_SERIES)
SIM_HAL_EnableClock(gSimBase[0], kSimClockGateXbar0);
SIM_HAL_SetAdcTrgSelMode(gSimBase[0], kSimAdcTrgSelXbar);
XBAR_DRV_ConfigSignalConnection(kXbaraInputLPTMR0_Output, kXbaraOutputADC_TRGA);
#else
SIM_HAL_SetAdcAlternativeTriggerCmd(gSimBase[0], adcInstance, true);
SIM_HAL_SetAdcPreTriggerMode(gSimBase[0], adcInstance, kSimAdcPretrgselA);
SIM_HAL_SetAdcTriggerMode(gSimBase[0], adcInstance, kSimAdcTrgSelLptimer);
#endif
}
/*!
* @Brief disable the trigger source
*/
void deinit_trigger_source(uint32_t adcInstance)
{
LPTMR_DRV_Stop(0);
LPTMR_DRV_Deinit(0);
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_EnableUartClock
* Description : Enable the clock for UART module
* This function enables the clock for UART module
*
*END**************************************************************************/
void CLOCK_SYS_EnableUartClock(uint32_t instance)
{
assert(instance < sizeof(uartGateTable)/sizeof(uartGateTable[0]));
SIM_HAL_EnableClock(SIM, uartGateTable[instance]);
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_EnableI2cClock
* Description : Enable the clock for I2C module
* This function enables the clock for I2C module
*
*END**************************************************************************/
void CLOCK_SYS_EnableI2cClock(uint32_t instance)
{
assert(instance < sizeof(i2cGateTable)/sizeof(i2cGateTable[0]));
SIM_HAL_EnableClock(SIM, i2cGateTable[instance]);
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_EnableSpiClock
* Description : Enable the clock for SPI module
* This function enables the clock for SPI module
*
*END**************************************************************************/
void CLOCK_SYS_EnableSpiClock(uint32_t instance)
{
assert(instance < sizeof(spiGateTable)/sizeof(spiGateTable[0]));
SIM_HAL_EnableClock(SIM, spiGateTable[instance]);
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_EnableFtmClock
* Description : Enable the clock for FTM module
* This function enables the clock for FTM module
*
*END**************************************************************************/
void CLOCK_SYS_EnableFtmClock(uint32_t instance)
{
assert(instance < sizeof(ftmGateTable)/sizeof(ftmGateTable[0]));
SIM_HAL_EnableClock(SIM, ftmGateTable[instance]);
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_SYS_EnablePdbClock
* Description : Enable the clock for PDB module
* This function enables the clock for PDB module
*
*END**************************************************************************/
void CLOCK_SYS_EnablePdbClock(uint32_t instance)
{
assert(instance < sizeof(pdbGateTable)/sizeof(pdbGateTable[0]));
SIM_HAL_EnableClock(SIM, pdbGateTable[instance]);
}
/*************************************************************************
* Function Name: Clock_init
* Parameters: none
* Return: none
* Description: Clock initialization
*************************************************************************/
void Clock_init(void)
{
//Enable clock to port
/* SCGC4. */
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateEwm0);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateI2c0);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateUart0);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateUart1);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateCmp);
/* SCGC5. */
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateLptmr0);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGatePortA);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGatePortB);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGatePortC);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGatePortD);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGatePortE);
/* SCGC6. */
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateFtf0);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateDmamux0);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateSpi0);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateCrc0);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGatePdb0);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateFtm0);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateFtm1);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateFtm2);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateAdc0);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateAdc1);
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateDac0);
/* SCGC7. */
SIM_HAL_EnableClock(SIM_BASE_PTR, kSimClockGateDma0);
// clock setting to 75 MHz
CLOCK_SYS_SetOutDiv1(0);
CLOCK_SYS_SetOutDiv4(2);// system clock = MCGOUTCLK ; Flash Clock (bus clock) = MCGOUTCLK / 3
// clock setting to 72 MHz, internal 32768 Hz reference clock oscilator
//MCG->C4 |= MCG_C4_DRST_DRS(2) | MCG_C4_DMX32_MASK;
MCG_WR_C4(MCG_BASE_PTR, MCG_C4_DRST_DRS(2) | MCG_C4_DMX32_MASK);
}
