/* timing model */ static set_error_t set_timing_model(void *dont_care, conf_object_t *obj, attr_value_t *val, attr_value_t *idx) { trans_splitter_t *ts = (trans_splitter_t *) obj; if (val->kind == Sim_Val_Nil) { ts->tm_ifc = NULL; ts->timing_model = NULL; } else { /* get the timing model interface */ ts->tm_ifc = SIM_get_interface(val->u.object, TIMING_MODEL_INTERFACE); if (SIM_clear_exception()) { SIM_log_error(&ts->log, 0, "set_timing_model: " "object does not provide the " "timing model interface."); return Sim_Set_Illegal_Value; } ts->timing_model = val->u.object; } return Sim_Set_Ok; }
integer_t read_reg(conf_object_t *cpu, const char* reg_name) { int reg_num = SIM_get_register_number(SIM_current_processor(), reg_name); if (SIM_clear_exception()) { fprintf(stderr, "read_reg: SIM_get_register_number(%s, %s) failed!\n", cpu->name, reg_name); assert(0); } integer_t val = SIM_read_register(cpu, reg_num); if (SIM_clear_exception()) { fprintf(stderr, "read_reg: SIM_read_register(%s, %d) failed!\n", cpu->name, reg_num); assert(0); } return val; }
const char *asm_s(instruction_id_t ii) { tuple_int_string_t *tuple; attr_value_t pc; pc = SIM_instruction_read_input_reg(ii, V9_Reg_Id_PC); if (pc.kind != Sim_Val_Integer) { SIM_clear_exception(); return "<unknown pc>"; } SIM_clear_exception(); tuple = SIM_disassemble(SIM_instruction_cpu(ii), (logical_address_t)pc.u.integer, 1); if (SIM_get_pending_exception()) { SIM_clear_exception(); return "<disass error>"; } vtsprintf(tmp_buf, "<0x%016llx> %s", (logical_address_t)pc.u.integer, tuple->string); return (const char *)tmp_buf; }
//************************************************************************** void hfa_init_local( void ) { attr_value_t attr; conf_class_t *conf_class; conf_object_t *conf_cpu; memset( &attr, 0, sizeof(attr) ); hfa_checkerr("BEGIN INIT"); if (SIM_number_processors() == 0) { #ifdef SIMICS22X printf("opal: No processors defined -- load a checkpoint first!\n"); printf("opal: Please restart simics and try again.\n"); return; #endif #ifdef SIMICS30 /* * This case arises because of Simics 3.0: * Simics 3.0 loads and "digitally signs" modules immediately after compiling them. * This raises havoc with Multifacet's modules, since most of them require a checkpoint * to be loaded BEFORE the module. */ printf("\033[34;1m\n"); printf(" /***************************************************************************\\\n"); printf(" > Opal found no processors. If you are NOT compiling Opal and you see this <\n"); printf(" > message, something is wrong. <\n"); printf(" > This message is part of the normal compilation process. <\n"); printf(" \\***************************************************************************/\033[m\n\n"); SIM_clear_exception(); return; #endif } /* Initialize and register the class "opal". */ memset(&hfa_class_data, 0, sizeof(class_data_t)); hfa_class_data.new_instance = hfa_new_instance; conf_class = SIM_register_class("opal", &hfa_class_data); /* Initialize and register the timing-model interface */ hfa_timing_interface.operate = NULL; SIM_register_interface(conf_class, TIMING_MODEL_INTERFACE, &hfa_timing_interface); /* Initialize and register the snoop-device interface */ hfa_snoop_interface.operate = NULL; SIM_register_interface(conf_class, SNOOP_MEMORY_INTERFACE, &hfa_snoop_interface); /* Initialize and register the event poster interface */ hfa_event_poster_interface.get_event_info = hfa_get_event; hfa_event_poster_interface.set_event_info = hfa_set_event; hfa_event_poster_interface.describe_event = hfa_describe_event; SIM_register_interface(conf_class, "event-poster", &hfa_event_poster_interface); /* Initialize and register multifacet-ruby interface */ memset(&hfa_ruby_interface, 0, sizeof(hfa_ruby_interface)); SIM_register_interface(conf_class, "mf-opal-api", &hfa_ruby_interface); /** create the hfa object */ hfa_conf_object = (hfa_object_t *) SIM_new_object(conf_class, "opal0"); /* register with cpu 0 event queue */ attr.kind = Sim_Val_Object; conf_cpu = SIM_next_queue(0); if (conf_cpu) { attr.u.object = conf_cpu; printf("Queue registration %s\n", conf_cpu->name ); set_error_t install_error = SIM_set_attribute( (conf_object_t *) hfa_conf_object, "queue", &attr ); if (install_error == Sim_Set_Ok) { printf( "successful installation of the opal queue.\n"); } else { printf( "error installing opal queue.\n"); exit(1); } } else { printf("error: unable to register queue interface\n"); } /* register interfaces on the hfa0 object */ /* event-poster interface */ SIM_register_attribute( conf_class, "install-event-poster", hfa_post_get, (void *) "install-event-poster", hfa_post_set, (void *) "install-event-poster", Sim_Attr_Pseudo, "Post a trace-related function to event queue" ); // Allocate and initialize a configuration reader hfa_construct_initvar(); hfa_checkerr("hfa_construct_initvar(): check"); // register a number of commands #define OPAL_COMMAND( COMMAND ) \ SIM_register_attribute( conf_class, COMMAND, \ initvar_dispatch_get, (void *) COMMAND, \ initvar_dispatch_set, (void *) COMMAND, \ Sim_Attr_Pseudo, \ "See documentation with associated opal command." ) /** read a configuration file */ OPAL_COMMAND( "init" ); OPAL_COMMAND( "readparam" ); OPAL_COMMAND( "saveparam" ); /** interfaces for recording a trace to disk */ OPAL_COMMAND( "trace-start" ); OPAL_COMMAND( "trace-stop" ); OPAL_COMMAND( "take-trace" ); OPAL_COMMAND( "skip-trace" ); OPAL_COMMAND( "branch-trace-start" ); OPAL_COMMAND( "branch-trace-stop" ); OPAL_COMMAND( "branch-trace-take" ); OPAL_COMMAND( "branch-trace-inf" ); OPAL_COMMAND( "stepper" ); OPAL_COMMAND( "param" ); /** interfaces to run inside of simics */ OPAL_COMMAND( "sim-flag" ); OPAL_COMMAND( "sim-start" ); OPAL_COMMAND( "sim-stop" ); OPAL_COMMAND( "sim-step" ); OPAL_COMMAND( "break_simulation" ); OPAL_COMMAND( "sim-inorder-step" ); OPAL_COMMAND( "sim-warmup" ); OPAL_COMMAND( "cycle" ); OPAL_COMMAND( "sim-stats" ); OPAL_COMMAND( "sim-inflight" ); OPAL_COMMAND( "sim-rd-check" ); OPAL_COMMAND( "sim-wr-check" ); OPAL_COMMAND( "debugtime" ); OPAL_COMMAND( "stall" ); OPAL_COMMAND( "togglemh" ); OPAL_COMMAND( "install-snoop" ); OPAL_COMMAND( "mlp-trace" ); // ADD_SIMCOMMAND // check for errors hfa_checkerr("class regististration"); // check that we are compatible with this version of the simulator hfa_simcheck(); hfa_checkerr("hfa_simcheck(): check"); printf("hfa_init_local done:\n"); return; }
//************************************************************************** void init_local() { class_data_t ruby_funcs; conf_class_t *ruby_class; conf_object_t *ruby_obj; attr_value_t val; conf_object_t *phys_mem0; /* Initialize and register the class "ruby-class". */ bzero(&ruby_funcs, sizeof(class_data_t)); ruby_funcs.new_instance = ruby_new_instance; ruby_funcs.delete_instance = NULL; ruby_class = SIM_register_class("ruby", &ruby_funcs); /* initialize the variable reader: sets all global variables to defaults */ init_variables(); /* Initialize and register the timing-model interface */ ruby_timing_interface = MM_ZALLOC(1, timing_model_interface_t); ruby_timing_interface->operate = ruby_operate; SIM_register_interface(ruby_class, "timing-model", ruby_timing_interface); ruby_obj = SIM_new_object(ruby_class, "ruby0"); phys_mem0 = SIM_get_object("phys_mem0"); if(phys_mem0 == NULL) { /* Look for an object called "phys_mem" instead */ SIM_clear_exception(); phys_mem0 = SIM_get_object("phys_mem"); } if(phys_mem0 == NULL) { /* Okay, now we can panic */ #ifndef SIMICS30 /* * Must load a checkpoint BEFORE load-module ruby */ printf("Please load a checkpoint BEFORE executing \"load-module ruby\"\n"); #endif #ifdef SIMICS30 /* * This case arises because of Simics 3.0: * Simics 3.0 loads and "digitally signs" modules immediately after compiling them. * This raises havoc with Multifacet's modules, since most of them require a checkpoint * to be loaded BEFORE the module. */ printf("\033[34;1m\n"); printf(" /***************************************************************************\\\n"); printf(" > Physical Memory object cannot be found. If you are NOT compiling Ruby and <\n"); printf(" > you see this message, something is wrong. <\n"); printf(" > This message is part of the normal compilation process. <\n"); printf(" \\***************************************************************************/\033[m\n\n"); #endif SIM_clear_exception(); return; } val.kind = Sim_Val_Object; val.u.object = ruby_obj; set_error_t install_error = SIM_set_attribute(phys_mem0, "timing_model", &val); if (install_error == Sim_Set_Ok) { printf( "successful installation of the ruby timing model.\n"); } else { printf( "error installing ruby timing model.\n"); exit(1); } /* Initialize the snoop interface if we are tracking values in simics */ if (init_use_snoop() == 1) { ruby_observe_interface = MM_ZALLOC(1, timing_model_interface_t); ruby_observe_interface->operate = ruby_observe; SIM_register_interface(ruby_class, "snoop-memory", ruby_observe_interface); SIM_set_attribute(phys_mem0, "snoop_device", &val); } /* init_opal_interface calls to a static function in OpalInterface.C * to determine is opal is installed. If it is, it registers itself, * and notifies opal that ruby is loaded. Otherwise, it does nothing. */ opal_interface = MM_ZALLOC(1, mf_ruby_api_t); SIM_register_interface(ruby_class, "mf-ruby-api", opal_interface); init_opal_interface( opal_interface ); // register a number of commands #define RUBY_COMMAND( COMMAND ) \ SIM_register_attribute( ruby_class, COMMAND, \ initvar_dispatch_get, (void *) COMMAND, \ initvar_dispatch_set, (void *) COMMAND, \ Sim_Attr_Session, \ "See documentation with associated ruby command." ) RUBY_COMMAND( "init" ); RUBY_COMMAND( "readparam" ); RUBY_COMMAND( "saveparam" ); RUBY_COMMAND( "param" ); RUBY_COMMAND( "dump-stats" ); RUBY_COMMAND( "dump-short-stats" ); RUBY_COMMAND( "periodic-stats-file" ); RUBY_COMMAND( "periodic-stats-interval" ); RUBY_COMMAND( "clear-stats" ); RUBY_COMMAND( "system-recovery" ); RUBY_COMMAND( "debug-verb" ); RUBY_COMMAND( "debug-filter" ); RUBY_COMMAND( "debug-output-file" ); RUBY_COMMAND( "debug-start-time" ); RUBY_COMMAND( "set-checkpoint-interval" ); RUBY_COMMAND( "load-caches" ); RUBY_COMMAND( "save-caches" ); RUBY_COMMAND( "dump-cache" ); RUBY_COMMAND( "dump-cache-data" ); RUBY_COMMAND( "tracer-output-file" ); RUBY_COMMAND( "set-procs-per-chip" ); RUBY_COMMAND( "abort-all" ); RUBY_COMMAND( "xact-visualizer-file" ); RUBY_COMMAND( "print-temp" ); RUBY_COMMAND( "reset-temp" ); RUBY_COMMAND( "print-reuse" ); RUBY_COMMAND( "reset-reuse" ); // Add end_transaction magic callback SIM_hap_add_callback("Core_Magic_Instruction", (obj_hap_func_t) magic_instruction_callback, NULL); #ifdef SPARC SIM_hap_add_callback("Core_Exception", (obj_hap_func_t) ctrl_exception_start, NULL); SIM_hap_add_callback("Core_Exception_Return", (obj_hap_func_t) ctrl_exception_done, NULL); SIM_hap_add_callback("Core_Mode_Change", (obj_hap_func_t) change_mode_callback, NULL); /// for MMU SIM_hap_add_callback("MMU_Data_TLB_Demap", (obj_hap_func_t) dtlb_demap_callback, NULL); SIM_hap_add_callback("MMU_Data_TLB_Map", (obj_hap_func_t) dtlb_map_callback, NULL); SIM_hap_add_callback("MMU_Data_TLB_Overwrite", (obj_hap_func_t) dtlb_overwrite_callback, NULL); SIM_hap_add_callback("MMU_Data_TLB_Replace", (obj_hap_func_t) dtlb_replace_callback, NULL); // Add callbacks to abort transactions on exceptions in Rock. // SIM_hap_add_callback("Core_Exception", (obj_hap_func_t) rock_exception_start, (void *) NULL); SIM_hap_add_callback("Core_Exception_Return", (obj_hap_func_t) rock_exception_done, (void *) NULL); // Add instruction decoder to install handlers for Rock-specific behavior. // decoder_t* decoder = ATMTP_create_instruction_decoder(); SIM_register_arch_decoder(decoder, NULL, 0); #endif // CM 2/2003: // Note: Please register other callbacks in the appropriate interface file, // instead of here. This module should only register callbacks that // are common to the "Driver" class (parent class to SimicsInterface // and OpalInterface). // If its only used by SimicsInterface, put it in that class. }