SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0),
SND_SOC_DAPM_MUX("Digital CH4 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch4_mux),
SND_SOC_DAPM_MUX("Digital CH3 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch3_mux),
SND_SOC_DAPM_MUX("Digital CH2 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch2_mux),
SND_SOC_DAPM_MUX("Digital CH1 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,
aiftx_power_control, SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route nau8540_dapm_routes[] = {
{"Frontend PGA1", NULL, "MIC1"},
{"Frontend PGA2", NULL, "MIC2"},
{"Frontend PGA3", NULL, "MIC3"},
{"Frontend PGA4", NULL, "MIC4"},
{"ADC1", NULL, "Frontend PGA1"},
{"ADC2", NULL, "Frontend PGA2"},
{"ADC3", NULL, "Frontend PGA3"},
{"ADC4", NULL, "Frontend PGA4"},
{"ADC CH1", NULL, "ADC1"},
{"ADC CH2", NULL, "ADC2"},
static const struct snd_kcontrol_new wm8804_tx_source_mux[] = {
SOC_DAPM_ENUM_EXT("Input Source", txsrc,
snd_soc_dapm_get_enum_double, txsrc_put),
};
static const struct snd_soc_dapm_widget wm8804_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("SPDIF Out"),
SND_SOC_DAPM_INPUT("SPDIF In"),
SND_SOC_DAPM_PGA("SPDIFTX", WM8804_PWRDN, 2, 1, NULL, 0),
SND_SOC_DAPM_PGA("SPDIFRX", WM8804_PWRDN, 1, 1, NULL, 0),
SND_SOC_DAPM_MUX("Tx Source", SND_SOC_NOPM, 6, 0, wm8804_tx_source_mux),
SND_SOC_DAPM_AIF_OUT_E("AIFTX", NULL, 0, SND_SOC_NOPM, 0, 0, wm8804_aif_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN_E("AIFRX", NULL, 0, SND_SOC_NOPM, 0, 0, wm8804_aif_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route wm8804_dapm_routes[] = {
{ "AIFRX", NULL, "Playback" },
{ "Tx Source", "AIF", "AIFRX" },
{ "SPDIFRX", NULL, "SPDIF In" },
{ "Tx Source", "S/PDIF RX", "SPDIFRX" },
{ "SPDIFTX", NULL, "Tx Source" },
{ "SPDIF Out", NULL, "SPDIFTX" },
{ "AIFTX", NULL, "SPDIFRX" },
2, 1, cs35l33_sdin_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("MON"),
SND_SOC_DAPM_ADC("VMON", NULL,
CS35L33_PWRCTL2, CS35L33_PDN_VMON_SHIFT, 1),
SND_SOC_DAPM_ADC("IMON", NULL,
CS35L33_PWRCTL2, CS35L33_PDN_IMON_SHIFT, 1),
SND_SOC_DAPM_ADC("VPMON", NULL,
CS35L33_PWRCTL2, CS35L33_PDN_VPMON_SHIFT, 1),
SND_SOC_DAPM_ADC("VBSTMON", NULL,
CS35L33_PWRCTL2, CS35L33_PDN_VBSTMON_SHIFT, 1),
SND_SOC_DAPM_AIF_OUT_E("SDOUT", NULL, 0, SND_SOC_NOPM, 0, 0,
cs35l33_sdout_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_PRE_PMD),
};
static const struct snd_soc_dapm_route cs35l33_audio_map[] = {
{"SDIN", NULL, "CS35L33 Playback"},
{"SPKDRV", NULL, "SDIN"},
{"SPK", NULL, "SPKDRV"},
{"VMON", NULL, "MON"},
{"IMON", NULL, "MON"},
{"SDOUT", NULL, "VMON"},
{"SDOUT", NULL, "IMON"},
{"CS35L33 Capture", NULL, "SDOUT"},
};
/* SGEN */
SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6351_AFE_SGEN_CFG0,
SGEN_C_DAC_EN_CTL_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6351_AFE_SGEN_CFG0,
SGEN_C_MUTE_SW_CTL_BIT, 1,
mt_sgen_event, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6351_AFE_DL_SRC2_CON0_L,
RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0, NULL, 0),
SND_SOC_DAPM_INPUT("SGEN DL"),
/* Uplinks */
SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
MT6351_AFE_UL_SRC_CON0_L,
UL_SRC_ON_TMP_CTL, 0,
mt_aif_out_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO", SUPPLY_SUBSEQ_ENABLE,
MT6351_LDO_VUSB33_CON0, RG_VUSB33_EN, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO_CTRL", SUPPLY_SUBSEQ_SETTING,
MT6351_LDO_VUSB33_CON0, RG_VUSB33_ON_CTRL, 1,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("VA18_LDO", SUPPLY_SUBSEQ_ENABLE,
MT6351_LDO_VA18_CON0, RG_VA18_EN, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("VA18_LDO_CTRL", SUPPLY_SUBSEQ_SETTING,
MT6351_LDO_VA18_CON0, RG_VA18_ON_CTRL, 1,
NULL, 0),
