/*****************************************************************************
function name : mali_regulator_enable
description : powerup mali by calling regulator
input vars : void
output vars : NA
return value : void
calls : regulator_enable
called : mali_platform_powerup
history :
1.data : 04/03/2014
author : s00250033
modify : new
*****************************************************************************/
void mali_regulator_enable(void)
{
int i, ret;
if( IS_ERR_OR_NULL(mali_regulator) )
{
MALI_DEBUG_PRINT(1, ("error on mali_regulator_enable : g3d_regulator is null\n"));
return;
}
ret = regulator_enable(mali_regulator);
if(ret < 0)
{
return;
}
for (i = 0; i < 50; i++)
{
ret = phy_reg_readl(SOC_AO_SCTRL_BASE_ADDR, SOC_AO_SCTRL_SC_PW_MTCMOS_STAT0_ADDR(0), 1, 1);
if (1 == ret)
{
MALI_DEBUG_PRINT(3, ("MTCMOS open OK\n"));
break;
}
udelay(1);
}
if (50 == i)
{
MALI_DEBUG_PRINT(2, ("****error: MTCMOS open failed\n"));
return;
}
}
int video_harden_regdis_clkdis_isoen_rsten_check(video_harden_dev_id_enum dev_id)
{
unsigned int regTmp = 0xff;
unsigned int regExpect = 0x0;
int ret = 0;
printk(KERN_INFO "dev_Id is %d. start video_harden_rstdis_isodis_clken_check.....\n", dev_id);
ret = video_harden_device_id_check(dev_id);
if (ret != 0) {
return 0;
}
ret = down_interruptible(&video_harden_busy_lock);
if (0 != ret) {
printk(KERN_ERR "video_harden_busy_lock failed\n");
return 0;
}
if ((0 == video_harden_rst_iso_clk_vote.vcodec_bit)
&& (0 == video_harden_rst_iso_clk_vote.jpeg_bit)
&& (0 == video_harden_rst_iso_clk_vote.isp_bit)) {
/*================== AO_SC PW MTCMOS STAT [0x838] ==================*/
regTmp = phy_reg_readl(SOC_AO_SCTRL_BASE_ADDR,
SOC_AO_SCTRL_SC_PW_MTCMOS_STAT0_ADDR(CALC_REG_OFFSET),
SOC_AO_SCTRL_SC_PW_MTCMOS_STAT0_pw_mtcmos_ack_stat0_2codecisp_START,
SOC_AO_SCTRL_SC_PW_MTCMOS_STAT0_pw_mtcmos_ack_stat0_2codecisp_END);
printk(KERN_INFO "PW MTCMOS STAT = 0x%x, addr=0x%x\n", regTmp,
(SOC_AO_SCTRL_BASE_ADDR+SOC_AO_SCTRL_SC_PW_MTCMOS_STAT0_ADDR(CALC_REG_OFFSET)));
regExpect = 0x0;
if (regTmp != regExpect) {
printk(KERN_ERR "ERR: PW MTCMOS STAT = 0x%x\n", regExpect);
ret = -1;
}
regExpect = 0x0;
regTmp = 0xffff;
/*================== AO_SC PW CLK STAT [0x808] ==================*/
regTmp = phy_reg_readl(SOC_AO_SCTRL_BASE_ADDR,
SOC_AO_SCTRL_SC_PW_CLK_STAT0_ADDR(CALC_REG_OFFSET),
SOC_AO_SCTRL_SC_PW_CLK_STAT0_pw_clk_stat0_2codecisp_START,
SOC_AO_SCTRL_SC_PW_CLK_STAT0_pw_clk_stat0_2codecisp_END);
printk(KERN_INFO "PW CLK STAT: 2codecisp = 0x%x, addr=0x%x\n", regTmp,
(SOC_AO_SCTRL_BASE_ADDR+SOC_AO_SCTRL_SC_PW_CLK_STAT0_ADDR(CALC_REG_OFFSET)));
regExpect = 0x0;
if (regTmp != regExpect) {
printk(KERN_ERR "ERR:PW CLK STAT: 2codecisp = 0x%x\n", regExpect);
ret = -1;
}
regExpect = 0x0;
regTmp = 0xffff;
/*================== AO_SC PW ISO STAT [0x828] ==================*/
regTmp = phy_reg_readl(SOC_AO_SCTRL_BASE_ADDR,
SOC_AO_SCTRL_SC_PW_ISO_STAT0_ADDR(CALC_REG_OFFSET),
SOC_AO_SCTRL_SC_PW_ISO_STAT0_pw_iso_stat0_2codecisp_START,
SOC_AO_SCTRL_SC_PW_ISO_STAT0_pw_iso_stat0_2codecisp_END);
printk(KERN_INFO "PW ISO STAT: 2codecisp = 0x%x, addr=0x%x\n", regTmp,
(SOC_AO_SCTRL_BASE_ADDR+SOC_AO_SCTRL_SC_PW_ISO_STAT0_ADDR(CALC_REG_OFFSET)));
regExpect = 0x1;
if (regTmp != regExpect) {
printk(KERN_ERR "ERR:PW ISO STAT: 2codecisp = 0x%x\n", regExpect);
ret = -1;
}
regExpect = 0x0;
regTmp = 0xffff;
/*================== AO_SC PW RST STAT [0x818] ==================*/
regTmp = phy_reg_readl(SOC_AO_SCTRL_BASE_ADDR,
SOC_AO_SCTRL_SC_PW_RST_STAT0_ADDR(CALC_REG_OFFSET),
SOC_AO_SCTRL_SC_PW_RST_STAT0_pw_rst_stat0_2codecisp_START,
SOC_AO_SCTRL_SC_PW_RST_STAT0_pw_rst_stat0_2codecisp_END);
printk(KERN_INFO "PW RST STAT: 2codecisp = 0x%x, addr=0x%x\n", regTmp,
(SOC_AO_SCTRL_BASE_ADDR+SOC_AO_SCTRL_SC_PW_RST_STAT0_ADDR(CALC_REG_OFFSET)));
regExpect = 0x1;
if (regTmp != regExpect) {
printk(KERN_ERR "ERR:PW RST STAT: 2codecisp = 0x%x\n", regExpect);
ret = -1;
}
regExpect = 0x0;
regTmp = 0xffff;
} else {
printk(KERN_INFO "video_harden_regdis_clkdis_isoen_rsten_check is unnecessary!. \n");
}
up(&video_harden_busy_lock);
return ret;
}
