/*****************************************************************************
Description : platform related, sctrl register initial,
set SCTRL to reset device when watchdog freeze
1.Date: 2012/9/13
Author : x00138766
Modification : Created function
*****************************************************************************/
static void __init sctrl_reset_mode_init(void)
{
/*Modify_for_c_reset, l00212112,20130511, starts*/
/*改为报中断给mcu*/
#if 1
void __iomem *base = NULL;
unsigned int val = 1;
unsigned int val_org = 1;
base = (void __iomem *)IO_ADDRESS(REG_BASE_SC_ON);
writel(val, SOC_AO_SCTRL_SC_INT_EN0_ADDR(base));
val = readl(SOC_AO_SCTRL_SC_MCU_WKUP_INT_EN1_ADDR(base));
printk(KERN_INFO"sctrl_reset_mode_init, val1 = 0x%X\n", val);
writel((val | (1 << 5)), SOC_AO_SCTRL_SC_MCU_WKUP_INT_EN1_ADDR(base));
val = readl(SOC_AO_SCTRL_SC_MCU_WKUP_INT_EN1_ADDR(base));
printk(KERN_INFO"sctrl_reset_mode_init, val1 = 0x%X\n", val);
val_org = readl(SOC_AO_SCTRL_SC_SYS_CTRL1_ADDR(base));
printk(KERN_INFO"sctrl_reset_mode_init, val_org = 0x%X\n", val_org);
val_org = (~(1<<WDT_RESET_DEVICE_MASK_BIT)) & val_org;
val = (~(1<<WDT_RESET_DEVICE_CFG_BIT)) & val_org;
printk(KERN_INFO"sctrl_reset_mode_init, val_new = 0x%X\n", val);
writel(val, SOC_AO_SCTRL_SC_SYS_CTRL1_ADDR(base));
#else
void __iomem *base = NULL;
unsigned int val = (1<<WDT_RESET_DEVICE_MASK_BIT | 1<<WDT_RESET_DEVICE_CFG_BIT);
base = (void __iomem *)IO_ADDRESS(REG_BASE_SC_ON);
writel(val, SOC_AO_SCTRL_SC_SYS_CTRL1_ADDR(base));
#endif
/*Modify_for_c_reset, l00212112,20130511, ends*/
return;
}
s32_t pwrctrl_sleep_initial ( void_t )
{
pwrctrl_arm_init();
/*修改掉电后重启后pc指向的位置:*/
pwrctrl_write_reg32(IO_ADDRESS(PWRCTRL_ACPU_ASM_SPACE_ADDR), PWRCTRL_JMP_INSTRUCTION);
/*remap to sram*/
#if defined(CHIP_BB_HI6210)/*B020 Modify*/
pwrctrl_set_bits(IO_ADDRESS(SOC_AO_SCTRL_SC_SYS_CTRL1_ADDR(SOC_AO_SCTRL_BASE_ADDR)), \
BIT(SOC_AO_SCTRL_SC_SYS_CTRL1_remap_sram_aarm_START) | \
BIT(SOC_AO_SCTRL_SC_SYS_CTRL1_remap_sram_aarm_msk_START));
#else
pwrctrl_set_bits(IO_ADDRESS(SOC_AO_SCTRL_SC_SECURITY_CTRL2_ADDR(SOC_SC_ON_BASE_ADDR)), \
BIT(SOC_AO_SCTRL_SC_SECURITY_CTRL2_remap_sram_aarm_START));
#endif
#if 0/*defined(CHIP_BB_HI6210)*//*A7 feature, support hardware invalid cache*/
pwrctrl_set_bits(IO_ADDRESS(SOC_ACPU_SCTRL_ACPU_SC_CPU0_CTRL_ADDR(SOC_ACPU_SC_BASE_ADDR)),\
BIT(SOC_ACPU_SCTRL_ACPU_SC_CPU0_CTRL_l1rstdisable0_START));
pwrctrl_set_bits(IO_ADDRESS(SOC_ACPU_SCTRL_ACPU_SC_CPU1_CTRL_ADDR(SOC_ACPU_SC_BASE_ADDR)),\
BIT(SOC_ACPU_SCTRL_ACPU_SC_CPU1_CTRL_l1rstdisable1_START));
pwrctrl_set_bits(IO_ADDRESS(SOC_ACPU_SCTRL_ACPU_SC_CPU2_CTRL_ADDR(SOC_ACPU_SC_BASE_ADDR)),\
BIT(SOC_ACPU_SCTRL_ACPU_SC_CPU2_CTRL_l1rstdisable2_START));
pwrctrl_set_bits(IO_ADDRESS(SOC_ACPU_SCTRL_ACPU_SC_CPU3_CTRL_ADDR(SOC_ACPU_SC_BASE_ADDR)),\
BIT(SOC_ACPU_SCTRL_ACPU_SC_CPU3_CTRL_l1rstdisable3_START));
pwrctrl_set_bits(IO_ADDRESS(SOC_ACPU_SCTRL_ACPU_SC_CPU_CTRL_ADDR(SOC_ACPU_SC_BASE_ADDR)),\
BIT(SOC_ACPU_SCTRL_ACPU_SC_CPU_CTRL_l2rstdisable_START));
#endif
return RET_OK;
}
static int mntn_dump_sram_mcu_finish(void)
{
void __iomem * sys_ctrl_addr;
unsigned int sc_ctrl1;
sys_ctrl_addr = ioremap(REG_BASE_SC_ON, REG_SC_ON_IOSIZE);
if (NULL == sys_ctrl_addr)
{
MNTN_FILESYS_PRINT(KERN_ERR"mntn_err: fail to map after accessing mcu sram!\n");
return -1;
};
sc_ctrl1 = readl(SOC_AO_SCTRL_SC_SYS_CTRL1_ADDR(sys_ctrl_addr));
sc_ctrl1 |= 0x80008000;
writel(sc_ctrl1, (SOC_AO_SCTRL_SC_SYS_CTRL1_ADDR(sys_ctrl_addr)));
iounmap(sys_ctrl_addr);
return 0;
}
