/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
uint32_t n;
/* The system is switched to the RUN0 mode, the default for normal
operations.*/
if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
/* PIT_0 clock initialization.*/
halSPCSetPeripheralClockMode(30, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
/* TB counter enabled for debug and measurements.*/
asm volatile ("li %%r3, 0x4000 \t\n" /* TBEN bit. */
"mtspr 1008, %%r3" /* HID0 register. */
: : : "r3");
/* PIT channel 0 initialization for Kernel ticks, the PIT is configured
to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
modes.*/
INTC_PSR(226) = SPC5_PIT0_IRQ_PRIORITY;
n = SPC5_AC12_DC4_CLK / OSAL_ST_FREQUENCY - 1;
PIT_0.MCR.R = 1; /* Clock enabled, stop while debugging. */
PIT_0.CH[0].LDVAL.R = n;
PIT_0.CH[0].CVAL.R = n;
PIT_0.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */
PIT_0.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
/* EDMA initialization.*/
// edmaInit();
}
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
uint32_t reg;
/* The system is switched to the RUN0 mode, the default for normal
operations.*/
if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
/* INTC initialization, software vector mode, 4 bytes vectors, starting
at priority 0.*/
INTC.MCR.R = 0;
INTC.CPR.R = 0;
INTC.IACKR.R = (uint32_t)_vectors;
/* PIT channel 0 initialization for Kernel ticks, the PIT is configured
to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
modes.*/
INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY;
halSPCSetPeripheralClockMode(92,
SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
reg = halSPCGetSystemClock() / OSAL_ST_FREQUENCY - 1;
PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
PIT.CH[0].LDVAL.R = reg;
PIT.CH[0].CVAL.R = reg;
PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */
PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
/* EDMA initialization.*/
edmaInit();
}
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
uint32_t n;
/* The system is switched to the RUN0 mode, the default for normal
operations.*/
if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
#if SPC5_HSM_HANDSHAKE == 1
/* Notifies the HSM full clock initialization.*/
HT2HSMF = 2;
#endif
#if SPC5_HSM_HANDSHAKE == 2
/* Notifies the HSM full clock initialization by clearing WF_CC_DONE bit
* Note that clearing a bit in HSM2HTF mailbox is done by writing 1 in the bit
*
* We also clear the CLK_CHG_RDY bit, no longer used
*/
HSM2HTF = WF_CC_DONE | CLK_CHG_RDY;
#endif
/* PIT_0 clock initialization.*/
halSPCSetPeripheralClockMode(30, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
/* TB counter enabled for debug and measurements.*/
asm volatile ("li %%r3, 0x4000 \t\n" /* TBEN bit. */
"mtspr 1008, %%r3" /* HID0 register. */
: : : "r3");
/* PIT channel 0 initialization for Kernel ticks, the PIT is configured
to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
modes.*/
INTC_PSR(226) = SPC5_PIT0_IRQ_PRIORITY;
n = SPC5_AC12_DC4_CLK / OSAL_ST_FREQUENCY - 1;
PIT_0.MCR.R = 1; /* Clock enabled, stop while debugging. */
PIT_0.TIMER[0].LDVAL.R = n;
PIT_0.TIMER[0].CVAL.R = n;
PIT_0.TIMER[0].TFLG.R = 1; /* Interrupt flag cleared. */
PIT_0.TIMER[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
/* EDMA initialization.*/
// edmaInit();
}
/**
* @brief SPC560B/Cxx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h and
* @p hal_lld.h
* @note This function must be invoked only after the system reset.
*
* @special
*/
void spc_clock_init(void) {
/* Waiting for IRC stabilization before attempting anything else.*/
while (!ME.GS.B.S_FIRC)
;
#if !SPC5_NO_INIT
#if SPC5_DISABLE_WATCHDOG
/* SWT disabled.*/
SWT.SR.R = 0xC520;
SWT.SR.R = 0xD928;
SWT.CR.R = 0xFF00000A;
#endif
/* SSCM initialization. Setting up the most restrictive handling of
invalid accesses to peripherals.*/
SSCM.ERROR.R = 3; /* PAE and RAE bits. */
/* RGM errors clearing.*/
RGM.FES.R = 0xFFFF;
RGM.DES.R = 0xFFFF;
/* Oscillators dividers setup.*/
CGM.FIRC_CTL.B.RCDIV = SPC5_IRCDIV_VALUE - 1;
CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1;
/* The system must be in DRUN mode on entry, if this is not the case then
it is considered a serious anomaly.*/
if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) {
SPC5_CLOCK_FAILURE_HOOK();
}
#if defined(SPC5_OSC_BYPASS)
/* If the board is equipped with an oscillator instead of a xtal then the
bypass must be activated.*/
CGM.FXOSC_CTL.B.OSCBYP = TRUE;
#endif /* SPC5_OSC_BYPASS */
/* Setting the various dividers and source selectors.*/
CGM.SC_DC0.R = SPC5_CGM_SC_DC0;
CGM.SC_DC1.R = SPC5_CGM_SC_DC1;
CGM.SC_DC2.R = SPC5_CGM_SC_DC2;
/* Initialization of the FMPLLs settings.*/
CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
(SPC5_FMPLL0_NDIV_VALUE << 16);
CGM.FMPLL_MR.R = 0; /* TODO: Add a setting. */
/* Run modes initialization.*/
ME.IS.R = 8; /* Resetting I_ICONF status.*/
ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */
ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */
ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */
ME.HALT.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
ME.STOP.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
ME.STANDBY.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */
if (ME.IS.B.I_ICONF) {
/* Configuration rejected.*/
SPC5_CLOCK_FAILURE_HOOK();
}
/* Peripherals run and low power modes initialization.*/
ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS;
ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS;
ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS;
ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS;
ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS;
ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS;
ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS;
ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS;
ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS;
ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS;
ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS;
ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS;
ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS;
ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS;
ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS;
ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS;
/* CFLASH settings calculated for a maximum clock of 48MHz.*/
CFLASH.PFCR0.B.BK0_APC = 2;
CFLASH.PFCR0.B.BK0_RWSC = 2;
/* CMU clock enable */
halSPCSetPeripheralClockMode(104,
SPC5_ME_PCTL_RUN(1) | SPC5_ME_PCTL_LP(2));
/* Switches again to DRUN mode (current mode) in order to update the
settings.*/
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
#endif /* !SPC5_NO_INIT */
}
/**
* @brief SPC56ELxx early initialization.
* @note All the involved constants come from the file @p board.h and
* @p hal_lld.h
* @note This function must be invoked only after the system reset.
*
* @special
*/
void spc_clock_init(void) {
/* Waiting for IRC stabilization before attempting anything else.*/
while (!MC_ME.GS.B.S_IRC)
;
#if !SPC5_NO_INIT
#if SPC5_DISABLE_WATCHDOG
/* SWTs disabled.*/
SWT_0.SR.R = 0xC520;
SWT_0.SR.R = 0xD928;
SWT_0.CR.R = 0xFF000002;
SWT_1.SR.R = 0xC520;
SWT_1.SR.R = 0xD928;
SWT_1.CR.R = 0xFF000002;
SWT_2.SR.R = 0xC520;
SWT_2.SR.R = 0xD928;
SWT_2.CR.R = 0xFF000002;
SWT_3.SR.R = 0xC520;
SWT_3.SR.R = 0xD928;
SWT_3.CR.R = 0xFF000002;
#endif
/* SSCM initialization from configuration data.*/
SSCM.ERROR.R = SPC5_SSCM_ERROR_INIT;
/* RGM errors clearing.*/
MC_RGM.FES.R = 0xFFFF;
MC_RGM.DES.R = 0xFFFF;
/* The system must be in DRUN mode on entry, if this is not the case then
it is considered a serious anomaly.*/
if (MC_ME.GS.B.S_CURRENT_MODE != SPC5_RUNMODE_DRUN) {
SPC5_CLOCK_FAILURE_HOOK();
}
#if defined(SPC5_OSC_BYPASS)
/* If the board is equipped with an oscillator instead of a crystal then the
bypass must be activated.*/
XOSC.CTL.B.OSCBYP = TRUE;
#endif /* SPC5_OSC_BYPASS */
/* Setting the system dividers to their final values.*/
MC_CGM.SC_DC0.R = SPC5_CGM_SC_DC0_BITS;
MC_CGM.SC_DC1.R = SPC5_CGM_SC_DC1_BITS;
MC_CGM.SC_DC2.R = SPC5_CGM_SC_DC2_BITS;
MC_CGM.SC_DC3.R = SPC5_CGM_SC_DC3_BITS;
#if !defined(_SPC58NE84C3_CUT1_)
MC_CGM.SC_DC4.R = SPC5_CGM_SC_DC4_BITS;
#endif
/* Setting the auxiliary dividers to their final values.*/
MC_CGM.AC0_DC0.R = SPC5_CGM_AC0_DC0_BITS;
MC_CGM.AC0_DC1.R = SPC5_CGM_AC0_DC1_BITS;
MC_CGM.AC0_DC2.R = SPC5_CGM_AC0_DC2_BITS;
MC_CGM.AC0_DC3.R = SPC5_CGM_AC0_DC3_BITS;
#if defined(_SPC58NE84C3_CUT1_)
MC_CGM.AC0_DC4.R = SPC5_CGM_AC0_DC4_BITS;
#endif
MC_CGM.AC6_DC0.R = SPC5_CGM_AC6_DC0_BITS;
MC_CGM.AC7_DC0.R = SPC5_CGM_AC7_DC0_BITS;
MC_CGM.AC12_DC0.R = SPC5_CGM_AC12_DC0_BITS;
MC_CGM.AC12_DC1.R = SPC5_CGM_AC12_DC1_BITS;
MC_CGM.AC12_DC2.R = SPC5_CGM_AC12_DC2_BITS;
MC_CGM.AC12_DC3.R = SPC5_CGM_AC12_DC3_BITS;
MC_CGM.AC12_DC4.R = SPC5_CGM_AC12_DC4_BITS;
/* Setting the clock selectors to their final sources.*/
MC_CGM.AC0_SC.R = SPC5_CGM_AC0_SC_BITS;
MC_CGM.AC3_SC.R = SPC5_CGM_AC3_SC_BITS;
MC_CGM.AC4_SC.R = SPC5_CGM_AC4_SC_BITS;
MC_CGM.AC6_SC.R = SPC5_CGM_AC6_SC_BITS;
MC_CGM.AC7_SC.R = SPC5_CGM_AC7_SC_BITS;
MC_CGM.AC12_SC.R = SPC5_CGM_AC12_SC_BITS;
/* Enables the XOSC in order to check its functionality before proceeding
with the initialization.*/
MC_ME.DRUN_MC.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON |
SPC5_ME_MC_XOSC0ON | SPC5_ME_MC_FLAON_NORMAL |
SPC5_ME_MC_MVRON;
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
/* PLLs initialization, the changes will have effect on mode switch.*/
PLLDIG.PLL0CR.R = 0;
PLLDIG.PLL0DV.R = SPC5_PLL0_DV_RFDPHI1(SPC5_PLL0_RFDPHI1_VALUE) |
SPC5_PLL0_DV_RFDPHI(SPC5_PLL0_RFDPHI_VALUE) |
SPC5_PLL0_DV_PREDIV(SPC5_PLL0_PREDIV_VALUE) |
SPC5_PLL0_DV_MFD(SPC5_PLL0_MFD_VALUE);
PLLDIG.PLL1CR.R = 0;
PLLDIG.PLL1DV.R = SPC5_PLL1_DV_RFDPHI(SPC5_PLL1_RFDPHI_VALUE) |
SPC5_PLL1_DV_MFD(SPC5_PLL1_MFD_VALUE);
/* Run modes initialization, note writes to the MC registers are verified
by a protection mechanism, the operation success is verified at the
end of the sequence.*/
MC_ME.IS.R = 8; /* Resetting I_ICONF status.*/
MC_ME.ME.R = SPC5_ME_ME_BITS;
MC_ME.SAFE_MC.R = SPC5_ME_SAFE_MC_BITS;
MC_ME.DRUN_MC.R = SPC5_ME_DRUN_MC_BITS;
MC_ME.RUN_MC[0].R = SPC5_ME_RUN0_MC_BITS;
MC_ME.RUN_MC[1].R = SPC5_ME_RUN1_MC_BITS;
MC_ME.RUN_MC[2].R = SPC5_ME_RUN2_MC_BITS;
MC_ME.RUN_MC[3].R = SPC5_ME_RUN3_MC_BITS;
MC_ME.HALT0_MC.R = SPC5_ME_HALT0_MC_BITS;
MC_ME.STOP0_MC.R = SPC5_ME_STOP0_MC_BITS;
if (MC_ME.IS.B.I_ICONF) {
/* Configuration rejected.*/
SPC5_CLOCK_FAILURE_HOOK();
}
/* Peripherals run and low power modes initialization.*/
MC_ME.RUN_PC[0].R = SPC5_ME_RUN_PC0_BITS;
MC_ME.RUN_PC[1].R = SPC5_ME_RUN_PC1_BITS;
MC_ME.RUN_PC[2].R = SPC5_ME_RUN_PC2_BITS;
MC_ME.RUN_PC[3].R = SPC5_ME_RUN_PC3_BITS;
MC_ME.RUN_PC[4].R = SPC5_ME_RUN_PC4_BITS;
MC_ME.RUN_PC[5].R = SPC5_ME_RUN_PC5_BITS;
MC_ME.RUN_PC[6].R = SPC5_ME_RUN_PC6_BITS;
MC_ME.RUN_PC[7].R = SPC5_ME_RUN_PC7_BITS;
MC_ME.LP_PC[0].R = SPC5_ME_LP_PC0_BITS;
MC_ME.LP_PC[1].R = SPC5_ME_LP_PC1_BITS;
MC_ME.LP_PC[2].R = SPC5_ME_LP_PC2_BITS;
MC_ME.LP_PC[3].R = SPC5_ME_LP_PC3_BITS;
MC_ME.LP_PC[4].R = SPC5_ME_LP_PC4_BITS;
MC_ME.LP_PC[5].R = SPC5_ME_LP_PC5_BITS;
MC_ME.LP_PC[6].R = SPC5_ME_LP_PC6_BITS;
MC_ME.LP_PC[7].R = SPC5_ME_LP_PC7_BITS;
/* TODO: PFLASH settings initialized for a maximum clock of 200MHz.*/
/* PFLASH.PFCR0.B.B02_APC = 3;
PFLASH.PFCR0.B.B02_WWSC = 3;
PFLASH.PFCR0.B.B02_RWSC = 3;*/
/* Switches again to DRUN mode (current mode) in order to update the
settings.*/
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
#endif /* !SPC5_NO_INIT */
}
/**
* @brief SPC560Pxx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h and
* @p hal_lld.h
* @note This function must be invoked only after the system reset.
*
* @special
*/
void spc_clock_init(void) {
/* Waiting for IRC stabilization before attempting anything else.*/
while (!ME.GS.B.S_RC)
;
#if !SPC5_NO_INIT
#if SPC5_DISABLE_WATCHDOG
/* SWT disabled.*/
SWT.SR.R = 0xC520;
SWT.SR.R = 0xD928;
SWT.CR.R = 0xFF00000A;
#endif
/* SSCM initialization. Setting up the most restrictive handling of
invalid accesses to peripherals.*/
SSCM.ERROR.R = 3; /* PAE and RAE bits. */
/* RGM errors clearing.*/
RGM.FES.R = 0xFFFF;
RGM.DES.R = 0xFFFF;
/* The system must be in DRUN mode on entry, if this is not the case then
it is considered a serious anomaly.*/
if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) {
SPC5_CLOCK_FAILURE_HOOK();
}
#if defined(SPC5_OSC_BYPASS)
/* If the board is equipped with an oscillator instead of a xtal then the
bypass must be activated.*/
CGM.OSC_CTL.B.OSCBYP = TRUE;
#endif /* SPC5_OSC_BYPASS */
/* Setting the various dividers and source selectors.*/
#if SPC5_HAS_AC0
CGM.AC0DC.R = SPC5_CGM_AC0_DC0;
CGM.AC0SC.R = SPC5_AUX0CLK_SRC;
#endif
#if SPC5_HAS_AC1
CGM.AC1DC.R = SPC5_CGM_AC1_DC0;
CGM.AC1SC.R = SPC5_AUX1CLK_SRC;
#endif
#if SPC5_HAS_AC2
CGM.AC2DC.R = SPC5_CGM_AC2_DC0;
CGM.AC2SC.R = SPC5_AUX2CLK_SRC;
#endif
#if SPC5_HAS_AC3
CGM.AC3DC.R = SPC5_CGM_AC3_DC0;
CGM.AC3SC.R = SPC5_AUX3CLK_SRC;
#endif
/* Enables the XOSC in order to check its functionality before proceeding
with the initialization.*/
ME.DRUN.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | SPC5_ME_MC_MVRON;
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
/* Initialization of the FMPLLs settings.*/
CGM.FMPLL[0].CR.R = SPC5_FMPLL0_ODF |
((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
(SPC5_FMPLL0_NDIV_VALUE << 16);
CGM.FMPLL[0].MR.R = 0; /* TODO: Add a setting. */
#if SPC5_HAS_FMPLL1
CGM.FMPLL[1].CR.R = SPC5_FMPLL1_ODF |
((SPC5_FMPLL1_IDF_VALUE - 1) << 26) |
(SPC5_FMPLL1_NDIV_VALUE << 16);
CGM.FMPLL[1].MR.R = 0; /* TODO: Add a setting. */
#endif
/* Run modes initialization.*/
ME.IS.R = 8; /* Resetting I_ICONF status.*/
ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */
ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */
ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */
ME.HALT0.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
ME.STOP0.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
if (ME.IS.B.I_CONF) {
/* Configuration rejected.*/
SPC5_CLOCK_FAILURE_HOOK();
}
/* Peripherals run and low power modes initialization.*/
ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS;
ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS;
ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS;
ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS;
ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS;
ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS;
ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS;
ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS;
ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS;
ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS;
ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS;
ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS;
ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS;
ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS;
ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS;
ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS;
/* CFLASH settings calculated for a maximum clock of 64MHz.*/
CFLASH.PFCR0.B.BK0_APC = 2;
CFLASH.PFCR0.B.BK0_RWSC = 2;
CFLASH.PFCR1.B.BK1_APC = 2;
CFLASH.PFCR1.B.BK1_RWSC = 2;
/* Switches again to DRUN mode (current mode) in order to update the
settings.*/
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
#endif /* !SPC5_NO_INIT */
}
/**
* @brief SPC56ELxx early initialization.
* @note All the involved constants come from the file @p board.h and
* @p hal_lld.h
* @note This function must be invoked only after the system reset.
*
* @special
*/
void spc_clock_init(void) {
/* Waiting for IRC stabilization before attempting anything else.*/
while (!MC_ME.GS.B.S_IRC)
;
#if !SPC5_NO_INIT
#if SPC5_HSM_HANDSHAKE == 1
/* Waits until the HSM notifies it is ready to accept a clock change.*/
while (HSM2HTF != 1)
;
/* Notifies the HSM an acknowledge.*/
HT2HSMF = 1;
#endif
#if SPC5_HSM_HANDSHAKE == 2
/* This protocol does not ensure the Z4 will wait for HSM prescaler will be
* set before changing clock settings --> We may overclock the HSM.
*
* But there are waiting loops that ensure that HSM will have time to
* set it on time. The rationale is that with this protocol, priority
* is given to application core. If the HSM did not start, the goal is
* to not lock the full platfrom.
*/
{
uint32_t counter = 0;
/* If set, clear bit telling that HSML started, may speed up
the HSM startup process.*/
if ((HSM2HTF & WF_GO) == WF_GO)
HSM2HTF = WF_GO;
/* Wait for HSM notification that it changed its prescaler divider and
we can change PLL settings, but for a limited time (4000 loops).*/
counter = 0;
do {
if ((HSM2HTF & CLK_CHG_RDY) == CLK_CHG_RDY)
break;
counter ++;
}
while (counter < 4000);
}
#endif
#if SPC5_DISABLE_WATCHDOG
/* SWTs disabled.*/
SWT_0.SR.R = 0xC520;
SWT_0.SR.R = 0xD928;
SWT_0.CR.R = 0xFF000002;
SWT_1.SR.R = 0xC520;
SWT_1.SR.R = 0xD928;
SWT_1.CR.R = 0xFF000002;
SWT_2.SR.R = 0xC520;
SWT_2.SR.R = 0xD928;
SWT_2.CR.R = 0xFF000002;
SWT_3.SR.R = 0xC520;
SWT_3.SR.R = 0xD928;
SWT_3.CR.R = 0xFF000002;
#endif
/* SSCM initialization from configuration data.*/
SSCM.ERROR.R = SPC5_SSCM_ERROR_INIT;
/* RGM errors clearing.*/
MC_RGM.FES.R = 0xFFFF;
MC_RGM.DES.R = 0xFFFF;
/* The system must be in DRUN mode on entry, if this is not the case then
it is considered a serious anomaly.*/
if (MC_ME.GS.B.S_CURRENT_MODE != SPC5_RUNMODE_DRUN) {
SPC5_CLOCK_FAILURE_HOOK();
}
#if defined(SPC5_OSC_BYPASS)
/* If the board is equipped with an oscillator instead of a crystal then the
bypass must be activated.*/
XOSC.CTL.B.OSCBYP = TRUE;
#endif /* SPC5_OSC_BYPASS */
/* Setting the system dividers to their final values.*/
MC_CGM.SC_DC0.R = SPC5_CGM_SC_DC0_BITS;
MC_CGM.SC_DC1.R = SPC5_CGM_SC_DC1_BITS;
MC_CGM.SC_DC2.R = SPC5_CGM_SC_DC2_BITS;
MC_CGM.SC_DC3.R = SPC5_CGM_SC_DC3_BITS;
/* Setting the auxiliary dividers to their final values.*/
MC_CGM.AC0_DC0.R = SPC5_CGM_AC0_DC0_BITS;
MC_CGM.AC0_DC1.R = SPC5_CGM_AC0_DC1_BITS;
MC_CGM.AC0_DC2.R = SPC5_CGM_AC0_DC2_BITS;
MC_CGM.AC0_DC3.R = SPC5_CGM_AC0_DC3_BITS;
MC_CGM.AC0_DC4.R = SPC5_CGM_AC0_DC4_BITS;
MC_CGM.AC6_DC0.R = SPC5_CGM_AC6_DC0_BITS;
MC_CGM.AC7_DC0.R = SPC5_CGM_AC7_DC0_BITS;
MC_CGM.AC12_DC0.R = SPC5_CGM_AC12_DC0_BITS;
MC_CGM.AC12_DC1.R = SPC5_CGM_AC12_DC1_BITS;
MC_CGM.AC12_DC2.R = SPC5_CGM_AC12_DC2_BITS;
MC_CGM.AC12_DC3.R = SPC5_CGM_AC12_DC3_BITS;
MC_CGM.AC12_DC4.R = SPC5_CGM_AC12_DC4_BITS;
/* Setting the clock selectors to their final sources.*/
MC_CGM.AC0_SC.R = SPC5_CGM_AC0_SC_BITS;
MC_CGM.AC3_SC.R = SPC5_CGM_AC3_SC_BITS;
MC_CGM.AC4_SC.R = SPC5_CGM_AC4_SC_BITS;
MC_CGM.AC6_SC.R = SPC5_CGM_AC6_SC_BITS;
MC_CGM.AC7_SC.R = SPC5_CGM_AC7_SC_BITS;
MC_CGM.AC12_SC.R = SPC5_CGM_AC12_SC_BITS;
/* Enables the XOSC in order to check its functionality before proceeding
with the initialization.*/
MC_ME.DRUN_MC.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON |
SPC5_ME_MC_XOSC0ON | SPC5_ME_MC_FLAON_NORMAL |
SPC5_ME_MC_MVRON;
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
/* PLLs initialization, the changes will have effect on mode switch.*/
PLLDIG.PLL0CR.R = 0;
PLLDIG.PLL0DV.R = SPC5_PLL0_DV_RFDPHI1(SPC5_PLL0_RFDPHI1_VALUE) |
SPC5_PLL0_DV_RFDPHI(SPC5_PLL0_RFDPHI_VALUE) |
SPC5_PLL0_DV_PREDIV(SPC5_PLL0_PREDIV_VALUE) |
SPC5_PLL0_DV_MFD(SPC5_PLL0_MFD_VALUE);
PLLDIG.PLL1CR.R = 0;
PLLDIG.PLL1DV.R = SPC5_PLL1_DV_RFDPHI(SPC5_PLL1_RFDPHI_VALUE) |
SPC5_PLL1_DV_MFD(SPC5_PLL1_MFD_VALUE);
/* Run modes initialization, note writes to the MC registers are verified
by a protection mechanism, the operation success is verified at the
end of the sequence.*/
MC_ME.IS.R = 8; /* Resetting I_ICONF status.*/
MC_ME.ME.R = SPC5_ME_ME_BITS;
MC_ME.SAFE_MC.R = SPC5_ME_SAFE_MC_BITS;
MC_ME.DRUN_MC.R = SPC5_ME_DRUN_MC_BITS;
MC_ME.RUN0_MC.R = SPC5_ME_RUN0_MC_BITS;
MC_ME.RUN1_MC.R = SPC5_ME_RUN1_MC_BITS;
MC_ME.RUN2_MC.R = SPC5_ME_RUN2_MC_BITS;
MC_ME.RUN3_MC.R = SPC5_ME_RUN3_MC_BITS;
MC_ME.HALT0_MC.R = SPC5_ME_HALT0_MC_BITS;
MC_ME.STOP0_MC.R = SPC5_ME_STOP0_MC_BITS;
if (MC_ME.IS.B.I_ICONF) {
/* Configuration rejected.*/
SPC5_CLOCK_FAILURE_HOOK();
}
/* Peripherals run and low power modes initialization.*/
MC_ME.RUN_PC[0].R = SPC5_ME_RUN_PC0_BITS;
MC_ME.RUN_PC[1].R = SPC5_ME_RUN_PC1_BITS;
MC_ME.RUN_PC[2].R = SPC5_ME_RUN_PC2_BITS;
MC_ME.RUN_PC[3].R = SPC5_ME_RUN_PC3_BITS;
MC_ME.RUN_PC[4].R = SPC5_ME_RUN_PC4_BITS;
MC_ME.RUN_PC[5].R = SPC5_ME_RUN_PC5_BITS;
MC_ME.RUN_PC[6].R = SPC5_ME_RUN_PC6_BITS;
MC_ME.RUN_PC[7].R = SPC5_ME_RUN_PC7_BITS;
MC_ME.LP_PC[0].R = SPC5_ME_LP_PC0_BITS;
MC_ME.LP_PC[1].R = SPC5_ME_LP_PC1_BITS;
MC_ME.LP_PC[2].R = SPC5_ME_LP_PC2_BITS;
MC_ME.LP_PC[3].R = SPC5_ME_LP_PC3_BITS;
MC_ME.LP_PC[4].R = SPC5_ME_LP_PC4_BITS;
MC_ME.LP_PC[5].R = SPC5_ME_LP_PC5_BITS;
MC_ME.LP_PC[6].R = SPC5_ME_LP_PC6_BITS;
MC_ME.LP_PC[7].R = SPC5_ME_LP_PC7_BITS;
/* TODO: PFLASH settings initialized for a maximum clock of 200MHz.*/
/* PFLASH.PFCR0.B.B02_APC = 3;
PFLASH.PFCR0.B.B02_WWSC = 3;
PFLASH.PFCR0.B.B02_RWSC = 3;*/
/* Switches again to DRUN mode (current mode) in order to update the
settings.*/
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
#endif /* !SPC5_NO_INIT */
}
