/**
* uDMA Error Handler
*
* \note Need to add the ISR to the NVIC table in the row labeled "uDMA Error"
*
**/
void twe_uDMAErrorHandler(void) {
uint32_t ui32Status;
ui32Status = MAP_uDMAErrorStatusGet();
if(ui32Status) {
MAP_uDMAErrorStatusClear();
g_DMAErrCount++;
}
uDMAChannelDisable(UDMA_CHANNEL_SSI0TX);
SSIDMADisable(SSI0_BASE, SSI_DMA_RX | SSI_DMA_TX);
}
/**************************************************************************************************
* @fn npSpiUdmaPrepareRx
*
* @brief This function is called to set up uDMA for SPI RX. The uDMA and SPI must be
* initialized once already.
*
* input parameters
*
* None.
*
* output parameters
*
* None.
*
* @return None.
**************************************************************************************************
*/
static void npSpiUdmaPrepareRx(void)
{
uint32 ulDummy;
/* Flush the RX FIFO */
while(SSIDataGetNonBlocking(BSP_SPI_SSI_BASE, &ulDummy));
/* Prepare for the next one byte RX DMA */
uDMAChannelTransferSet(UDMA_CH10_SSI0RX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC, SPI_DATA, npSpiBuf, 1);
uDMAChannelEnable(UDMA_CH10_SSI0RX);
/* Disable the TX channel in RX */
SSIDMADisable(BSP_SPI_SSI_BASE, SSI_DMA_TX);
SSIDMAEnable(BSP_SPI_SSI_BASE, SSI_DMA_RX);
}
/**************************************************************************************************
* @fn spi_tx
*
* @brief This function is called to send an SPI packet
*
* input parameters
*
* None.
*
* output parameters
*
* None.
*
* @return None.
**************************************************************************************************
*/
static void spi_tx(uint8* buf)
{
uint8 tx_len = buf[0] + 3;
osal_memcpy(npSpiBuf, buf, tx_len);
/* Disable the RX channel in TX */
SSIDMADisable(BSP_SPI_SSI_BASE, SSI_DMA_RX);
SSIDMAEnable(BSP_SPI_SSI_BASE, SSI_DMA_TX);
/* The transfer buffers and transfer size are now configured using BASIC mode */
uDMAChannelTransferSet(UDMA_CH11_SSI0TX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC, npSpiBuf, SPI_DATA, tx_len);
/* Pull the SRDY pin high */
GPIOPinWrite(HAL_SPI_SRDY_BASE, HAL_SPI_SRDY_PIN, HAL_SPI_SRDY_PIN);
/* Enable the TX channel. */
uDMAChannelEnable(UDMA_CH11_SSI0TX);
}
/*!
* @brief Function that cancels a SPI transfer. Will disable SPI and UDMA modules
* and allow standby.
*
* @pre SPICC26XXDMA_open() has to be called first.
* Calling context: Task
*
* @param handle The SPI_Handle for ongoing transaction.
*/
void SPICC26XXDMA_transferCancel(SPI_Handle handle) {
SPICC26XX_Object *object;
SPI_Transaction *msg;
SPICC26XX_HWAttrs const *hwAttrs;
volatile tDMAControlTable *dmaControlTableEntry;
unsigned int key;
/* Get the pointer to the object and hwAttrs */
object = handle->object;
hwAttrs = handle->hwAttrs;
/* Check if a transfer is in progress */
key = Hwi_disable();
/* Check if there is an active transaction */
if(!(object->currentTransaction)) {
Hwi_restore(key);
return;
}
Hwi_restore(key);
/* Disable the SPI module */
SSIDisable(hwAttrs->baseAddr);
/* Disable SPI TX/RX DMA and clear DMA done interrupt just in case it finished */
SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX);
UDMACC26XX_clearInterrupt(object->udmaHandle, (hwAttrs->rxChannelBitMask) | (hwAttrs->txChannelBitMask));
/* Disable and clear any pending interrupts */
SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR);
SSIIntClear(hwAttrs->baseAddr, SSI_RXOR);
/* Clear out the FIFO by resetting SPI module and re-initting */
HapiResetPeripheral(hwAttrs->baseAddr == SSI0_BASE ? PRCM_PERIPH_SSI0 : PRCM_PERIPH_SSI1);
SPICC26XXDMA_initHw(handle);
/* Release constraint since transaction is done */
threadSafeConstraintRelease((uint32_t)(object->currentTransaction->txBuf));
/* Mark the transaction as failed if we didn't end up here due to a CSN deassertion */
if (object->currentTransaction->status != SPI_TRANSFER_CSN_DEASSERT) {
object->currentTransaction->status = SPI_TRANSFER_FAILED;
}
/* Disable the UDMA channels */
UDMACC26XX_channelDisable(object->udmaHandle, (hwAttrs->rxChannelBitMask) | (hwAttrs->txChannelBitMask));
/* Update the SPI_Transaction.count parameter */
/* rxChannel always finishes after txChannel so remaining bytes of the rxChannel is used to update count */
dmaControlTableEntry = (hwAttrs->baseAddr == SSI0_BASE ? &dmaRxControlTableEntry0 : &dmaRxControlTableEntry1);
object->currentTransaction->count -= UDMACC26XX_GET_TRANSFER_SIZE(dmaControlTableEntry->ui32Control);
/* Use a temporary transaction pointer in case the callback function
* attempts to perform another SPI_transfer call
*/
msg = object->currentTransaction;
/* Indicate we are done with this transfer */
object->currentTransaction = NULL;
Log_print2(Diags_USER1,"SPI:(%p) DMA transaction: %p cancelled",
hwAttrs->baseAddr, (UArg)msg);
/* Perform callback */
object->transferCallbackFxn(handle, msg);
/* Transaction was successfully canceled */
return;
}
/*
* ======== SPICC26XXDMA_hwiFxn ========
* ISR for the SPI when we use the UDMA
*/
static void SPICC26XXDMA_hwiFxn (UArg arg) {
SPI_Transaction *msg;
SPICC26XX_Object *object;
SPICC26XX_HWAttrs const *hwAttrs;
uint32_t intStatus;
/* Get the pointer to the object and hwAttrs */
object = ((SPI_Handle)arg)->object;
hwAttrs = ((SPI_Handle)arg)->hwAttrs;
Log_print1(Diags_USER2, "SPI:(%p) interrupt context start", hwAttrs->baseAddr);
/* Get the interrupt status of the SPI controller */
intStatus = SSIIntStatus(hwAttrs->baseAddr, true);
SSIIntClear(hwAttrs->baseAddr, intStatus);
/* Error handling:
* Overrun in the RX Fifo -> at least one sample in the shift
* register has been discarded */
if (intStatus & SSI_RXOR) {
/* disable the interrupt */
SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR);
/* If the RX overrun occurred during a transfer */
if (object->currentTransaction) {
/* Then cancel the ongoing transfer */
SPICC26XXDMA_transferCancel((SPI_Handle)arg);
}
else {
/* Otherwise disable the SPI and DMA modules and flush FIFOs */
SSIDisable(hwAttrs->baseAddr);
/* Disable SPI TX/RX DMA and clear DMA done interrupt just in case it finished */
SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX);
UDMACC26XX_clearInterrupt(object->udmaHandle, (hwAttrs->rxChannelBitMask) | (hwAttrs->txChannelBitMask));
/* Clear out the FIFO by resetting SPI module and re-initting */
HapiResetPeripheral(hwAttrs->baseAddr == SSI0_BASE ? PRCM_PERIPH_SSI0 : PRCM_PERIPH_SSI1);
SPICC26XXDMA_initHw((SPI_Handle)arg);
}
Log_print1(Diags_USER1, "RX FIFO overrun occurred in SPI: (%p) !\n", hwAttrs->baseAddr);
}
else {
/* Determine if the TX DMA channel has completed... */
if (UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->txChannelBitMask)) {
/* Disable SPI TX DMA and clear DMA done interrupt. */
SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX);
UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->txChannelBitMask);
/* All transfers will set up both TX and RX DMA channels and both will finish.
* Even if the transaction->rxBuf == NULL, it will setup a dummy RX transfer to
* a scratch memory location which is then discarded.
* Therefore all cleanup is only done when the RX DMA channel has completed,
* since it will always run at some point after the TX DMA channel has completed.
*/
}
/* Determine if the RX DMA channel has completed... */
if(UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->rxChannelBitMask)) {
/* Disable SPI RX DMA and clear DMA done interrupt. */
SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_RX);
UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->rxChannelBitMask);
/* Transaction is complete */
object->currentTransaction->status = SPI_TRANSFER_COMPLETED;
/* Use a temporary transaction pointer in case the callback function
* attempts to perform another SPI_transfer call
*/
msg = object->currentTransaction;
Log_print2(Diags_USER1,"SPI:(%p) DMA transaction: %p complete",
hwAttrs->baseAddr, (UArg)msg);
/* Release constraint since transaction is done */
threadSafeConstraintRelease((uint32_t)(object->currentTransaction->txBuf));
/* Indicate we are done with this transfer */
object->currentTransaction = NULL;
/* Perform callback */
object->transferCallbackFxn((SPI_Handle)arg, msg);
}
}
Log_print1(Diags_USER2, "SPI:(%p) interrupt context end",
hwAttrs->baseAddr);
}
