/**
* @brief Initialize RTT module
*
* The RTT is running at 32768 Hz by default, i.e. @ XOSC32K frequency without
* divider. There are 2 cascaded dividers in the clock path:
*
* - GCLK_GENDIV_DIV(n): between 1 and 31
* - RTC_MODE0_CTRL_PRESCALER_DIVn: between 1 and 1024, see defines in `component_rtc.h`
*
* However the division scheme of GCLK_GENDIV_DIV can be changed by setting
* GCLK_GENCTRL_DIVSEL:
*
* - GCLK_GENCTRL_DIVSEL = 0: Clock divided by GENDIV.DIV (default)
* - GCLK_GENCTRL_DIVSEL = 1: Clock divided by 2^( GENDIV.DIV + 1 )
*/
void rtt_init(void)
{
RtcMode0 *rtcMode0 = &(RTT_DEV);
/* Turn on power manager for RTC */
PM->APBAMASK.reg |= PM_APBAMASK_RTC;
/* RTC uses External 32,768KHz Oscillator because OSC32K isn't accurate
* enough (p1075/1138). Also keep running in standby. */
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ONDEMAND |
SYSCTRL_XOSC32K_EN32K |
SYSCTRL_XOSC32K_XTALEN |
SYSCTRL_XOSC32K_STARTUP(6) |
#if RTT_RUNSTDBY
SYSCTRL_XOSC32K_RUNSTDBY |
#endif
SYSCTRL_XOSC32K_ENABLE;
/* Setup clock GCLK2 with divider 1 */
GCLK->GENDIV.reg = GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(1);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* Enable GCLK2 with XOSC32K as source. Use divider without modification
* and keep running in standby. */
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(2) |
GCLK_GENCTRL_GENEN |
#if RTT_RUNSTDBY
GCLK_GENCTRL_RUNSTDBY |
#endif
GCLK_GENCTRL_SRC_XOSC32K;
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* Connect GCLK2 to RTC */
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN_GCLK2 |
GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_ID(RTC_GCLK_ID);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* Disable RTC */
rtt_poweroff();
/* Reset RTC */
rtcMode0->CTRL.bit.SWRST = 1;
while (rtcMode0->STATUS.bit.SYNCBUSY || rtcMode0->CTRL.bit.SWRST) {}
/* Configure as 32bit counter with no prescaler and no clear on match compare */
rtcMode0->CTRL.reg = RTC_MODE0_CTRL_MODE_COUNT32 |
RTT_PRESCALER;
while (rtcMode0->STATUS.bit.SYNCBUSY) {}
/* Setup interrupt */
NVIC_EnableIRQ(RTT_IRQ);
/* Enable RTC */
rtt_poweron();
}
void
SystemInit(void)
{
// Setup flash to work with 48Mhz clock
NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_RWS_HALF;
// Enable external 32Khz crystal
uint32_t val = (SYSCTRL_XOSC32K_STARTUP(6)
| SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K);
SYSCTRL->XOSC32K.reg = val;
SYSCTRL->XOSC32K.reg = val | SYSCTRL_XOSC32K_ENABLE;
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY))
;
// Reset GCLK
GCLK->CTRL.reg = GCLK_CTRL_SWRST;
while (GCLK->CTRL.reg & GCLK_CTRL_SWRST)
;
// Route 32Khz clock to DFLL48M
GCLK->GENDIV.reg = GCLK_GENDIV_ID(CLK_32K);
GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(CLK_32K)
| GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_GENEN);
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_ID(MCLK_DFLL48M)
| GCLK_CLKCTRL_GEN(CLK_32K) | GCLK_CLKCTRL_CLKEN);
// Configure DFLL48M clock
SYSCTRL->DFLLCTRL.reg = 0;
uint32_t mul = DIV_ROUND_CLOSEST(CONFIG_CLOCK_FREQ, CLK_32K_FREQ);
SYSCTRL->DFLLMUL.reg = (SYSCTRL_DFLLMUL_CSTEP(31)
| SYSCTRL_DFLLMUL_FSTEP(511)
| SYSCTRL_DFLLMUL_MUL(mul));
SYSCTRL->DFLLCTRL.reg = (SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_WAITLOCK
| SYSCTRL_DFLLCTRL_QLDIS
| SYSCTRL_DFLLCTRL_ENABLE);
uint32_t ready = (SYSCTRL_PCLKSR_DFLLRDY | SYSCTRL_PCLKSR_DFLLLCKC
| SYSCTRL_PCLKSR_DFLLLCKF);
while ((SYSCTRL->PCLKSR.reg & ready) != ready)
;
// Switch main clock to DFLL48M clock
GCLK->GENDIV.reg = GCLK_GENDIV_ID(CLK_MAIN);
GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(CLK_MAIN)
| GCLK_GENCTRL_SRC_DFLL48M
| GCLK_GENCTRL_IDC | GCLK_GENCTRL_GENEN);
}
void rtc_init(void)
{
RtcMode2 *rtcMode2 = &(RTC_DEV);
/* Turn on power manager for RTC */
PM->APBAMASK.reg |= PM_APBAMASK_RTC;
/* RTC uses External 32,768KHz Oscillator (OSC32K isn't accurate enough p1075/1138)*/
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ONDEMAND |
SYSCTRL_XOSC32K_EN32K |
SYSCTRL_XOSC32K_XTALEN |
SYSCTRL_XOSC32K_STARTUP(6) |
SYSCTRL_XOSC32K_ENABLE;
/* Setup clock GCLK2 with OSC32K divided by 32 */
GCLK->GENDIV.reg = GCLK_GENDIV_ID(2)|GCLK_GENDIV_DIV(4);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_ID(2) | GCLK_GENCTRL_DIVSEL );
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
GCLK->CLKCTRL.reg = (uint32_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK2 | (RTC_GCLK_ID << GCLK_CLKCTRL_ID_Pos)));
while (GCLK->STATUS.bit.SYNCBUSY);
/* DISABLE RTC MASTER */
while (rtcMode2->STATUS.reg & RTC_STATUS_SYNCBUSY);
rtc_poweroff();
/* Reset RTC */
while (rtcMode2->STATUS.bit.SYNCBUSY);
rtcMode2->CTRL.reg= RTC_MODE2_CTRL_SWRST;
while (rtcMode2->STATUS.bit.SYNCBUSY);
/* RTC config with RTC_MODE2_CTRL_CLKREP = 0 (24h) */
rtcMode2->CTRL.reg = RTC_MODE2_CTRL_PRESCALER_DIV1024|RTC_MODE2_CTRL_MODE_CLOCK;
while (rtcMode2->STATUS.bit.SYNCBUSY);
rtcMode2->INTENSET.reg = RTC_MODE2_INTENSET_OVF;
while (rtcMode2->STATUS.bit.SYNCBUSY);
rtc_poweron();
}
void main_clock_init (void)
{
/* enable the xosc32k and set the start up time */
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP(6) | SYSCTRL_XOSC32K_EN32K |
SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_ENABLE;
while (!SYSCTRL->PCLKSR.bit.XOSC32KRDY){}
/* enable the generic clock GEN1 and configure the XOSC32K as clock source for it */
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID_GCLK1 | GCLK_GENCTRL_SRC_XOSC32K |
GCLK_GENCTRL_GENEN | GCLK_GENCTRL_IDC;
while (GCLK->STATUS.bit.SYNCBUSY){}
/* Enable the DFLL and set the operation mode as closed loop */
SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE | SYSCTRL_DFLLCTRL_MODE;
while(!SYSCTRL->PCLKSR.bit.DFLLRDY){}
/* Load the Multiply factor, Coarse Step and fine Step for DFLL */
SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP(0x1F/4) | SYSCTRL_DFLLMUL_FSTEP(0xFF/4) |
SYSCTRL_DFLLMUL_MUL(1465);
/* Enable the Generic Clock GEN 1 as DFLL48 as Reference */
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK1 | GCLK_CLKCTRL_ID(0);
/* wait for fine lock */
while(!SYSCTRL->PCLKSR.bit.DFLLLCKF){}
/* Set the NVM Read Wait States to 1, Since the operating frequency 48 MHz */
NVMCTRL->CTRLB.bit.RWS = 1;
/* Enable the Generic Clock 0 and Configure the DFLL as Clock Source for it*/
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID_GCLK0 | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_GENEN |
GCLK_GENCTRL_IDC;
while(GCLK->STATUS.bit.SYNCBUSY){}
}
void SystemInit( void )
{
/* Set 1 Flash Wait State for 48MHz, cf tables 20.9 and 35.27 in SAMD21 Datasheet */
NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val ;
/* Turn on the digital interface clock */
PM->APBAMASK.reg |= PM_APBAMASK_GCLK ;
/* ----------------------------------------------------------------------------------------------
* 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator)
*/
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP( 0x6u ) | /* cf table 15.10 of product datasheet in chapter 15.8.6 */
SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K ;
SYSCTRL->XOSC32K.bit.ENABLE = 1 ; /* separate call, as described in chapter 15.6.3 */
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY) == 0 )
{
/* Wait for oscillator stabilization */
}
/* Software reset the module to ensure it is re-initialized correctly */
/* Note: Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete.
* CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete, as described in chapter 13.8.1
*/
GCLK->CTRL.reg = GCLK_CTRL_SWRST ;
while ( (GCLK->CTRL.reg & GCLK_CTRL_SWRST) && (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) )
{
/* Wait for reset to complete */
}
/* ----------------------------------------------------------------------------------------------
* 2) Put XOSC32K as source of Generic Clock Generator 1
*/
GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) ; // Generic Clock Generator 1
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
/* Write Generic Clock Generator 1 configuration */
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) | // Generic Clock Generator 1
GCLK_GENCTRL_SRC_XOSC32K | // Selected source is External 32KHz Oscillator
// GCLK_GENCTRL_OE | // Output clock to a pin for tests
GCLK_GENCTRL_GENEN ;
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
/* ----------------------------------------------------------------------------------------------
* 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
*/
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GENERIC_CLOCK_MULTIPLEXER_DFLL48M ) | // Generic Clock Multiplexer 0
GCLK_CLKCTRL_GEN_GCLK1 | // Generic Clock Generator 1 is source
GCLK_CLKCTRL_CLKEN ;
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
/* ----------------------------------------------------------------------------------------------
* 4) Enable DFLL48M clock
*/
/* DFLL Configuration in Closed Loop mode, cf product datasheet chapter 15.6.7.1 - Closed-Loop Operation */
/* Remove the OnDemand mode, Bug http://avr32.icgroup.norway.atmel.com/bugzilla/show_bug.cgi?id=9905 */
SYSCTRL->DFLLCTRL.bit.ONDEMAND = 0 ;
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
{
/* Wait for synchronization */
}
SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 31 ) | // Coarse step is 31, half of the max value
SYSCTRL_DFLLMUL_FSTEP( 511 ) | // Fine step is 511, half of the max value
SYSCTRL_DFLLMUL_MUL( (__CLOCK_48MHz/__CLOCK_32KHz) ) ; // External 32KHz is the reference
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
{
/* Wait for synchronization */
}
/* Write full configuration to DFLL control register */
SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE | /* Enable the closed loop mode */
SYSCTRL_DFLLCTRL_WAITLOCK |
SYSCTRL_DFLLCTRL_QLDIS ; /* Disable Quick lock */
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
{
/* Wait for synchronization */
}
/* Enable the DFLL */
SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0 )
{
/* Wait for locks flags */
}
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
{
/* Wait for synchronization */
}
/* ----------------------------------------------------------------------------------------------
* 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
*/
GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_MAIN ) ; // Generic Clock Generator 0
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
/* Write Generic Clock Generator 0 configuration */
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_MAIN ) | // Generic Clock Generator 0
GCLK_GENCTRL_SRC_DFLL48M | // Selected source is DFLL 48MHz
// GCLK_GENCTRL_OE | // Output clock to a pin for tests
GCLK_GENCTRL_IDC | // Set 50/50 duty cycle
GCLK_GENCTRL_GENEN ;
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
/* ----------------------------------------------------------------------------------------------
* 6) Modify PRESCaler value of OSC8M to have 8MHz
*/
SYSCTRL->OSC8M.bit.PRESC = SYSCTRL_OSC8M_PRESC_0_Val ;
SYSCTRL->OSC8M.bit.ONDEMAND = 0 ;
/* ----------------------------------------------------------------------------------------------
* 7) Put OSC8M as source for Generic Clock Generator 3
*/
GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) ; // Generic Clock Generator 3
/* Write Generic Clock Generator 3 configuration */
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) | // Generic Clock Generator 3
GCLK_GENCTRL_SRC_OSC8M | // Selected source is RC OSC 8MHz (already enabled at reset)
// GCLK_GENCTRL_OE | // Output clock to a pin for tests
GCLK_GENCTRL_GENEN ;
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
/* ----------------------------------------------------------------------------------------------
* 8) Put OSC8M as source for Generic Clock Generator 2, with freq/8
*/
GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_OSC1M ) | 8 << 8; // Generic Clock Generator 4
/* Write Generic Clock Generator 3 configuration */
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC1M ) | // Generic Clock Generator 4
GCLK_GENCTRL_SRC_OSC8M | // Selected source is RC OSC 8MHz (already enabled at reset)
// GCLK_GENCTRL_OE | // Output clock to a pin for tests
GCLK_GENCTRL_GENEN ;
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
/*
* Now that all system clocks are configured, we can set CPU and APBx BUS clocks.
* There values are normally the one present after Reset.
*/
PM->CPUSEL.reg = PM_CPUSEL_CPUDIV_DIV1 ;
PM->APBASEL.reg = PM_APBASEL_APBADIV_DIV1_Val ;
PM->APBBSEL.reg = PM_APBBSEL_APBBDIV_DIV1_Val ;
PM->APBCSEL.reg = PM_APBCSEL_APBCDIV_DIV1_Val ;
SystemCoreClock=__CLOCK_48MHz ;
return;
}
/**
* \brief Initializes clock generators
*
* All GCLK generators are running when this function returns.
*/
void _sysctrl_init_sources(void)
{
void *hw = (void *)SYSCTRL;
uint16_t calib;
#if CONF_XOSC32K_CONFIG == 1
hri_sysctrl_write_XOSC32K_reg(hw,
( CONF_XOSC32K_WRTLOCK << SYSCTRL_XOSC32K_WRTLOCK_Pos ) |
SYSCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) |
( CONF_XOSC32K_RUNSTDBY << SYSCTRL_XOSC32K_RUNSTDBY_Pos ) |
( CONF_XOSC32K_AAMPEN << SYSCTRL_XOSC32K_AAMPEN_Pos ) |
( CONF_XOSC32K_EN1K << SYSCTRL_XOSC32K_EN1K_Pos ) |
( CONF_XOSC32K_EN32K << SYSCTRL_XOSC32K_EN32K_Pos ) |
( CONF_XOSC32K_XTALEN << SYSCTRL_XOSC32K_XTALEN_Pos ) |
( CONF_XOSC32K_ENABLE << SYSCTRL_XOSC32K_ENABLE_Pos ));
#endif
#if CONF_XOSC_CONFIG == 1
hri_sysctrl_write_XOSC_reg(hw, SYSCTRL_XOSC_STARTUP(
CONF_XOSC_STARTUP) |
( CONF_XOSC_AMPGC << SYSCTRL_XOSC_AMPGC_Pos ) |
SYSCTRL_XOSC_GAIN(CONF_XOSC_GAIN) |
( CONF_XOSC_RUNSTDBY << SYSCTRL_XOSC_RUNSTDBY_Pos ) |
( CONF_XOSC_XTALEN << SYSCTRL_XOSC_XTALEN_Pos ) |
( CONF_XOSC_ENABLE << SYSCTRL_XOSC_ENABLE_Pos ));
#endif
#if CONF_OSC8M_CONFIG == 1
calib = hri_sysctrl_read_OSC8M_CALIB_bf(hw);
hri_sysctrl_write_OSC8M_reg(hw,
SYSCTRL_OSC8M_FRANGE(hri_sysctrl_read_OSC8M_FRANGE_bf(hw)) |
# if CONF_OSC8M_OVERWRITE_CALIBRATION == 1
SYSCTRL_OSC8M_CALIB(CONF_OSC8M_CALIB) |
# else
SYSCTRL_OSC8M_CALIB(calib) |
# endif
SYSCTRL_OSC8M_PRESC(CONF_OSC8M_PRESC) |
( CONF_OSC8M_RUNSTDBY << SYSCTRL_OSC8M_RUNSTDBY_Pos ) |
( CONF_OSC8M_ENABLE << SYSCTRL_OSC8M_ENABLE_Pos ));
#endif
#if CONF_OSC32K_CONFIG == 1
calib = SYSCTRL->OSC32K.bit.CALIB;
hri_sysctrl_write_OSC32K_reg(hw,
# if CONF_OSC32K_OVERWRITE_CALIBRATION == 1
SYSCTRL_OSC32K_CALIB(CONF_OSC32K_CALIB) |
# else
SYSCTRL_OSC32K_CALIB(calib) |
# endif
( CONF_OSC32K_WRTLOCK << SYSCTRL_OSC32K_WRTLOCK_Pos ) |
SYSCTRL_OSC32K_STARTUP(CONF_OSC32K_STARTUP) |
( CONF_OSC32K_RUNSTDBY << SYSCTRL_OSC32K_RUNSTDBY_Pos ) |
( CONF_OSC32K_EN1K << SYSCTRL_OSC32K_EN1K_Pos ) |
( CONF_OSC32K_EN32K << SYSCTRL_OSC32K_EN32K_Pos ) |
( 1 << SYSCTRL_OSC32K_ENABLE_Pos ));
#else
/* Enable OSC32K anyway since GCLK configuration may need it to sync */
hri_sysctrl_set_OSC32K_ENABLE_bit(hw);
#endif
#if CONF_OSCULP32K_CONFIG == 1
hri_sysctrl_write_OSCULP32K_reg(hw,
# if OSC32K_OVERWRITE_CALIBRATION == 1
SYSCTRL_OSCULP32K_CALIB(OSCULP32K_CALIB) |
# else
SYSCTRL_OSCULP32K_CALIB(calib) |
# endif
( CONF_OSC32K_WRTLOCK << SYSCTRL_OSCULP32K_WRTLOCK_Pos ));
#endif
#if CONF_XOSC32K_CONFIG == 1
# if CONF_XOSC32K_ENABLE == 1
while (!hri_sysctrl_get_PCLKSR_XOSC32KRDY_bit(hw)) {;
}
# endif
# if CONF_XOSC32K_ONDEMAND == 1
hri_sysctrl_set_XOSC32K_ONDEMAND_bit(hw);
# endif
#endif
#if CONF_XOSC_CONFIG == 1
# if CONF_XOSC_ENABLE == 1
while (!hri_sysctrl_get_PCLKSR_XOSCRDY_bit(hw)) {;
}
# endif
# if CONF_XOSC_ONDEMAND == 1
hri_sysctrl_set_XOSC_ONDEMAND_bit(hw);
# endif
#endif
#if CONF_OSC32K_CONFIG == 1
# if CONF_OSC32K_ENABLE == 1
while (!hri_sysctrl_get_PCLKSR_OSC32KRDY_bit(hw)) {;
}
# endif
# if CONF_OSC32K_ONDEMAND == 1
hri_sysctrl_set_OSC32K_ONDEMAND_bit(hw);
# endif
#endif
#if CONF_OSC8M_CONFIG == 1
# if CONF_OSC8M_ENABLE == 1
while (!hri_sysctrl_get_PCLKSR_OSC8MRDY_bit(hw)) {;
}
# endif
# if CONF_OSC8M_ONDEMAND == 1
hri_sysctrl_set_OSC8M_ONDEMAND_bit(hw);
# endif
#endif
(void)calib, (void)hw;
}
