void patch_func (void)
{
//0x00032795 cmp_abs_time
SetWord32(PATCH_ADDR0_REG, 0x00032794);
SetWord32(PATCH_DATA0_REG, 0x6889df00); //cmp_abs_time svc 0
//0x0002a32b l2cc_pdu_recv_ind_handler (atts)
SetWord32(PATCH_ADDR1_REG, 0x0002a328);
SetWord32(PATCH_DATA1_REG, 0xdf014770); //l2cc_pdu_recv_ind_handler svc 1
//0x0002ca1f smpc_send_pairing_req_ind
SetWord32(PATCH_ADDR2_REG, 0x0002ca1c);
SetWord32(PATCH_DATA2_REG, 0xdf02bdf8); //smpc_send_pairing_req_ind svc 2
//0x0002cb43 smpc_check_pairing_feat
SetWord32(PATCH_ADDR3_REG, 0x0002cb40);
SetWord32(PATCH_DATA3_REG, 0xdf03e7f5); //smpc_check_pairing_feat svc 3
//0x0002d485 smpc_pairing_cfm_handler
SetWord32(PATCH_ADDR4_REG, 0x0002d484);
SetWord32(PATCH_DATA4_REG, 0xb089df04); //smpc_pairing_cfm_handler svc 4
NVIC_DisableIRQ(SVCall_IRQn);
NVIC_SetPriority(SVCall_IRQn, 0);
NVIC_EnableIRQ(SVCall_IRQn);
}
/**
****************************************************************************************
* @brief Read low power clock selection from
*
* The Hclk and Pclk are set
****************************************************************************************
*/
void select_lp_clk()
{
#if (CFG_LP_CLK == LP_CLK_FROM_OTP)
int cnt = 100000;
# ifndef APP_BOOT_FROM_OTP
#define XPMC_MODE_MREAD 0x1
uint16_t *lp_clk = (uint16_t *)(0x40000 + LP_CLK_OTP_OFFSET); //where in OTP header is IQ_Trim
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 1); //enable OTP clock
while ((GetWord16(ANA_STATUS_REG) & LDO_OTP_OK) != LDO_OTP_OK && cnt--)
/* Just wait */;
// set OTP in read mode
SetWord32(OTPC_MODE_REG, XPMC_MODE_MREAD);
# else
uint16_t *lp_clk = (uint16_t *)(0x20000000 + LP_CLK_OTP_OFFSET); //where in OTP header is IQ_Trim
# endif //APP_BOOT_FROM_OTP
lp_clk_sel = (*lp_clk);
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 0); //disable OTP clock
#else //CFG_LP_CLK
lp_clk_sel = CFG_LP_CLK;
#endif
}
void nvds_read_bdaddr_from_otp()
{
const uint16_t BDADDR_OFFSET = 0x7fd4; // offset of BD address in OTP header
uint8_t *otp_bdaddr;
if (!APP_BOOT_FROM_OTP)
{
int cnt = 100000;
#define XPMC_MODE_MREAD 0x1
otp_bdaddr = (uint8_t *)0x40000 + BDADDR_OFFSET; //where in OTP header is BDADDR
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 1); // enable OTP clock
while ((GetWord16(ANA_STATUS_REG) & LDO_OTP_OK) != LDO_OTP_OK && cnt--)
/* Just wait */;
// set OTP in read mode
SetWord32(OTPC_MODE_REG, XPMC_MODE_MREAD);
}
else
otp_bdaddr = (uint8_t *)0x20000000 + BDADDR_OFFSET; //where in OTP header is BDADDR
#if BLE_JWAOO_TOY_SERVER
memcpy(jwaoo_toy_device_data.bd_addr, otp_bdaddr, sizeof(jwaoo_toy_device_data.bd_addr));
#else
memcpy(&dev_bdaddr, otp_bdaddr, sizeof(dev_bdaddr));
#endif
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 0); //disable OTP clock
}
void nvds_read_bdaddr_from_otp()
{
#ifdef BDADDR_FROM_OTP
#ifndef APP_BOOT_FROM_OTP
int cnt=100000;
#define XPMC_MODE_MREAD 0x1
uint8_t *otp_bdaddr = (uint8_t *)0x40000 + BDADDR_FROM_OTP; //where in OTP header is BDADDR
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 1); // enable OTP clock
while ((GetWord16(ANA_STATUS_REG) & LDO_OTP_OK) != LDO_OTP_OK && cnt--)
/* Just wait */;
// set OTP in read mode
SetWord32 (OTPC_MODE_REG,XPMC_MODE_MREAD);
#else
uint8_t *otp_bdaddr = (uint8_t *)0x20000000 + BDADDR_FROM_OTP; //where in OTP header is BDADDR
#endif
memcpy(&dev_bdaddr, otp_bdaddr, sizeof(dev_bdaddr));
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 0); //disable OTP clock
#ifdef SUPPORT_1_8_V
SetBits16(DCDC_CTRL2_REG, DCDC_VBAT3V_LEV, 0x0); ///--Support 1.8V boot
#endif
#endif
}
bool uart_sps_flow_off(void)
{
bool flow_off = true;
do
{
// First check if no transmission is ongoing
if ((uart_temt_getf() == 0) || (uart_thre_getf() == 0) || !uart_sps_is_rx_fifo_empty())
{
flow_off = false;
break;
}
// Configure modem (HW flow control disable, 'RTS flow off')
SetWord32(UART_MCR_REG, GetWord32(UART_MCR_REG) & (~UART_RTS));
//SetWord32(UART_MCR_REG, 0);
// Wait for 1 character duration to ensure host has not started a transmission at the
// same time
for (int i=0;i<UART_WAIT_BYTE_COUNTER;i++);
// Check if data has been received during wait time
if(!uart_sps_is_rx_fifo_empty())
{
// Re-enable UART flow
uart_sps_flow_on();
// We failed stopping the flow
flow_off = false;
}
} while(false);
return (flow_off);
}
void iq_trim_from_otp()
{
#ifdef IQTRIM_FROM_OTP
#ifndef APP_BOOT_FROM_OTP
int cnt=100000;
#define XPMC_MODE_MREAD 0x1
uint16_t *iqtrim = (uint16_t *)(0x40000 + IQTRIM_FROM_OTP); //where in OTP header is IQ_Trim
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 1); // enable OTP clock
while ((GetWord16(ANA_STATUS_REG) & LDO_OTP_OK) != LDO_OTP_OK && cnt--)
/* Just wait */;
// set OTP in read mode
SetWord32 (OTPC_MODE_REG,XPMC_MODE_MREAD);
#else
uint16_t *iqtrim = (uint16_t *)(0x20000000 + IQTRIM_FROM_OTP); //where in OTP header is IQ_Trim
#endif
iq_trim_bias_ctrl1_reg = *iqtrim++;
iq_trim_rf_mixer_ctrl1_reg = *iqtrim;
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 0); //disable OTP clock
#ifdef SUPPORT_1_8_V
SetBits16(DCDC_CTRL2_REG, DCDC_VBAT3V_LEV, 0x0); ///--Support 1.8V boot
#endif
#endif
}
void hci_xtal_trim_cmd(uint8_t* ptr_data)
{
uint16_t delta = ptr_data[2]<<8|ptr_data[1];
struct msg_xtal_trim_cfm s;
uint8_t* bufptr;
s.packet_type = HCI_EVT_MSG_TYPE;
s.event_code = HCI_CMD_CMPL_EVT_CODE;
s.length = 5;
s.param0 = 0x0001;
if(ptr_data[0] == 0)
s.xtrim_val = GetWord16(CLK_FREQ_TRIM_REG);
else
s.xtrim_val = 0x0;
s.param_opcode = HCI_XTAL_TRIM_CMD_OPCODE;
bufptr = (uint8_t*)&s;
uart_write(bufptr,sizeof(struct msg_xtal_trim_cfm),NULL);
if(ptr_data[0] == 1)
{
set_XTAL_trim_reg(delta);
}
else if(ptr_data[0] == 2)
{
SetWord32(TEST_CTRL_REG, 1);
SetWord32(P05_MODE_REG, 0x300);
}
else if(ptr_data[0] == 3)
{
uint16_t reg_value = GetWord16(CLK_FREQ_TRIM_REG);
if (reg_value <= 0xFFFF - delta)
set_XTAL_trim_reg(reg_value + delta);
//for (i=0; i<400; i++); //wait for at least 200us
}
else if(ptr_data[0] == 4)
{
uint16_t reg_value = GetWord16(CLK_FREQ_TRIM_REG);
if (reg_value >= delta)
set_XTAL_trim_reg(reg_value - delta);
//for (i=0; i<400; i++); //wait for at least 200us
}
else if(ptr_data[0] == 5)
{
SetWord32(TEST_CTRL_REG, 0);
SetWord32(P05_MODE_REG, 0x200);
}
}
void rf_regs(void)
{
SetWord32( BLE_RADIOPWRUPDN_REG, PREF_BLE_RADIOPWRUPDN_REG);
SetWord16( RF_LF_CTRL_REG, PREF_RF_LF_CTRL_REG);
SetWord16( RF_CP_CTRL_REG, PREF_RF_CP_CTRL_REG);
SetWord16( RF_REF_OSC_REG, PREF_RF_REF_OSC_REG);
SetWord16( RF_ENABLE_CONFIG1_REG, PREF_RF_ENABLE_CONFIG1_REG);
SetWord16( RF_ENABLE_CONFIG2_REG, PREF_RF_ENABLE_CONFIG2_REG);
SetWord16( RF_ENABLE_CONFIG6_REG, PREF_RF_ENABLE_CONFIG6_REG);
SetWord16( RF_ENABLE_CONFIG9_REG, PREF_RF_ENABLE_CONFIG9_REG);
SetWord16( RF_ENABLE_CONFIG10_REG, PREF_RF_ENABLE_CONFIG10_REG);
SetWord16( RF_ENABLE_CONFIG13_REG, PREF_RF_ENABLE_CONFIG13_REG);
SetWord16( RF_ENABLE_CONFIG14_REG, PREF_RF_ENABLE_CONFIG14_REG);
SetWord16( RF_ENABLE_CONFIG19_REG, PREF_RF_ENABLE_CONFIG19_REG);
SetWord16( RF_CNTRL_TIMER_3_REG, PREF_RF_CNTRL_TIMER_3_REG);
SetWord16( RF_CNTRL_TIMER_4_REG, PREF_RF_CNTRL_TIMER_4_REG);
SetWord16( RF_CNTRL_TIMER_8_REG, PREF_RF_CNTRL_TIMER_8_REG);
SetWord16( RF_CNTRL_TIMER_9_REG, PREF_RF_CNTRL_TIMER_9_REG);
SetWord16( RF_CNTRL_TIMER_10_REG, PREF_RF_CNTRL_TIMER_10_REG);
SetWord16( RF_CNTRL_TIMER_11_REG, PREF_RF_CNTRL_TIMER_11_REG);
SetWord16( RF_CNTRL_TIMER_12_REG, PREF_RF_CNTRL_TIMER_12_REG);
SetWord16( RF_CNTRL_TIMER_13_REG, PREF_RF_CNTRL_TIMER_13_REG);
SetWord16( RF_CNTRL_TIMER_14_REG, PREF_RF_CNTRL_TIMER_14_REG);
//SetWord16( BIAS_CTRL1_REG, PREF_BIAS_CTRL1_REG);
SetWord16( RF_DEM_CTRL_REG, PREF_RF_DEM_CTRL_REG);
SetWord16( RF_AGC_CTRL1_REG, PREF_RF_AGC_CTRL1_REG);
SetWord16( RF_AGC_CTRL2_REG, PREF_RF_AGC_CTRL2_REG);
SetWord16( RF_AGC_LUT_23_REG, PREF_RF_AGC_LUT_23_REG);
SetWord16( RF_AFC_CTRL_REG, PREF_RF_AFC_CTRL_REG);
SetWord16( RF_DC_OFFSET_CTRL2_REG, PREF_RF_DC_OFFSET_CTRL2_REG);
SetWord16( RF_DC_OFFSET_CTRL3_REG, PREF_RF_DC_OFFSET_CTRL3_REG);
SetWord16( RF_DC_OFFSET_CTRL4_REG, PREF_RF_DC_OFFSET_CTRL4_REG);
SetWord16( RF_PA_CTRL_REG, PREF_RF_PA_CTRL_REG);
SetWord16( RF_SYNTH_CTRL2_REG, PREF_RF_SYNTH_CTRL2_REG);
#if (LUT_PATCH_ENABLED)
SetBits16( RF_VCOCAL_CTRL_REG, VCO_FREQTRIM_SEL, 0x1);
#else
SetWord16( RF_VCOCAL_CTRL_REG, PREF_RF_VCOCAL_CTRL_REG);
#endif
#if (MGCKMODA_PATCH_ENABLED)
SetWord16( RF_MGAIN_CTRL_REG, 0x9503); // GAUSS_GAIN_SEL=0x1 and KMOD_ALPHA=3 to have some range above/below the final SW based KMOD_ALPHA value
#else
SetWord16( RF_MGAIN_CTRL_REG, PREF_RF_MGAIN_CTRL_REG);
#endif
SetWord16( RF_VCO_CALCAP_BIT14_REG, PREF_RF_VCO_CALCAP_BIT14_REG);
SetWord16( RF_LF_RES_CTRL_REG, PREF_RF_LF_RES_CTRL_REG);
SetWord16( RF_MGAIN_CTRL2_REG, PREF_RF_MGAIN_CTRL2_REG);
SetWord16(RF_MIXER_CTRL1_REG, iq_trim_rf_mixer_ctrl1_reg);
SetWord16(BIAS_CTRL1_REG, iq_trim_bias_ctrl1_reg);
// Near Field Mode Register Enable
#ifdef NEAR_FIELD_MODE_ENABLED
SetWord16(RF_ENABLE_CONFIG13_REG, 0x0030);
#endif
}
void uart_flow_on_func(void)
{
// Configure modem (HW flow control enable)
#if 0
// Configure modem (HW flow control enable)
uart_mcr_pack(UART_ENABLE, // extfunc
UART_ENABLE, // autorts
UART_ENABLE, // autocts
UART_ENABLE); // rts
#endif
SetWord32(UART_MCR_REG, UART_AFCE|UART_RTS);
}
void hci_end_tx_continuous_test_cmd(void)
{
struct msg_tx_end_continue_test_cfm s;
uint8_t* bufptr;
s.packet_type = HCI_EVT_MSG_TYPE;
s.event_code = HCI_CMD_CMPL_EVT_CODE;
s.length = 3;
s.param0 = 0x01;
s.param_opcode = HCI_TX_END_CONTINUE_TEST_CMD_OPCODE;
bufptr = (uint8_t*)&s;
uart_write(bufptr,sizeof(struct msg_tx_end_continue_test_cfm),NULL);
set_state_stop();
SetWord32(BLE_RFTESTCNTL_REG,0); //disable continuous mode
}
/**
****************************************************************************************
* @brief otp_prepare()
*
* About: Prepare OTP Controller in order to be able to reload SysRAM at the next power-up
****************************************************************************************
*/
static __inline void otp_prepare(uint32 code_size)
{
// Enable OPTC clock in order to have access
SetBits16 (CLK_AMBA_REG, OTP_ENABLE, 1);
// Wait a little bit to start the OTP clock...
for(uint8 i=0;i<10;i++); //change this later to a defined time
SetBits16(SYS_CTRL_REG, OTP_COPY, 1);
// Copy the size of software from the first word of the retaintion mem.
SetWord32 (OTPC_NWORDS_REG, code_size - 1);
// And close the OPTC clock to save power
SetBits16 (CLK_AMBA_REG, OTP_ENABLE, 0);
}
bool uart_flow_off_func(void)
{
bool flow_off = true;
do
{
// First check if no transmission is ongoing
if ((uart_temt_getf() == 0) || (uart_thre_getf() == 0))
{
flow_off = false;
break;
}
// Configure modem (HW flow control disable, 'RTS flow off')
#if 0
uart_mcr_pack(UART_ENABLE, // extfunc
UART_DISABLE, // autorts
UART_ENABLE, // autocts
UART_DISABLE); // rts
#endif
SetWord32(UART_MCR_REG, 0);
// Wait for 1 character duration to ensure host has not started a transmission at the
// same time
for (i=0;i<350;i++);
// Wait for 1 character duration to ensure host has not started a transmission at the
// same time
#ifndef __GNUC__
// timer_wait(UART_CHAR_DURATION);
#endif //__GNUC__
// Check if data has been received during wait time
if(!uart_is_rx_fifo_empty())
{
// Re-enable UART flow
uart_flow_on();
// We failed stopping the flow
flow_off = false;
}
} while(false);
return (flow_off);
}
void nvds_read_bdaddr_from_otp()
{
#ifdef BDADDR_FROM_OTP
#if DEVELOPMENT__NO_OTP
int cnt=100000;
#define XPMC_MODE_MREAD 0x1
uint8_t *otp_bdaddr = (uint8_t *)0x40000 + BDADDR_FROM_OTP; //where in OTP header is BDADDR
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 1); // enable OTP clock
while ((GetWord16(ANA_STATUS_REG) & LDO_OTP_OK) != LDO_OTP_OK && cnt--)
/* Just wait */;
// set OTP in read mode
SetWord32 (OTPC_MODE_REG,XPMC_MODE_MREAD);
#else
uint8_t *otp_bdaddr = (uint8_t *)0x20000000 + BDADDR_FROM_OTP; //where in OTP header is BDADDR
#endif
memcpy(&dev_bdaddr, otp_bdaddr, sizeof(dev_bdaddr));
SetBits16(CLK_AMBA_REG, OTP_ENABLE, 0); //disable OTP clock
#endif
}
void rf_reinit_func(void)
{
uint32 tmp32 = 0;
SetBits32(&tmp32, RTRIP_DELAY, 7);
SetBits32(&tmp32, TXPWRDN, 0x5);
SetBits32(&tmp32, RXPWRUP, RXPWRUP_VAL);
SetBits32(&tmp32, TXPWRUP, TXPWRUP_VAL);
SetWord32(BLE_RADIOPWRUPDN_REG, tmp32);
SetBits32(BLE_RADIOCNTL1_REG, XRFSEL, 3);
SetBits32(BLE_RWBTLECNTL_REG, SYNCERR, 0); //this must be always '0'
SetBits16(CLK_RADIO_REG, RFCU_DIV, 1); //RFCU clock must always be 8MHz!
SetBits16(CLK_RADIO_REG, RFCU_ENABLE, 1);
SetBits16(PMU_CTRL_REG, RETENTION_MODE, 0xF);
if (lp_clk_sel == LP_CLK_XTAL32)
{
//If LP clock is XTAL32 in Boost mode set XTAL32K_CUR to 1.
if (GetBits16(ANA_STATUS_REG, BOOST_SELECTED) == 0x1)
SetBits16(CLK_32K_REG, XTAL32K_CUR, 1);
}
rf_regs();
#if LUT_PATCH_ENABLED
const volatile struct LUT_CFG_struct *pLUT_CFG; // = (const volatile struct LUT_CFG_struct *)(jump_table_struct[lut_cfg_pos]);
pLUT_CFG= (const volatile struct LUT_CFG_struct *)(jump_table_struct[lut_cfg_pos]);
if (pLUT_CFG->HW_LUT_MODE)
{
SetWord16(RF_VCOCAL_CTRL_REG, vcocal_ctrl_reg_val);
}
#endif //LUT_PATCH_ENABLED
enable_rf_diag_irq(RF_DIAG_IRQ_MODE_RXTX); // This just enables the TX_EN int. RX_EN int enable status remains as it was
}
void uart_sps_force_flow_off(void)
{
SetWord32(UART_MCR_REG, GetWord32(UART_MCR_REG) & (~UART_RTS));
}
void uart_sps_flow_on(void)
{
// Configure modem (HW flow control enable)
SetWord32(UART_MCR_REG, UART_AFCE|UART_RTS);
}
void patch_func (void)
{
#ifdef __DA14581__
//0x00024b1d lld_adv_start
SetWord32(PATCH_ADDR0_REG, 0x00024b1C);
SetWord32(PATCH_DATA0_REG, 0xb5ffdf01); //lld_adv_start svc 1 (+ enabling of interrupts)
#if (BLE_HOST_PRESENT)
//0x0002a8c5 atts_read_resp
SetWord32(PATCH_ADDR1_REG, 0x0002a8c4);
SetWord32(PATCH_DATA1_REG, 0xb5f8df00); //atts_read_resp svc 0 (+ enabling of interrupts)
#else
//0x000278f9 llm_rd_local_supp_feats_cmd_handler
SetWord32(PATCH_ADDR1_REG, 0x000278f8);
SetWord32(PATCH_DATA1_REG, 0x4619df00); //llm_rd_local_supp_feats_cmd_handler svc 0
SetWord32(PATCH_ADDR2_REG, 0x000278c0); // llm_rd_local_ver_info_cmd_handler
SetWord32(PATCH_DATA2_REG, 0x80c121d2); // patch manufacturer ID
SetWord32(PATCH_ADDR3_REG, 0x0002299c); // llc_version_ind_pdu_send
SetWord32(PATCH_DATA3_REG, 0x80d020d2); // patch manufacturer ID
#endif
#endif
#ifndef __DA14581__
//0x00032795 cmp_abs_time
SetWord32(PATCH_ADDR0_REG, 0x00032794);
SetWord32(PATCH_DATA0_REG, 0xdf00b662); //cmp_abs_time svc 0 (+ enabling of interrupts)
//0x0002a32b l2cc_pdu_recv_ind_handler (atts)
SetWord32(PATCH_ADDR1_REG, 0x0002a328);
SetWord32(PATCH_DATA1_REG, 0xdf014770); //l2cc_pdu_recv_ind_handler svc 1
//0x0002ca1f smpc_send_pairing_req_ind
SetWord32(PATCH_ADDR2_REG, 0x0002ca1c);
SetWord32(PATCH_DATA2_REG, 0xdf02bdf8); //smpc_send_pairing_req_ind svc 2
//0x0002cb43 smpc_check_pairing_feat
SetWord32(PATCH_ADDR3_REG, 0x0002cb40);
SetWord32(PATCH_DATA3_REG, 0xdf03e7f5); //smpc_check_pairing_feat svc 3
//0x0002d485 smpc_pairing_cfm_handler
SetWord32(PATCH_ADDR4_REG, 0x0002d484);
SetWord32(PATCH_DATA4_REG, 0xb089df04); //smpc_pairing_cfm_handler svc 4
//0x000233bf llc_con_update_req_ind
SetWord32(PATCH_ADDR5_REG, 0x000233bc);
SetWord32(PATCH_DATA5_REG, 0xdf05bdf8); //llc_con_update_req_ind svc 5
//0x0002341b llc_ch_map_req_ind
SetWord32(PATCH_ADDR6_REG, 0x00023418);
SetWord32(PATCH_DATA6_REG, 0xdf06bdf8); //llc_ch_map_req_ind svc 6
//0x00030cef gapm_adv_op_sanity
SetWord32(PATCH_ADDR7_REG, 0x00030cec);
SetWord32(PATCH_DATA7_REG, 0xdf07bd70); //gapm_adv_op_sanity svc 7
NVIC_DisableIRQ(SVCall_IRQn);
NVIC_SetPriority(SVCall_IRQn, 0);
NVIC_EnableIRQ(SVCall_IRQn);
#endif
}
void rf_init_func(struct rwip_rf_api *api)
{
uint32 tmp32 = 0;
uint8 idx = 0;
uint8 temp_freq_tbl[EM_BLE_FREQ_TABLE_LEN];
// Initialize the RF driver API structure
api->reg_rd = rf_reg_rd;
api->reg_wr = rf_reg_wr;
api->txpwr_dbm_get = rf_txpwr_dbm_get;
//api->txpwr_max = RPL_POWER_MAX;
api->sleep = rf_sleep;
api->reset = rf_reset;
#ifdef CFG_BLE
api->isr = RADIOCNTL_Handler;
api->force_agc_enable = rf_force_agc_enable;
#endif //CFG_BLE
api->rssi_convert = rf_rssi_convert;
#ifdef CFG_BT
api->txpwr_inc = rf_txpwr_inc;
api->txpwr_dec = rf_txpwr_dec;
api->txpwr_epc_req = rf_txpwr_epc_req;
api->txpwr_cs_get = rf_txpwr_cs_get;
api->rssi_high_thr = (uint8_t)RPL_RSSI_20dB_THRHLD;
api->rssi_low_thr = (uint8_t)RPL_RSSI_60dB_THRHLD;
api->rssi_interf_thr = (uint8_t)RPL_RSSI_70dB_THRHLD;
#ifdef CFG_BTCORE_30
api->wakeup_delay = RPL_WK_UP_DELAY;
#endif //CFG_BTCORE_30
api->skew = RPL_RADIO_SKEW;
#endif //CFG_BT
// CLK_FREQ_TRIM_REG initialization was moved to main_func() in arch_main.c
// The initialization of this register is done by the Boot ROM code if a valid
// value has been written to the corresponding position in the OTP header by
// the customer.
// main_func() will write this register with a default value and the customer
// must remove this code when he has written the OTP header.
SetBits32(&tmp32, RTRIP_DELAY, 7);
SetBits32(&tmp32, TXPWRDN, 0x5);
SetBits32(&tmp32, RXPWRUP, RXPWRUP_VAL);
SetBits32(&tmp32, TXPWRUP, TXPWRUP_VAL);
SetWord32(BLE_RADIOPWRUPDN_REG,tmp32);
SetBits32(BLE_RADIOCNTL0_REG, DPCORR_EN, 0); //THIS MAY NOT BE '1', THEN WE MISS 12 BITS IN THE SYNCWORD DURING A RX BURST
SetBits32(BLE_RADIOCNTL1_REG, XRFSEL, 3);
SetBits32(BLE_CNTL2_REG, SW_RPL_SPI ,0);
SetBits32(BLE_CNTL2_REG, BB_ONLY,0);
while(idx < EM_BLE_FREQ_TABLE_LEN)
{
temp_freq_tbl[idx] = idx ;
idx++;
}
em_ble_burst_wr(&temp_freq_tbl[0], EM_BLE_FT_OFFSET, EM_BLE_FREQ_TABLE_LEN);
rf_regs();
last_temp_count = get_rc16m_count();
#if LUT_PATCH_ENABLED
pll_vcocal_LUT_InitUpdate(LUT_INIT);
#endif
rf_calibration();
}
