void test_setProgramCounter_should_able_to_set_value_0xabcdef(){ clearAllFileRegisters(); int pc = 0xabcdef; setProgramCounter(pc); TEST_ASSERT_EQUAL_HEX16(0xab,fileRegisters[PCLATU] ); TEST_ASSERT_EQUAL_HEX16(0xcd,fileRegisters[PCLATH] ); TEST_ASSERT_EQUAL_HEX16(0xef,fileRegisters[PCL] ); }
void test_getProgramCounter_and_setProgramCounter_should_able_to_get_and_update_pc(){ clearAllFileRegisters(); fileRegisters[PCLATU] = 0x00; fileRegisters[PCLATH] = 0x00; fileRegisters[PCL] = 0x01; int pc = getProgramCounter(); pc += 0x5; setProgramCounter(pc); TEST_ASSERT_EQUAL_HEX16(0x00,fileRegisters[PCLATU] ); TEST_ASSERT_EQUAL_HEX16(0x00,fileRegisters[PCLATH] ); TEST_ASSERT_EQUAL_HEX16(0x06,fileRegisters[PCL] ); }
void testNotEqualHex16sIfSigned(void) { _US16 v0, v1; v0 = -1024; v1 = -1028; EXPECT_ABORT_BEGIN TEST_ASSERT_EQUAL_HEX16(v0, v1); VERIFY_FAILS_END }
void testNotEqualHex16s(void) { _UU16 v0, v1; v0 = 0x1234; v1 = 0x1235; EXPECT_ABORT_BEGIN TEST_ASSERT_EQUAL_HEX16(v0, v1); VERIFY_FAILS_END }
/** Common for all SDIO devices, set block size for specific function */ static void sdio_slave_set_blocksize(sdmmc_card_t* card, int function, uint16_t bs) { const uint8_t* bs_u8 = (const uint8_t*) &bs; uint16_t bs_read = 0; uint8_t* bs_read_u8 = (uint8_t*) &bs_read; uint32_t offset = SD_IO_FBR_START * function; TEST_ESP_OK( sdmmc_io_write_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEL, bs_u8[0], NULL)); TEST_ESP_OK( sdmmc_io_write_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEH, bs_u8[1], NULL)); TEST_ESP_OK( sdmmc_io_read_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEL, &bs_read_u8[0])); TEST_ESP_OK( sdmmc_io_read_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEH, &bs_read_u8[1])); TEST_ASSERT_EQUAL_HEX16(bs, bs_read); }
void test_push(void){ int error; Instruction inst = { .mnemonic = PUSH, .name = "push" }; Bytecode code = {.instruction = &inst, .operand1 = -1, .operand2 = -1, .operand3 = -1, .absoluteAddress = 0}; FSR[STKPTR] = 0; push(&code); TEST_ASSERT_EQUAL(0x1, FSR[STKPTR]); TEST_ASSERT_EQUAL_HEX16(0x1, PIC18Stack[FSR[STKPTR]]); }
void test_FA_with_ERR_NO_ARGUMENT_0xff6_should_return_0xf6_and_store_in_ACCESS(void){ int value; int e; Text *text = textNew("135"); String *str = stringNew(text); extractValue_ExpectAndReturn(str, 0xff6); extractACCESSBANKED_ExpectAndThrow(str, 4); value = FA(str); TEST_ASSERT_EQUAL_HEX16(value, 0xf6); }
void test_FA_should_return_0x34_and_store_in_BANKED(void){ int value; int e; Text *text = textNew("135"); String *str = stringNew(text); extractValue_ExpectAndReturn(str, 0x134); extractACCESSBANKED_ExpectAndReturn(str, 1); value = FA(str); TEST_ASSERT_EQUAL_HEX16(value, 0x134); }
void test_binary_16() { TEST_ASSERT_EQUAL_HEX16(0x0000, BIN16(00000000, 00000000)); TEST_ASSERT_EQUAL_HEX16(0x000f, BIN16(00000000, 00001111)); TEST_ASSERT_EQUAL_HEX16(0x00f0, BIN16(00000000, 11110000)); TEST_ASSERT_EQUAL_HEX16(0x0f00, BIN16(00001111, 00000000)); TEST_ASSERT_EQUAL_HEX16(0xf000, BIN16(11110000, 00000000)); TEST_ASSERT_EQUAL_HEX16(0xffff, BIN16(11111111, 11111111)); }
void testNotEqualHex16sIfSigned(void) { int failed; _US16 v0, v1; v0 = -1024; v1 = -1028; EXPECT_ABORT_BEGIN TEST_ASSERT_EQUAL_HEX16(v0, v1); EXPECT_ABORT_END failed = Unity.CurrentTestFailed; Unity.CurrentTestFailed = 0; TEST_ASSERT_MESSAGE(1U == failed, "This is expected"); }
void testNotEqualHex16s(void) { int failed; _UU16 v0, v1; v0 = 0x1234; v1 = 0x1235; EXPECT_ABORT_BEGIN TEST_ASSERT_EQUAL_HEX16(v0, v1); EXPECT_ABORT_END failed = Unity.CurrentTestFailed; Unity.CurrentTestFailed = 0; TEST_ASSERT_MESSAGE(1U == failed, "This is expected"); }
void testEqualHex16s(void) { _UU16 v0, v1; _UU16 *p0, *p1; v0 = 0x9876; v1 = 0x9876; p0 = &v0; p1 = &v1; TEST_ASSERT_EQUAL_HEX16(0x9876, 0x9876); TEST_ASSERT_EQUAL_HEX16(v0, v1); TEST_ASSERT_EQUAL_HEX16(0x9876, v1); TEST_ASSERT_EQUAL_HEX16(v0, 0x9876); TEST_ASSERT_EQUAL_HEX16(*p0, v1); TEST_ASSERT_EQUAL_HEX16(*p0, *p1); TEST_ASSERT_EQUAL_HEX16(*p0, 0x9876); }
TEST(Sample, Simple) { int expected = 0x180; int actual = SetBit(SetBit(0, 7), 8); TEST_ASSERT_EQUAL_HEX16(expected, actual); }
void test_decfsz_should_decrement_value_0x01_expect_0x00_pc_add_4_store_in_wreg_access_should_pass(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x12, .operand2 = W, .operand3 = ACCESS, .absoluteAddress = 0}; FSR[code.operand1] = 0x01; decfsz(&code); TEST_ASSERT_EQUAL_HEX8(0x00, FSR[WREG]); } void test_decfsz_should_decrement_value_0x02_expect_0x01_pc_add_2_store_in_wreg_access_should_pass(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x12, .operand2 = W, .operand3 = ACCESS, .absoluteAddress = 0}; FSR[code.operand1] = 0x02; decfsz(&code); TEST_ASSERT_EQUAL_HEX8(0x01, FSR[WREG]); } void test_decfsz_should_decrement_value_0x01_expect_0x00_pc_add_4_store_in_file_reg_access_should_pass(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x12, .operand2 = F, .operand3 = ACCESS, .absoluteAddress = 0}; FSR[code.operand1] = 0x01; decfsz(&code); TEST_ASSERT_EQUAL_HEX8(0x00, FSR[code.operand1]); } void test_decfsz_should_decrement_value_0x02_expect_0x01_pc_add_2_store_in_file_reg_access_should_pass(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x12, .operand2 = F, .operand3 = ACCESS, .absoluteAddress = 0}; FSR[code.operand1] = 0x02; decfsz(&code); TEST_ASSERT_EQUAL_HEX8(0x01, FSR[code.operand1]); } void test_decfsz_should_decrement_value_0x00_expect_0xff_pc_add_2_store_in_file_reg_access_should_pass(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x244, .operand2 = F, .operand3 = -1, .absoluteAddress = 0}; FSR[code.operand1] = 0x0; decfsz(&code); TEST_ASSERT_EQUAL_HEX8(0xff, FSR[code.operand1+(FSR[BSR]<<8)]); } void test_decfsz_should_decrement_value_0x02_expect_0x01_pc_add_2_store_in_file_reg_access_address_0xa1_should_change_to_0xfa1_pass(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0xa1, .operand2 = F, .operand3 = 0, .absoluteAddress = 0}; FSR[code.operand1] = 0x02; decfsz(&code); TEST_ASSERT_EQUAL_HEX16(0xfa1, code.operand1); } void test_decfsz_should_decrement_value_0x02_expect_0x01_pc_add_2_default_operand2_access_should_pass(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x12, .operand2 = ACCESS, .operand3 = -1, .absoluteAddress = 0}; FSR[code.operand1] = 0x02; decfsz(&code); TEST_ASSERT_EQUAL_HEX8(0x01, FSR[code.operand1]); } void test_decfsz_should_decrement_value_0x02_expect_0x01_pc_add_2_default_operand2_operand3_should_pass(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x12, .operand2 = -1, .operand3 = -1, .absoluteAddress = 0}; FSR[code.operand1] = 0x02; decfsz(&code); TEST_ASSERT_EQUAL_HEX8(0x01, FSR[code.operand1]); } void test_decfsz_should_decrement_value_0x01_expect_0x00_pc_add_4_store_in_wreg_bsr_5_should_pass(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x12, .operand2 = 0, .operand3 = 1, .absoluteAddress = 0}; FSR[BSR] = 0x05; FSR[code.operand1+(FSR[BSR]<<8)] = 0x01; decfsz(&code); TEST_ASSERT_EQUAL_HEX8(0x00, FSR[WREG]); } void test_decfsz_should_decrement_value_0x02_expect_0x01_pc_add_2_store_in_wreg_bsr_5_should_pass(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x12, .operand2 = W, .operand3 = BANKED, .absoluteAddress = 0}; FSR[BSR] = 0x05; FSR[0x512] = 0x02; decfsz(&code); TEST_ASSERT_EQUAL_HEX8(0x01, FSR[WREG]); } void test_decfsz_should_decrement_value_0x10_expect_0x0f_pc_add_2_store_in_wreg_bsr_5_should_pass(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0xf92, .operand2 = W, .operand3 = BANKED, .absoluteAddress = 0}; FSR[BSR] = 0x05; FSR[code.operand1] = 0x10; decfsz(&code); TEST_ASSERT_EQUAL_HEX8(0x0f, FSR[WREG]); } void test_decfsz_should_decrement_value_0x01_expect_0x00_pc_add_4_store_in_file_bsr_5_should_pass(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x12, .operand2 = F, .operand3 = 1, .absoluteAddress = 0}; FSR[BSR] = 0x05; FSR[code.operand1+(FSR[BSR]<<8)] = 0x01; decfsz(&code); TEST_ASSERT_EQUAL_HEX8(0x00, FSR[code.operand1+(FSR[BSR]<<8)]); } void test_decfsz_should_decrement_value_0x02_expect_0x01_pc_add_2_store_in_file_bsr_5_should_pass(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x12, .operand2 = F, .operand3 = BANKED, .absoluteAddress = 0}; FSR[BSR] = 0x05; FSR[code.operand1+(FSR[BSR]<<8)] = 0x02; decfsz(&code); TEST_ASSERT_EQUAL_HEX8(0x01, FSR[code.operand1+(FSR[BSR]<<8)]); } void test_decfsz_invalid_operand1_should_throw_exception(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = -1, .operand2 = F, .operand3 = BANKED}; FSR[BSR] = 0x05; FSR[code.operand1+(FSR[BSR]<<8)] = 0x02; Try{ decfsz(&code); }Catch(error){ TEST_ASSERT_EQUAL(1, ERR_INVALID_OPERAND); } } void test_decfsz_invalid_operand2_should_throw_exception(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x12, .operand2 = 2, .operand3 = BANKED}; FSR[BSR] = 0x05; FSR[code.operand1+(FSR[BSR]<<8)] = 0x02; Try{ decfsz(&code); }Catch(error){ TEST_ASSERT_EQUAL(1, ERR_INVALID_OPERAND); } } void test_decfsz_invalid_operand3_should_throw_exception(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x12, .operand2 = F, .operand3 = 2}; FSR[BSR] = 0x05; FSR[code.operand1+(FSR[BSR]<<8)] = 0x02; Try{ decfsz(&code); }Catch(error){ TEST_ASSERT_EQUAL(1, ERR_INVALID_OPERAND); } } void test_decfsz_should_decrement_value_0x02_expect_0x01_pc_add_2_default_operand2_invalid_operand3_should_throw_exception(){ int error; Instruction inst = { .mnemonic = DECFSZ, .name = "decfsz" }; Bytecode code = {.instruction = &inst, .operand1 = 0x12, .operand2 = ACCESS, .operand3 = 2}; FSR[code.operand1] = 0x02; Try{ decfsz(&code); }Catch(error){ TEST_ASSERT_EQUAL(1, ERR_INVALID_OPERAND); } }
void test_ONFI_set_speed_ShouldWork(void) { ONFI_set_speed(5); TEST_ASSERT_EQUAL_HEX16(0xe0, ONFI_ReadStatus()); }