DEBUG_FUNCTION void
debug_value_data (struct value_data *vd)
{
HARD_REG_SET set;
unsigned int i, j;
CLEAR_HARD_REG_SET (set);
for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
if (vd->e[i].oldest_regno == i)
{
if (vd->e[i].mode == VOIDmode)
{
if (vd->e[i].next_regno != INVALID_REGNUM)
fprintf (stderr, "[%u] Bad next_regno for empty chain (%u)\n",
i, vd->e[i].next_regno);
continue;
}
SET_HARD_REG_BIT (set, i);
fprintf (stderr, "[%u %s] ", i, GET_MODE_NAME (vd->e[i].mode));
for (j = vd->e[i].next_regno;
j != INVALID_REGNUM;
j = vd->e[j].next_regno)
{
if (TEST_HARD_REG_BIT (set, j))
{
fprintf (stderr, "[%u] Loop in regno chain\n", j);
return;
}
if (vd->e[j].oldest_regno != i)
{
fprintf (stderr, "[%u] Bad oldest_regno (%u)\n",
j, vd->e[j].oldest_regno);
return;
}
SET_HARD_REG_BIT (set, j);
fprintf (stderr, "[%u %s] ", j, GET_MODE_NAME (vd->e[j].mode));
}
fputc ('\n', stderr);
}
for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
if (! TEST_HARD_REG_BIT (set, i)
&& (vd->e[i].mode != VOIDmode
|| vd->e[i].oldest_regno != i
|| vd->e[i].next_regno != INVALID_REGNUM))
fprintf (stderr, "[%u] Non-empty reg in chain (%s %u %i)\n",
i, GET_MODE_NAME (vd->e[i].mode), vd->e[i].oldest_regno,
vd->e[i].next_regno);
}
/* Return true if insn is an instruction that sets a target register.
if CHECK_CONST is true, only return true if the source is constant.
If such a set is found and REGNO is nonzero, assign the register number
of the destination register to *REGNO. */
static int
insn_sets_btr_p (const_rtx insn, int check_const, int *regno)
{
rtx set;
if (NONJUMP_INSN_P (insn)
&& (set = single_set (insn)))
{
rtx dest = SET_DEST (set);
rtx src = SET_SRC (set);
if (GET_CODE (dest) == SUBREG)
dest = XEXP (dest, 0);
if (REG_P (dest)
&& TEST_HARD_REG_BIT (all_btrs, REGNO (dest)))
{
gcc_assert (!btr_referenced_p (src, NULL));
if (!check_const || CONSTANT_P (src))
{
if (regno)
*regno = REGNO (dest);
return 1;
}
}
}
return 0;
}
static void
validate_value_data (struct value_data *vd)
{
HARD_REG_SET set;
unsigned int i, j;
CLEAR_HARD_REG_SET (set);
for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
if (vd->e[i].oldest_regno == i)
{
if (vd->e[i].mode == VOIDmode)
{
if (vd->e[i].next_regno != INVALID_REGNUM)
internal_error ("validate_value_data: [%u] Bad next_regno for empty chain (%u)",
i, vd->e[i].next_regno);
continue;
}
SET_HARD_REG_BIT (set, i);
for (j = vd->e[i].next_regno;
j != INVALID_REGNUM;
j = vd->e[j].next_regno)
{
if (TEST_HARD_REG_BIT (set, j))
internal_error ("validate_value_data: Loop in regno chain (%u)",
j);
if (vd->e[j].oldest_regno != i)
internal_error ("validate_value_data: [%u] Bad oldest_regno (%u)",
j, vd->e[j].oldest_regno);
SET_HARD_REG_BIT (set, j);
}
}
for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
if (! TEST_HARD_REG_BIT (set, i)
&& (vd->e[i].mode != VOIDmode
|| vd->e[i].oldest_regno != i
|| vd->e[i].next_regno != INVALID_REGNUM))
internal_error ("validate_value_data: [%u] Non-empty reg in chain (%s %u %i)",
i, GET_MODE_NAME (vd->e[i].mode), vd->e[i].oldest_regno,
vd->e[i].next_regno);
}
/* Process the death of hard register REGNO. This updates
hard_regs_live and START_DYING. */
static void
make_hard_regno_dead (int regno)
{
lra_assert (regno < FIRST_PSEUDO_REGISTER);
if (! TEST_HARD_REG_BIT (hard_regs_live, regno))
return;
sparseset_set_bit (start_dying, regno);
CLEAR_HARD_REG_BIT (hard_regs_live, regno);
}
/* The function processing birth of hard register REGNO. It updates
living hard regs, conflict hard regs for living pseudos, and
START_LIVING. */
static void
make_hard_regno_born (int regno)
{
unsigned int i;
lra_assert (regno < FIRST_PSEUDO_REGISTER);
if (TEST_HARD_REG_BIT (hard_regs_live, regno))
return;
SET_HARD_REG_BIT (hard_regs_live, regno);
sparseset_set_bit (start_living, regno);
EXECUTE_IF_SET_IN_SPARSESET (pseudos_live, i)
SET_HARD_REG_BIT (lra_reg_info[i].conflict_hard_regs, regno);
}
/* The function processing birth of hard register REGNO. It updates
living hard regs, START_LIVING, and conflict hard regs for living
pseudos. Conflict hard regs for the pic pseudo is not updated if
REGNO is REAL_PIC_OFFSET_TABLE_REGNUM and CHECK_PIC_PSEUDO_P is
true. */
static void
make_hard_regno_born (int regno, bool check_pic_pseudo_p ATTRIBUTE_UNUSED)
{
unsigned int i;
lra_assert (regno < FIRST_PSEUDO_REGISTER);
if (TEST_HARD_REG_BIT (hard_regs_live, regno))
return;
SET_HARD_REG_BIT (hard_regs_live, regno);
sparseset_set_bit (start_living, regno);
EXECUTE_IF_SET_IN_SPARSESET (pseudos_live, i)
#ifdef REAL_PIC_OFFSET_TABLE_REGNUM
if (! check_pic_pseudo_p
|| regno != REAL_PIC_OFFSET_TABLE_REGNUM
|| pic_offset_table_rtx == NULL
|| i != REGNO (pic_offset_table_rtx))
#endif
SET_HARD_REG_BIT (lra_reg_info[i].conflict_hard_regs, regno);
}
/* Spill pseudos which are assigned to hard registers in SET. Add
affected insns for processing in the subsequent constraint
pass. */
static void
spill_pseudos (HARD_REG_SET set)
{
int i;
bitmap_head to_process;
rtx_insn *insn;
if (hard_reg_set_empty_p (set))
return;
if (lra_dump_file != NULL)
{
fprintf (lra_dump_file, " Spilling non-eliminable hard regs:");
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (TEST_HARD_REG_BIT (set, i))
fprintf (lra_dump_file, " %d", i);
fprintf (lra_dump_file, "\n");
}
bitmap_initialize (&to_process, ®_obstack);
for (i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
if (lra_reg_info[i].nrefs != 0 && reg_renumber[i] >= 0
&& overlaps_hard_reg_set_p (set,
PSEUDO_REGNO_MODE (i), reg_renumber[i]))
{
if (lra_dump_file != NULL)
fprintf (lra_dump_file, " Spilling r%d(%d)\n",
i, reg_renumber[i]);
reg_renumber[i] = -1;
bitmap_ior_into (&to_process, &lra_reg_info[i].insn_bitmap);
}
IOR_HARD_REG_SET (lra_no_alloc_regs, set);
for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
if (bitmap_bit_p (&to_process, INSN_UID (insn)))
{
lra_push_insn (insn);
lra_set_used_insn_alternative (insn, -1);
}
bitmap_clear (&to_process);
}
static void
recompute_gain_for_pattern_seq (pattern_seq pseq)
{
matching_seq mseq;
rtx x;
int i;
int hascall;
HARD_REG_SET linkregs;
/* Initialize data. */
SET_HARD_REG_SET (linkregs);
pseq->link_reg = NULL_RTX;
pseq->abstracted_length = 0;
pseq->gain = -(seq_call_cost - seq_jump_cost + seq_return_cost);
/* Determine ABSTRACTED_LENGTH and COST for matching sequences of PSEQ.
ABSTRACTED_LENGTH may be less than MATCHING_LENGTH if sequences in the
same block overlap. */
for (mseq = pseq->matching_seqs; mseq; mseq = mseq->next_matching_seq)
{
/* Determine ABSTRACTED_LENGTH. */
if (mseq->next_matching_seq)
mseq->abstracted_length = (int)(mseq->next_matching_seq->idx -
mseq->idx);
else
mseq->abstracted_length = mseq->matching_length;
if (mseq->abstracted_length > mseq->matching_length)
mseq->abstracted_length = mseq->matching_length;
/* Compute the cost of sequence. */
RECOMPUTE_COST (mseq);
/* If COST is big enough registers live in this matching sequence
should not be used as a link register. Also set ABSTRACTED_LENGTH
of PSEQ. */
if (mseq->cost > seq_call_cost)
{
clear_regs_live_in_seq (&linkregs, mseq->insn,
mseq->abstracted_length);
if (mseq->abstracted_length > pseq->abstracted_length)
pseq->abstracted_length = mseq->abstracted_length;
}
}
/* Modify ABSTRACTED_LENGTH of PSEQ if pattern sequence overlaps with one
of the matching sequences. */
for (mseq = pseq->matching_seqs; mseq; mseq = mseq->next_matching_seq)
{
x = pseq->insn;
for (i = 0; (i < pseq->abstracted_length) && (x != mseq->insn); i++)
x = prev_insn_in_block (x);
pseq->abstracted_length = i;
}
/* Compute the cost of pattern sequence. */
RECOMPUTE_COST (pseq);
/* No gain if COST is too small. */
if (pseq->cost <= seq_call_cost)
{
pseq->gain = -1;
return;
}
/* Ensure that no matching sequence is longer than the pattern sequence. */
for (mseq = pseq->matching_seqs; mseq; mseq = mseq->next_matching_seq)
{
if (mseq->abstracted_length > pseq->abstracted_length)
{
mseq->abstracted_length = pseq->abstracted_length;
RECOMPUTE_COST (mseq);
}
/* Once the length is stabilizing the gain can be calculated. */
if (mseq->cost > seq_call_cost)
pseq->gain += mseq->cost - seq_call_cost;
}
/* No need to do further work if there is no gain. */
if (pseq->gain <= 0)
return;
/* Should not use registers live in the pattern sequence as link register.
*/
clear_regs_live_in_seq (&linkregs, pseq->insn, pseq->abstracted_length);
/* Determine whether pattern sequence contains a call_insn. */
hascall = 0;
x = pseq->insn;
for (i = 0; i < pseq->abstracted_length; i++)
{
if (CALL_P (x))
{
hascall = 1;
break;
}
x = prev_insn_in_block (x);
}
/* Should not use a register as a link register if - it is a fixed
register, or - the sequence contains a call insn and the register is a
call used register, or - the register needs to be saved if used in a
function but was not used before (since saving it can invalidate already
computed frame pointer offsets), or - the register cannot be used as a
base register. */
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (fixed_regs[i]
#ifdef REGNO_OK_FOR_INDIRECT_JUMP_P
|| (!REGNO_OK_FOR_INDIRECT_JUMP_P (i, Pmode))
#else
|| (!ok_for_base_p_1 (i, Pmode, MEM, SCRATCH))
|| (!reg_class_subset_p (REGNO_REG_CLASS (i),
base_reg_class (VOIDmode, MEM, SCRATCH)))
#endif
|| (hascall && call_used_regs[i])
|| (!call_used_regs[i] && !df_regs_ever_live_p (i)))
CLEAR_HARD_REG_BIT (linkregs, i);
/* Find an appropriate register to be used as the link register. */
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (TEST_HARD_REG_BIT (linkregs, i))
{
pseq->link_reg = gen_rtx_REG (Pmode, i);
break;
}
/* Abstraction is not possible if no link register is available, so set
gain to 0. */
if (!pseq->link_reg)
pseq->gain = 0;
}
void
init_caller_save ()
{
char *first_obj = (char *) oballoc (0);
rtx addr_reg;
int offset;
rtx address;
int i, j;
/* First find all the registers that we need to deal with and all
the modes that they can have. If we can't find a mode to use,
we can't have the register live over calls. */
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
if (call_used_regs[i] && ! call_fixed_regs[i])
{
for (j = 1; j <= MOVE_MAX / UNITS_PER_WORD; j++)
{
regno_save_mode[i][j] = choose_hard_reg_mode (i, j);
if (regno_save_mode[i][j] == VOIDmode && j == 1)
{
call_fixed_regs[i] = 1;
SET_HARD_REG_BIT (call_fixed_reg_set, i);
}
}
}
else
regno_save_mode[i][1] = VOIDmode;
}
/* The following code tries to approximate the conditions under which
we can easily save and restore a register without scratch registers or
other complexities. It will usually work, except under conditions where
the validity of an insn operand is dependent on the address offset.
No such cases are currently known.
We first find a typical offset from some BASE_REG_CLASS register.
This address is chosen by finding the first register in the class
and by finding the smallest power of two that is a valid offset from
that register in every mode we will use to save registers. */
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (TEST_HARD_REG_BIT (reg_class_contents[(int) BASE_REG_CLASS], i))
break;
if (i == FIRST_PSEUDO_REGISTER)
abort ();
addr_reg = gen_rtx_REG (Pmode, i);
for (offset = 1 << (HOST_BITS_PER_INT / 2); offset; offset >>= 1)
{
address = gen_rtx_PLUS (Pmode, addr_reg, GEN_INT (offset));
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (regno_save_mode[i][1] != VOIDmode
&& ! strict_memory_address_p (regno_save_mode[i][1], address))
break;
if (i == FIRST_PSEUDO_REGISTER)
break;
}
/* If we didn't find a valid address, we must use register indirect. */
if (offset == 0)
address = addr_reg;
/* Next we try to form an insn to save and restore the register. We
see if such an insn is recognized and meets its constraints. */
start_sequence ();
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
for (j = 1; j <= MOVE_MAX / UNITS_PER_WORD; j++)
if (regno_save_mode[i][j] != VOIDmode)
{
rtx mem = gen_rtx_MEM (regno_save_mode[i][j], address);
rtx reg = gen_rtx_REG (regno_save_mode[i][j], i);
rtx savepat = gen_rtx_SET (VOIDmode, mem, reg);
rtx restpat = gen_rtx_SET (VOIDmode, reg, mem);
rtx saveinsn = emit_insn (savepat);
rtx restinsn = emit_insn (restpat);
int ok;
reg_save_code[i][j] = recog_memoized (saveinsn);
reg_restore_code[i][j] = recog_memoized (restinsn);
/* Now extract both insns and see if we can meet their
constraints. */
ok = (reg_save_code[i][j] != -1 && reg_restore_code[i][j] != -1);
if (ok)
{
insn_extract (saveinsn);
ok = constrain_operands (reg_save_code[i][j], 1);
insn_extract (restinsn);
ok &= constrain_operands (reg_restore_code[i][j], 1);
}
if (! ok)
{
regno_save_mode[i][j] = VOIDmode;
if (j == 1)
{
call_fixed_regs[i] = 1;
SET_HARD_REG_BIT (call_fixed_reg_set, i);
}
}
}
end_sequence ();
obfree (first_obj);
}
static bool
copyprop_hardreg_forward_1 (basic_block bb, struct value_data *vd)
{
bool anything_changed = false;
rtx insn;
for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn))
{
int n_ops, i, alt, predicated;
bool is_asm, any_replacements;
rtx set;
rtx link;
bool replaced[MAX_RECOG_OPERANDS];
bool changed = false;
struct kill_set_value_data ksvd;
if (!NONDEBUG_INSN_P (insn))
{
if (DEBUG_INSN_P (insn))
{
rtx loc = INSN_VAR_LOCATION_LOC (insn);
if (!VAR_LOC_UNKNOWN_P (loc))
replace_oldest_value_addr (&INSN_VAR_LOCATION_LOC (insn),
ALL_REGS, GET_MODE (loc),
ADDR_SPACE_GENERIC, insn, vd);
}
if (insn == BB_END (bb))
break;
else
continue;
}
set = single_set (insn);
extract_insn (insn);
if (! constrain_operands (1))
fatal_insn_not_found (insn);
preprocess_constraints ();
alt = which_alternative;
n_ops = recog_data.n_operands;
is_asm = asm_noperands (PATTERN (insn)) >= 0;
/* Simplify the code below by rewriting things to reflect
matching constraints. Also promote OP_OUT to OP_INOUT
in predicated instructions. */
predicated = GET_CODE (PATTERN (insn)) == COND_EXEC;
for (i = 0; i < n_ops; ++i)
{
int matches = recog_op_alt[i][alt].matches;
if (matches >= 0)
recog_op_alt[i][alt].cl = recog_op_alt[matches][alt].cl;
if (matches >= 0 || recog_op_alt[i][alt].matched >= 0
|| (predicated && recog_data.operand_type[i] == OP_OUT))
recog_data.operand_type[i] = OP_INOUT;
}
/* Apply changes to earlier DEBUG_INSNs if possible. */
if (vd->n_debug_insn_changes)
note_uses (&PATTERN (insn), cprop_find_used_regs, vd);
/* For each earlyclobber operand, zap the value data. */
for (i = 0; i < n_ops; i++)
if (recog_op_alt[i][alt].earlyclobber)
kill_value (recog_data.operand[i], vd);
/* Within asms, a clobber cannot overlap inputs or outputs.
I wouldn't think this were true for regular insns, but
scan_rtx treats them like that... */
note_stores (PATTERN (insn), kill_clobbered_value, vd);
/* Kill all auto-incremented values. */
/* ??? REG_INC is useless, since stack pushes aren't done that way. */
for_each_rtx (&PATTERN (insn), kill_autoinc_value, vd);
/* Kill all early-clobbered operands. */
for (i = 0; i < n_ops; i++)
if (recog_op_alt[i][alt].earlyclobber)
kill_value (recog_data.operand[i], vd);
/* If we have dead sets in the insn, then we need to note these as we
would clobbers. */
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
{
if (REG_NOTE_KIND (link) == REG_UNUSED)
{
kill_value (XEXP (link, 0), vd);
/* Furthermore, if the insn looked like a single-set,
but the dead store kills the source value of that
set, then we can no-longer use the plain move
special case below. */
if (set
&& reg_overlap_mentioned_p (XEXP (link, 0), SET_SRC (set)))
set = NULL;
}
}
/* Special-case plain move instructions, since we may well
be able to do the move from a different register class. */
if (set && REG_P (SET_SRC (set)))
{
rtx src = SET_SRC (set);
unsigned int regno = REGNO (src);
enum machine_mode mode = GET_MODE (src);
unsigned int i;
rtx new_rtx;
/* If we are accessing SRC in some mode other that what we
set it in, make sure that the replacement is valid. */
if (mode != vd->e[regno].mode)
{
if (hard_regno_nregs[regno][mode]
> hard_regno_nregs[regno][vd->e[regno].mode])
goto no_move_special_case;
/* And likewise, if we are narrowing on big endian the transformation
is also invalid. */
if (hard_regno_nregs[regno][mode]
< hard_regno_nregs[regno][vd->e[regno].mode]
&& (GET_MODE_SIZE (vd->e[regno].mode) > UNITS_PER_WORD
? WORDS_BIG_ENDIAN : BYTES_BIG_ENDIAN))
goto no_move_special_case;
}
/* If the destination is also a register, try to find a source
register in the same class. */
if (REG_P (SET_DEST (set)))
{
new_rtx = find_oldest_value_reg (REGNO_REG_CLASS (regno), src, vd);
if (new_rtx && validate_change (insn, &SET_SRC (set), new_rtx, 0))
{
if (dump_file)
fprintf (dump_file,
"insn %u: replaced reg %u with %u\n",
INSN_UID (insn), regno, REGNO (new_rtx));
changed = true;
goto did_replacement;
}
/* We need to re-extract as validate_change clobbers
recog_data. */
extract_insn (insn);
if (! constrain_operands (1))
fatal_insn_not_found (insn);
preprocess_constraints ();
}
/* Otherwise, try all valid registers and see if its valid. */
for (i = vd->e[regno].oldest_regno; i != regno;
i = vd->e[i].next_regno)
{
new_rtx = maybe_mode_change (vd->e[i].mode, vd->e[regno].mode,
mode, i, regno);
if (new_rtx != NULL_RTX)
{
if (validate_change (insn, &SET_SRC (set), new_rtx, 0))
{
ORIGINAL_REGNO (new_rtx) = ORIGINAL_REGNO (src);
REG_ATTRS (new_rtx) = REG_ATTRS (src);
REG_POINTER (new_rtx) = REG_POINTER (src);
if (dump_file)
fprintf (dump_file,
"insn %u: replaced reg %u with %u\n",
INSN_UID (insn), regno, REGNO (new_rtx));
changed = true;
goto did_replacement;
}
/* We need to re-extract as validate_change clobbers
recog_data. */
extract_insn (insn);
if (! constrain_operands (1))
fatal_insn_not_found (insn);
preprocess_constraints ();
}
}
}
no_move_special_case:
any_replacements = false;
/* For each input operand, replace a hard register with the
eldest live copy that's in an appropriate register class. */
for (i = 0; i < n_ops; i++)
{
replaced[i] = false;
/* Don't scan match_operand here, since we've no reg class
information to pass down. Any operands that we could
substitute in will be represented elsewhere. */
if (recog_data.constraints[i][0] == '\0')
continue;
/* Don't replace in asms intentionally referencing hard regs. */
if (is_asm && REG_P (recog_data.operand[i])
&& (REGNO (recog_data.operand[i])
== ORIGINAL_REGNO (recog_data.operand[i])))
continue;
if (recog_data.operand_type[i] == OP_IN)
{
if (recog_op_alt[i][alt].is_address)
replaced[i]
= replace_oldest_value_addr (recog_data.operand_loc[i],
recog_op_alt[i][alt].cl,
VOIDmode, ADDR_SPACE_GENERIC,
insn, vd);
else if (REG_P (recog_data.operand[i]))
replaced[i]
= replace_oldest_value_reg (recog_data.operand_loc[i],
recog_op_alt[i][alt].cl,
insn, vd);
else if (MEM_P (recog_data.operand[i]))
replaced[i] = replace_oldest_value_mem (recog_data.operand[i],
insn, vd);
}
else if (MEM_P (recog_data.operand[i]))
replaced[i] = replace_oldest_value_mem (recog_data.operand[i],
insn, vd);
/* If we performed any replacement, update match_dups. */
if (replaced[i])
{
int j;
rtx new_rtx;
new_rtx = *recog_data.operand_loc[i];
recog_data.operand[i] = new_rtx;
for (j = 0; j < recog_data.n_dups; j++)
if (recog_data.dup_num[j] == i)
validate_unshare_change (insn, recog_data.dup_loc[j], new_rtx, 1);
any_replacements = true;
}
}
if (any_replacements)
{
if (! apply_change_group ())
{
for (i = 0; i < n_ops; i++)
if (replaced[i])
{
rtx old = *recog_data.operand_loc[i];
recog_data.operand[i] = old;
}
if (dump_file)
fprintf (dump_file,
"insn %u: reg replacements not verified\n",
INSN_UID (insn));
}
else
changed = true;
}
did_replacement:
if (changed)
{
anything_changed = true;
/* If something changed, perhaps further changes to earlier
DEBUG_INSNs can be applied. */
if (vd->n_debug_insn_changes)
note_uses (&PATTERN (insn), cprop_find_used_regs, vd);
}
ksvd.vd = vd;
ksvd.ignore_set_reg = NULL_RTX;
/* Clobber call-clobbered registers. */
if (CALL_P (insn))
{
unsigned int set_regno = INVALID_REGNUM;
unsigned int set_nregs = 0;
unsigned int regno;
rtx exp;
for (exp = CALL_INSN_FUNCTION_USAGE (insn); exp; exp = XEXP (exp, 1))
{
rtx x = XEXP (exp, 0);
if (GET_CODE (x) == SET)
{
rtx dest = SET_DEST (x);
kill_value (dest, vd);
set_value_regno (REGNO (dest), GET_MODE (dest), vd);
copy_value (dest, SET_SRC (x), vd);
ksvd.ignore_set_reg = dest;
set_regno = REGNO (dest);
set_nregs
= hard_regno_nregs[set_regno][GET_MODE (dest)];
break;
}
}
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
if ((TEST_HARD_REG_BIT (regs_invalidated_by_call, regno)
|| HARD_REGNO_CALL_PART_CLOBBERED (regno, vd->e[regno].mode))
&& (regno < set_regno || regno >= set_regno + set_nregs))
kill_value_regno (regno, 1, vd);
/* If SET was seen in CALL_INSN_FUNCTION_USAGE, and SET_SRC
of the SET isn't in regs_invalidated_by_call hard reg set,
but instead among CLOBBERs on the CALL_INSN, we could wrongly
assume the value in it is still live. */
if (ksvd.ignore_set_reg)
{
note_stores (PATTERN (insn), kill_clobbered_value, vd);
for (exp = CALL_INSN_FUNCTION_USAGE (insn);
exp;
exp = XEXP (exp, 1))
{
rtx x = XEXP (exp, 0);
if (GET_CODE (x) == CLOBBER)
kill_value (SET_DEST (x), vd);
}
}
}
/* Notice stores. */
note_stores (PATTERN (insn), kill_set_value, &ksvd);
/* Notice copies. */
if (set && REG_P (SET_DEST (set)) && REG_P (SET_SRC (set)))
copy_value (SET_DEST (set), SET_SRC (set), vd);
if (insn == BB_END (bb))
break;
}
return anything_changed;
}
static int
reload_cse_simplify_operands (rtx insn, rtx testreg)
{
int i, j;
/* For each operand, all registers that are equivalent to it. */
HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
const char *constraints[MAX_RECOG_OPERANDS];
/* Vector recording how bad an alternative is. */
int *alternative_reject;
/* Vector recording how many registers can be introduced by choosing
this alternative. */
int *alternative_nregs;
/* Array of vectors recording, for each operand and each alternative,
which hard register to substitute, or -1 if the operand should be
left as it is. */
int *op_alt_regno[MAX_RECOG_OPERANDS];
/* Array of alternatives, sorted in order of decreasing desirability. */
int *alternative_order;
extract_insn (insn);
if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
return 0;
/* Figure out which alternative currently matches. */
if (! constrain_operands (1))
fatal_insn_not_found (insn);
alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives);
alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives);
alternative_order = XALLOCAVEC (int, recog_data.n_alternatives);
memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
/* For each operand, find out which regs are equivalent. */
for (i = 0; i < recog_data.n_operands; i++)
{
cselib_val *v;
struct elt_loc_list *l;
rtx op;
enum machine_mode mode;
CLEAR_HARD_REG_SET (equiv_regs[i]);
/* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
right, so avoid the problem here. Likewise if we have a constant
and the insn pattern doesn't tell us the mode we need. */
if (LABEL_P (recog_data.operand[i])
|| (CONSTANT_P (recog_data.operand[i])
&& recog_data.operand_mode[i] == VOIDmode))
continue;
op = recog_data.operand[i];
mode = GET_MODE (op);
#ifdef LOAD_EXTEND_OP
if (MEM_P (op)
&& GET_MODE_BITSIZE (mode) < BITS_PER_WORD
&& LOAD_EXTEND_OP (mode) != UNKNOWN)
{
rtx set = single_set (insn);
/* We might have multiple sets, some of which do implicit
extension. Punt on this for now. */
if (! set)
continue;
/* If the destination is also a MEM or a STRICT_LOW_PART, no
extension applies.
Also, if there is an explicit extension, we don't have to
worry about an implicit one. */
else if (MEM_P (SET_DEST (set))
|| GET_CODE (SET_DEST (set)) == STRICT_LOW_PART
|| GET_CODE (SET_SRC (set)) == ZERO_EXTEND
|| GET_CODE (SET_SRC (set)) == SIGN_EXTEND)
; /* Continue ordinary processing. */
#ifdef CANNOT_CHANGE_MODE_CLASS
/* If the register cannot change mode to word_mode, it follows that
it cannot have been used in word_mode. */
else if (REG_P (SET_DEST (set))
&& CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
word_mode,
REGNO_REG_CLASS (REGNO (SET_DEST (set)))))
; /* Continue ordinary processing. */
#endif
/* If this is a straight load, make the extension explicit. */
else if (REG_P (SET_DEST (set))
&& recog_data.n_operands == 2
&& SET_SRC (set) == op
&& SET_DEST (set) == recog_data.operand[1-i])
{
validate_change (insn, recog_data.operand_loc[i],
gen_rtx_fmt_e (LOAD_EXTEND_OP (mode),
word_mode, op),
1);
validate_change (insn, recog_data.operand_loc[1-i],
gen_rtx_REG (word_mode, REGNO (SET_DEST (set))),
1);
if (! apply_change_group ())
return 0;
return reload_cse_simplify_operands (insn, testreg);
}
else
/* ??? There might be arithmetic operations with memory that are
safe to optimize, but is it worth the trouble? */
continue;
}
#endif /* LOAD_EXTEND_OP */
v = cselib_lookup (op, recog_data.operand_mode[i], 0);
if (! v)
continue;
for (l = v->locs; l; l = l->next)
if (REG_P (l->loc))
SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
}
for (i = 0; i < recog_data.n_operands; i++)
{
enum machine_mode mode;
int regno;
const char *p;
op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives);
for (j = 0; j < recog_data.n_alternatives; j++)
op_alt_regno[i][j] = -1;
p = constraints[i] = recog_data.constraints[i];
mode = recog_data.operand_mode[i];
/* Add the reject values for each alternative given by the constraints
for this operand. */
j = 0;
while (*p != '\0')
{
char c = *p++;
if (c == ',')
j++;
else if (c == '?')
alternative_reject[j] += 3;
else if (c == '!')
alternative_reject[j] += 300;
}
/* We won't change operands which are already registers. We
also don't want to modify output operands. */
regno = true_regnum (recog_data.operand[i]);
if (regno >= 0
|| constraints[i][0] == '='
|| constraints[i][0] == '+')
continue;
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
{
int rclass = (int) NO_REGS;
if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
continue;
SET_REGNO (testreg, regno);
PUT_MODE (testreg, mode);
/* We found a register equal to this operand. Now look for all
alternatives that can accept this register and have not been
assigned a register they can use yet. */
j = 0;
p = constraints[i];
for (;;)
{
char c = *p;
switch (c)
{
case '=': case '+': case '?':
case '#': case '&': case '!':
case '*': case '%':
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
case '<': case '>': case 'V': case 'o':
case 'E': case 'F': case 'G': case 'H':
case 's': case 'i': case 'n':
case 'I': case 'J': case 'K': case 'L':
case 'M': case 'N': case 'O': case 'P':
case 'p': case 'X': case TARGET_MEM_CONSTRAINT:
/* These don't say anything we care about. */
break;
case 'g': case 'r':
rclass = reg_class_subunion[(int) rclass][(int) GENERAL_REGS];
break;
default:
rclass
= (reg_class_subunion
[(int) rclass]
[(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
break;
case ',': case '\0':
/* See if REGNO fits this alternative, and set it up as the
replacement register if we don't have one for this
alternative yet and the operand being replaced is not
a cheap CONST_INT. */
if (op_alt_regno[i][j] == -1
&& reg_fits_class_p (testreg, rclass, 0, mode)
&& (GET_CODE (recog_data.operand[i]) != CONST_INT
|| (rtx_cost (recog_data.operand[i], SET,
optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))
> rtx_cost (testreg, SET,
optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn))))))
{
alternative_nregs[j]++;
op_alt_regno[i][j] = regno;
}
j++;
rclass = (int) NO_REGS;
break;
}
p += CONSTRAINT_LEN (c, p);
if (c == '\0')
break;
}
}
}
/* Record all alternatives which are better or equal to the currently
matching one in the alternative_order array. */
for (i = j = 0; i < recog_data.n_alternatives; i++)
if (alternative_reject[i] <= alternative_reject[which_alternative])
alternative_order[j++] = i;
recog_data.n_alternatives = j;
/* Sort it. Given a small number of alternatives, a dumb algorithm
won't hurt too much. */
for (i = 0; i < recog_data.n_alternatives - 1; i++)
{
int best = i;
int best_reject = alternative_reject[alternative_order[i]];
int best_nregs = alternative_nregs[alternative_order[i]];
int tmp;
for (j = i + 1; j < recog_data.n_alternatives; j++)
{
int this_reject = alternative_reject[alternative_order[j]];
int this_nregs = alternative_nregs[alternative_order[j]];
if (this_reject < best_reject
|| (this_reject == best_reject && this_nregs > best_nregs))
{
best = j;
best_reject = this_reject;
best_nregs = this_nregs;
}
}
tmp = alternative_order[best];
alternative_order[best] = alternative_order[i];
alternative_order[i] = tmp;
}
/* Substitute the operands as determined by op_alt_regno for the best
alternative. */
j = alternative_order[0];
for (i = 0; i < recog_data.n_operands; i++)
{
enum machine_mode mode = recog_data.operand_mode[i];
if (op_alt_regno[i][j] == -1)
continue;
validate_change (insn, recog_data.operand_loc[i],
gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
}
for (i = recog_data.n_dups - 1; i >= 0; i--)
{
int op = recog_data.dup_num[i];
enum machine_mode mode = recog_data.operand_mode[op];
if (op_alt_regno[op][j] == -1)
continue;
validate_change (insn, recog_data.dup_loc[i],
gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
}
return apply_change_group ();
}
