static void __gptimer_set_mode(enum clock_event_mode mode,
struct clock_event_device *c)
{
unsigned int saved;
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
__gptimer_ctl(EVENT_TIMER, TIMER_DISABLE, PERIOD_MODE);
__raw_writel(LATCH, TIMER_LOAD(EVENT_TIMER));
__gptimer_ctl(EVENT_TIMER, TIMER_ENABLE, PERIOD_MODE);
__raw_writel(TIMER_INT_EN, TIMER_INT(EVENT_TIMER));
break;
case CLOCK_EVT_MODE_ONESHOT:
__gptimer_ctl(EVENT_TIMER, TIMER_ENABLE, ONETIME_MODE);
__raw_writel(TIMER_INT_EN, TIMER_INT(EVENT_TIMER));
break;
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_UNUSED:
saved = __raw_readl(TIMER_CTL(EVENT_TIMER)) & PERIOD_MODE;
__gptimer_ctl(EVENT_TIMER, TIMER_DISABLE, saved);
break;
case CLOCK_EVT_MODE_RESUME:
saved = __raw_readl(TIMER_CTL(EVENT_TIMER)) & PERIOD_MODE;
__gptimer_ctl(EVENT_TIMER, TIMER_ENABLE, saved);
break;
}
}
static irqreturn_t __gptimer_interrupt(int irq, void *dev_id)
{
unsigned int value;
struct clock_event_device *evt = dev_id;
value = __raw_readl(TIMER_INT(EVENT_TIMER));
value |= TIMER_INT_CLR;
__raw_writel(value, TIMER_INT(EVENT_TIMER));
if (evt->event_handler)
evt->event_handler(evt);
return IRQ_HANDLED;
}
void sec_debug_print_gptimer_reg(void)
{
printk("%s: gptimer-clockevent\n",__func__);
printk("load reg: 0x%x\n",__raw_readl(TIMER_LOAD(0,0)));
printk("value reg: 0x%x\n",__raw_readl(TIMER_VALUE(0,0)));
printk("control reg: 0x%x\n",__raw_readl(TIMER_CTL(0,0)));
printk("interrupt reg: 0x%x\n",__raw_readl(TIMER_INT(0,0)));
printk("%s: gptimer-clocksource\n",__func__);
printk("load reg: 0x%x\n",__raw_readl(TIMER_LOAD(0,2)));
printk("value reg: 0x%x\n",__raw_readl(TIMER_VALUE(0,2)));
printk("control reg: 0x%x\n",__raw_readl(TIMER_CTL(0,2)));
printk("interrupt reg: 0x%x\n",__raw_readl(TIMER_INT(0,2)));
}
static int __bctimer_set_next_event(unsigned long cycles,
struct clock_event_device *c)
{
while (TIMER_INT_BUSY & __raw_readl(TIMER_INT(BC_CPU, BC_TIMER))) ;
__gptimer_ctl(BC_CPU, BC_TIMER, TIMER_DISABLE, ONETIME_MODE);
__raw_writel(cycles, TIMER_LOAD(BC_CPU, BC_TIMER));
__gptimer_ctl(BC_CPU, BC_TIMER, TIMER_ENABLE, ONETIME_MODE);
return 0;
}
static int __gptimer_set_next_event(unsigned long cycles,
struct clock_event_device *c)
{
int cpu = smp_processor_id();
while (TIMER_INT_BUSY & __raw_readl(TIMER_INT(cpu, EVENT_TIMER))) ;
__gptimer_ctl(cpu, EVENT_TIMER, TIMER_DISABLE, ONETIME_MODE);
__raw_writel(cycles, TIMER_LOAD(cpu, EVENT_TIMER));
__gptimer_ctl(cpu, EVENT_TIMER, TIMER_ENABLE, ONETIME_MODE);
return 0;
}
/* ****************************************************************** */
static void __gptimer_clocksource_init(const char *name, unsigned long hz)
{
/* disalbe irq since it's just a read source */
__raw_writel(0, TIMER_INT(SOURCE_TIMER));
__gptimer_ctl(SOURCE_TIMER, TIMER_DISABLE, PERIOD_MODE);
__raw_writel(ULONG_MAX, TIMER_LOAD(SOURCE_TIMER));
__gptimer_ctl(SOURCE_TIMER, TIMER_ENABLE, PERIOD_MODE);
clocksource_mmio_init(TIMER_VALUE(SOURCE_TIMER), name,
hz, 300, 32, clocksource_mmio_readl_down);
}
static void sprd_gptimer_clockevent_init(unsigned int irq, const char *name,
unsigned long hz)
{
struct clock_event_device *evt = &gptimer_event;
__raw_writel(TIMER_DISABLE, TIMER_CTL(EVENT_TIMER));
__raw_writel(TIMER_INT_CLR, TIMER_INT(EVENT_TIMER));
evt->name = name;
evt->irq = irq;
evt->mult = div_sc(hz, NSEC_PER_SEC, evt->shift);
evt->max_delta_ns = clockevent_delta2ns(ULONG_MAX, evt);
evt->min_delta_ns = clockevent_delta2ns(2, evt);
evt->cpumask = cpu_all_mask;
setup_irq(irq, &gptimer_irq);
clockevents_register_device(evt);
}
void __init sci_enable_timer_early(void)
{
/* enable timer & syscnt in global regs */
int i = 0, j = 0;
sci_glb_set(REG_AON_APB_APB_EB0,
BIT_AON_TMR_EB | BIT_AP_SYST_EB | BIT_AP_TMR0_EB);
#if defined CONFIG_LOCAL_TIMERS && !defined CONFIG_HAVE_ARM_ARCH_TIMER
sci_glb_set(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB);
for (i = 0; i < 4; i++) {
#else
sci_glb_clr(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB);
for (i = 0; i < 2; i++) {
#endif
for (j = 0; j < 3; j++) {
__gptimer_ctl(i, j, TIMER_DISABLE, 0);
__raw_writel(TIMER_INT_CLR, TIMER_INT(i, j));
}
}
#if defined(CONFIG_ARCH_SCX30G) || defined(CONFIG_ARCH_SCX35L)
/*timer1 fixed 32768 clk */
sched_clock_source_freq = 32768;
#else /*timer2 clk source is from apb clk */
val = sci_glb_read(REG_AON_CLK_AON_APB_CFG, -1) & 0x3;
if (val == 0x1)
sched_clock_source_freq = 76800000;
else if (val == 0x2)
sched_clock_source_freq = 96000000;
else if (val == 0x3)
sched_clock_source_freq = 128000000;
else
sched_clock_source_freq = 26000000; /*default setting */
#endif
gptimer_clock_source_freq = sched_clock_source_freq;
#if !defined (CONFIG_HAVE_ARM_ARCH_TIMER)
__sched_clock_init(sched_clock_source_freq);
#endif
}
u32 get_sys_cnt(void)
{
u32 val = 0;
val = __raw_readl(SYSCNT_SHADOW_CNT);
return val;
}
static void __gptimer_clocksource_init(void)
{
/* disalbe irq since it's just a read source */
__raw_writel(0, TIMER_INT(e_cpu, SOURCE_TIMER));
__gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_DISABLE | TIMER_NEW,
PERIOD_MODE);
__raw_writel(ULONG_MAX, TIMER_LOAD(e_cpu, SOURCE_TIMER));
__gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_NEW, PERIOD_MODE);
__gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_ENABLE | TIMER_NEW,
PERIOD_MODE);
if (clocksource_register_hz
(&clocksource_sprd, gptimer_clock_source_freq))
printk("%s: can't register clocksource\n",
clocksource_sprd.name);
}
