status_t platform_set_oneshot_timer (platform_timer_callback callback, void *arg, lk_time_t interval)
{
LTRACEF("callback %p, arg %p, timeout %lu\n", callback, arg, interval);
uint64_t ticks = u64_mul_u64_fp32_64(interval, timer_freq_msec_conversion);
if (unlikely(ticks == 0))
ticks = 1;
if (unlikely(ticks > 0xffffffff))
ticks = 0xffffffff;
enter_critical_section();
t_callback = callback;
oneshot_interval = interval;
// disable timer
TIMREG(TIMER_CONTROL) = 0;
TIMREG(TIMER_LOAD) = ticks;
TIMREG(TIMER_CONTROL) = (1<<2) | (1<<0) | (1<<0); // irq enable, oneshot, enable
exit_critical_section();
return NO_ERROR;
}
status_t platform_set_oneshot_timer (platform_timer_callback callback, void *arg, lk_time_t interval)
{
LTRACEF("callback %p, arg %p, timeout %u\n", callback, arg, interval);
uint64_t ticks = u64_mul_u64_fp32_64(interval, timer_freq_msec_conversion);
if (unlikely(ticks == 0))
ticks = 1;
if (unlikely(ticks > 0xffffffff))
ticks = 0xffffffff;
spin_lock_saved_state_t state;
spin_lock_irqsave(&lock, state);
t_callback = callback;
oneshot_interval = interval;
// disable timer
TIMREG(TIMER_CONTROL) = 0;
TIMREG(TIMER_LOAD) = ticks;
TIMREG(TIMER_CONTROL) = (1<<2) | (1<<0) | (1<<0); // irq enable, oneshot, enable
spin_unlock_irqrestore(&lock, state);
return NO_ERROR;
}
void platform_init_timer(void)
{
/* disable timer */
TIMREG(CONTROL) = 0;
/* periodic mode, ints enabled, 32bit, wrapping */
TIMREG(CONTROL) = (1<<6)|(1<<5)|(1<<1);
register_int_handler(TIMER01_INT, &platform_tick, NULL);
}
void platform_init_timer(void)
{
/* disable timers */
TIMREG(CNT_CTRL(0)) = 0x1;
TIMREG(CNT_CTRL(1)) = 0x1;
TIMREG(CNT_CTRL(2)) = 0x1;
TIMREG(CLK_CTRL(0)) = (6 << 1) | 1; // prescale 133Mhz/(2^7) == 1039062Hz (close to 1Mhz)
register_int_handler(TTC0_A_INT, &platform_tick, NULL);
register_int_handler(TTC0_B_INT, &platform_tick, NULL);
register_int_handler(TTC0_C_INT, &platform_tick, NULL);
}
static void arm_cortex_a9_timer_init_percpu(uint level)
{
/* disable timer */
TIMREG(TIMER_CONTROL) = 0;
/* kill the watchdog */
TIMREG(WDOG_CONTROL) = 0;
/* ack any irqs that may be pending */
TIMREG(TIMER_ISR) = 1;
/* register the platform tick on each cpu */
register_int_handler(CPU_PRIV_TIMER_INT, &platform_tick, NULL);
unmask_interrupt(CPU_PRIV_TIMER_INT);
}
status_t platform_set_periodic_timer(platform_timer_callback callback, void *arg, lk_time_t interval)
{
enter_critical_section();
t_callback = callback;
periodic_interval = interval;
TIMREG(LOADVAL) = periodic_interval * 1000; /* timer is running at 1Mhz */
TIMREG(CONTROL) |= (1<<7); // enable
unmask_interrupt(TIMER01_INT);
exit_critical_section();
return NO_ERROR;
}
static enum handler_return platform_tick(void *arg)
{
ticks++;
TIMREG(INTCLEAR) = 1;
if (t_callback) {
return t_callback(arg, current_time());
} else {
return INT_NO_RESCHEDULE;
}
}
static enum handler_return platform_tick(void *arg)
{
LTRACE;
TIMREG(TIMER_ISR) = 1; // ack the irq
if (t_callback) {
return t_callback(arg, current_time());
} else {
return INT_NO_RESCHEDULE;
}
}
static enum handler_return platform_tick(void *arg)
{
ticks++;
volatile uint32_t hole = TIMREG(ISR(0)); // ack the irq
if (t_callback) {
return t_callback(arg, current_time());
} else {
return INT_NO_RESCHEDULE;
}
}
status_t platform_set_periodic_timer(platform_timer_callback callback, void *arg, lk_time_t interval)
{
enter_critical_section();
LTRACEF("callback %p, arg %p, interval %lu\n", callback, arg, interval);
t_callback = callback;
periodic_interval = interval;
uint32_t ticks = periodic_interval * 1000; /* timer is running close to 1Mhz */
ASSERT(ticks <= 0xffff);
TIMREG(IEN(0)) = (1<<0); // interval interrupt
TIMREG(INTERVAL_VAL(0)) = ticks;
TIMREG(CNT_CTRL(0)) = (1<<5) | (1<<4) | (1<<1); // no wave, reset, interval mode
unmask_interrupt(TTC0_A_INT);
exit_critical_section();
return NO_ERROR;
}
void arm_cortex_a9_timer_init(addr_t _scu_control_base, uint32_t freq)
{
scu_control_base = _scu_control_base;
/* disable timer */
TIMREG(TIMER_CONTROL) = 0;
/* kill the watchdog */
TIMREG(WDOG_CONTROL) = 0;
/* ack any irqs that may be pending */
TIMREG(TIMER_ISR) = 1;
/* save the timer frequency for later calculations */
timer_freq = freq;
/* precompute the conversion factor for global time to real time */
fp_32_64_div_32_32(&timer_freq_msec_conversion, timer_freq, 1000);
fp_32_64_div_32_32(&timer_freq_usec_conversion_inverse, 1000000, timer_freq);
fp_32_64_div_32_32(&timer_freq_msec_conversion_inverse, 1000, timer_freq);
register_int_handler(CPU_PRIV_TIMER_INT, &platform_tick, NULL);
unmask_interrupt(CPU_PRIV_TIMER_INT);
}
void platform_stop_timer(void)
{
LTRACE;
TIMREG(TIMER_CONTROL) = 0;
}
