void torture_setup ( void ) {
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN);
timer_reset(TIM3);
// 24Mhz / 10khz -1.
timer_set_prescaler(TIM3, 20000); // 24Mhz/10000hz - 1
// 10khz for 10 ticks = 1 khz overflow = 1ms overflow interrupts
timer_set_period(TIM3, 1);
/* Set timer start value. */
TIM_CNT(TIM3) = 1;
/* Set timer prescaler. */
TIM_PSC(TIM3) = 100; // 100 .. so about 840000 ticks per second
/* End timer value. If this is reached an interrupt is generated. */
TIM_ARR(TIM3) = 60; // 840000/14 -> 60,000/sec
nvic_enable_irq(NVIC_TIM3_IRQ);
timer_enable_update_event(TIM3); // default at reset!
timer_enable_irq(TIM3, TIM_DIER_UIE);
timer_enable_counter(TIM3);
}
static void timer2_setup ( void ) {
//timer_reset ( TIM2 );
//timer_set_mode
//timer_continuous_mode ( TIM2 );
/* Set timer start value. */
TIM_CNT(TIM2) = 1;
/* Set timer prescaler. 72MHz/1440 => 50000 counts per second. */
TIM_PSC(TIM2) = 300; // 280K/s or 0.000 003 571
/* End timer value. If this is reached an interrupt is generated. */
TIM_ARR(TIM2) = 8; //
// o-scope reports:
// prescale 2000, 1->600 should be 100/sec; in fact, we're exactly 20ms between which is exactly 50 .. so callback is 60MHz, not 120MHz
// manual says:
// The reference manual (see page 133) states that the GPIO is capable of:
// Fast toggle capable of changing every two clock cycles
// --> okay so at 120MHz, the best we can do is 60MHz of GPIO. But thats different than here, where the timer seems halved..
/* Update interrupt enable. */
TIM_DIER(TIM2) |= TIM_DIER_UIE;
//timer_set_repetition_counter ( TIM2, 100 );
/* Start timer. */
TIM_CR1(TIM2) |= TIM_CR1_CEN;
return;
}
int main(void)
{
rcc_clock_setup_in_hse_16mhz_out_72mhz();
gpio_setup();
nvic_setup();
gpio_clear(GPIOB, GPIO7); /* LED1 on */
gpio_set(GPIOB, GPIO6); /* LED2 off */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
/* the goal is to let the LED2 glow for a second and then be off for a second */
/* Set timer start value */
TIM_CNT(TIM2) = 1;
/* Set timer prescaler. 72MHz/1440 => 50000 counts per second */
TIM_PSC(TIM2) = 1440;
/* End timer value. If this value is reached an interrupt is generated */
TIM_ARR(TIM2) = 50000;
/* Update interrupt enable */
TIM_DIER(TIM2) |= TIM_DIER_UIE;
/* Start timer */
TIM_CR1(TIM2) |= TIM_CR1_CEN;
while(1); /* Halt. */
return 0;
}
/**
* @brief Initializes the AEAT9000 SSI Link
* @param u16 clk_speed SSI Clock Speed in 100bps LSB units
*/
void ssi_initialize(u16 clk_speed)
{
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN); // Initialize timer clk
// Initialize I/O Pins
gpio_set_mode(SSI_GPIO, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, SSI_CLK_PIN);
gpio_set_mode(SSI_GPIO, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, SSI_DATA_PIN);
gpio_set_mode(SSI_GPIO, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, SSI_NCS_PIN);
// Initialize clock timer on TIM1
TIM_DIER(SSI_TIMER) = TIM_DIER_UIE;
TIM_PSC(SSI_TIMER) = 1; // 24MHz Clock
TIM_ARR(SSI_TIMER) = TIMER_MAX; // Update at 500kHz
// Initialize NVIC
nvic_enable_irq(NVIC_TIM2_IRQ);
nvic_set_priority(NVIC_TIM2_IRQ, 1);
ssi_state = SSI_IDLE;
ssi_data_ready_flag = false;
}
void setupPWM()
{
gpio_mode_setup(LED_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, LED_R_PIN | LED_G_PIN);
gpio_set_output_options(LED_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, LED_R_PIN | LED_G_PIN);
gpio_set_af(LED_PORT, GPIO_AF1, LED_R_PIN | LED_G_PIN);
TIM_CCMR1(RGB_TIMER) = TIM_CCMR1_OC1M_PWM1 | TIM_CCMR1_OC2M_PWM1;
TIM_CCER(RGB_TIMER) = TIM_CCER_CC1E | TIM_CCER_CC2E;
TIM_PSC(RGB_TIMER) = 1000;
TIM_ARR(RGB_TIMER) = 0xff;
TIM_CR1(RGB_TIMER) = TIM_CR1_CEN;
g_isRedBlinking = false;
setLEDColor(127, 127, 0);
}
void timer1_setup()
{
// Timer 1 a 2MHz
/* Set timer start value */
TIM_CNT(TIM1) = 1;
/* Set timer prescaler. 72MHz/36 => 2MHz counts per second */
TIM_PSC(TIM1) = 36; // 2MHz
/* End timer value. If this value is reached an interrupt is generated */
TIM_ARR(TIM1) = 60000; // 1kHz
/* Update interrupt enable */
// TIM_DIER(TIM1) |= TIM_DIER_UIE;
/* Start timer */
TIM_CR1(TIM1) |= TIM_CR1_CEN;
}
void timer_set_prescaler(u32 timer_peripheral, u32 value)
{
TIM_PSC(timer_peripheral) = value;
}
bool Pwm_stm32::init(void)
{
bool success = true;
/* Enable peripheral port & TIM clock. */
//rcc_periph_clock_enable(RCC_GPIOx);
rcc_periph_clock_enable(pwm_config_.rcc_timer_config);
gpio_mode_setup(pwm_config_.gpio_config.port, GPIO_MODE_AF, GPIO_PUPD_NONE, pwm_config_.gpio_config.pin);
gpio_set_af(pwm_config_.gpio_config.port, pwm_config_.gpio_config.alt_fct, pwm_config_.gpio_config.pin);
gpio_set_output_options(pwm_config_.gpio_config.port, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, pwm_config_.gpio_config.port);
//WARNING Common to all channels of that TIMER
//select prescaler
TIM_PSC(pwm_config_.timer_config) = prescaler_;
//select the output period
TIM_ARR(pwm_config_.timer_config) = period_;
//enable the autoreload
TIM_CR1(pwm_config_.timer_config) |= TIM_CR1_ARPE;
//select counting mode (edge-aligned)
TIM_CR1(pwm_config_.timer_config) |= TIM_CR1_CMS_EDGE;
//counting up
TIM_CR1(pwm_config_.timer_config) |= TIM_CR1_DIR_UP;
//enable counter
TIM_CR1(pwm_config_.timer_config) |= TIM_CR1_CEN;
//CHANNEL SPECIFIC
if (pwm_config_.channel_config == PWM_STM32_CHANNEL_1)
{
//Disable channel1
TIM_CCER(pwm_config_.timer_config) &= (uint16_t)~TIM_CCER_CC1E;
//Reset output compare
TIM_CCMR1(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR1_OC1M_MASK;
TIM_CCMR1(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR1_CC1S_MASK;
//Select output mode
TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_CC1S_OUT;
//select polarity low
TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC1NP;
//select PWM mode 1
TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_OC1M_PWM1;
//select duty cycle
TIM_CCR1(pwm_config_.timer_config) = duty_cyle_;
//set the preload bit
TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_OC1PE;
//enable capture/compare
TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC1E;
}
else if (pwm_config_.channel_config == PWM_STM32_CHANNEL_2)
{
//Disable channel2
TIM_CCER(pwm_config_.timer_config) &= (uint16_t)~TIM_CCER_CC2E;
//Reset output compare
TIM_CCMR1(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR1_OC2M_MASK;
TIM_CCMR1(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR1_CC2S_MASK;
//Select output mode
TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_CC2S_OUT;
//select polarity low
TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC2NP;
//select PWM mode 1
TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_OC2M_PWM1;
//select duty cycle
TIM_CCR2(pwm_config_.timer_config) = duty_cyle_;
//set the preload bit
TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_OC2PE;
//enable capture/compare
TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC2E;
}
else if (pwm_config_.channel_config == PWM_STM32_CHANNEL_3)
{
//Disable channel3
TIM_CCER(pwm_config_.timer_config) &= (uint16_t)~TIM_CCER_CC3E;
//Reset output compare
TIM_CCMR2(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR2_OC3M_MASK;
TIM_CCMR2(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR2_CC3S_MASK;
//Select output mode
TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_CC3S_OUT;
//select polarity low
TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC3NP;
//select PWM mode 1
TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_OC3M_PWM1;
//select duty cycle
TIM_CCR3(pwm_config_.timer_config) = duty_cyle_;
//set the preload bit
TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_OC3PE;
//enable capture/compare
TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC3E;
}
else if (pwm_config_.channel_config == PWM_STM32_CHANNEL_4)
{
//Disable channel4
TIM_CCER(pwm_config_.timer_config) &= (uint16_t)~TIM_CCER_CC4E;
//Reset output compare
TIM_CCMR2(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR2_OC4M_MASK;
TIM_CCMR2(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR2_CC4S_MASK;
//Select output mode
TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_CC4S_OUT;
//select polarity low
TIM_CCER(pwm_config_.timer_config) |= (1 << 15); //TODO TIM_CCER_CC4NP does not exist in libopencm3 library
//select PWM mode 1
TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_OC4M_PWM1;
//select duty cycle
TIM_CCR4(pwm_config_.timer_config) = duty_cyle_;
//set the preload bit
TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_OC4PE;
//enable capture/compare
TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC4E;
}
return success;
}
