static int __init pmc_yosemite_setup(void)
{
unsigned long io_v_base;
io_v_base = (unsigned long) ioremap(TITAN_IO_BASE, TITAN_IO_SIZE);
if (!io_v_base)
panic(ioremap_failed);
set_io_port_base(io_v_base);
TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
ioport_resource.end = TITAN_IO_SIZE - 1;
register_pci_controller(&py_controller);
return 0;
}
/*
* Titan PCI Config Read Byte
*/
static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
int size, u32 * val)
{
int dev, bus, func;
uint32_t address_reg, data_reg;
uint32_t address;
bus = device->bus->number;
dev = PCI_SLOT(device->devfn);
func = PCI_FUNC(device->devfn);
address_reg = TITAN_PCI_0_CONFIG_ADDRESS;
data_reg = TITAN_PCI_0_CONFIG_DATA;
address = (bus << 16) | (dev << 11) | (func << 8) |
(offset & 0xfc) | 0x80000000;
/* start the configuration cycle */
TITAN_WRITE(address_reg, address);
switch (size) {
case 1:
TITAN_READ_8(data_reg + (offset & 0x3), val);
break;
case 2:
TITAN_READ_16(data_reg + (offset & 0x2), val);
break;
case 4:
TITAN_READ(data_reg, val);
break;
}
return PCIBIOS_SUCCESSFUL;
}
