uint8_t TM_USART_DMA_Sending(USART_TypeDef* USARTx) {
/* Get USART settings */
TM_USART_DMA_INT_t* Settings = TM_USART_DMA_INT_GetSettings(USARTx);
/* Check DMA Stream register of remaining data bytes */
return Settings->DMA_Stream->NDTR;
}
void TM_USART_DMA_Init(USART_TypeDef* USARTx) {
/* Init DMA TX mode */
/* Assuming USART is already initialized and clock is enabled */
/* Get USART settings */
TM_USART_DMA_INT_t* USART_Settings = TM_USART_DMA_INT_GetSettings(USARTx);
/* Enable DMA clock */
if (USART_Settings->DMA_Stream >= DMA2_Stream0) {
/* Enable DMA2 clock */
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
} else {
/* Enable DMA1 clock */
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
}
/* Set DMA options */
DMA_InitStruct.DMA_DIR = DMA_DIR_MemoryToPeripheral;
DMA_InitStruct.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStruct.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStruct.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStruct.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStruct.DMA_Mode = DMA_Mode_Normal;
DMA_InitStruct.DMA_Priority = DMA_Priority_Low;
DMA_InitStruct.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStruct.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
DMA_InitStruct.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStruct.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
}
void TM_USART_DMA_Deinit(USART_TypeDef* USARTx) {
/* Get USART settings */
TM_USART_DMA_INT_t* Settings = TM_USART_DMA_INT_GetSettings(USARTx);
/* Deinit DMA Stream */
DMA_DeInit(Settings->DMA_Stream);
}
uint8_t TM_USART_DMA_Send(USART_TypeDef* USARTx, uint8_t* DataArray, uint16_t count) {
/* Get USART settings */
TM_USART_DMA_INT_t* Settings = TM_USART_DMA_INT_GetSettings(USARTx);
/* Check if DMA is working now */
if (Settings->DMA_Stream->NDTR) {
/* DMA works right now */
return 0;
}
/* Set DMA options */
DMA_InitStruct.DMA_Channel = Settings->DMA_Channel;
DMA_InitStruct.DMA_BufferSize = count;
DMA_InitStruct.DMA_PeripheralBaseAddr = (uint32_t) &USARTx->DR;
DMA_InitStruct.DMA_Memory0BaseAddr = (uint32_t) &DataArray[0];
/* Deinit first, clear all flags */
DMA_DeInit(Settings->DMA_Stream);
/* Init DMA */
DMA_Init(Settings->DMA_Stream, &DMA_InitStruct);
/* Enable USART TX DMA */
USARTx->CR3 |= USART_CR3_DMAT;
/* Enable DMA Stream */
Settings->DMA_Stream->CR |= DMA_SxCR_EN;
/* DMA has started */
return 1;
}
void TM_USART_DMA_DisableInterrupts(USART_TypeDef* USARTx) {
/* Get USART settings */
TM_USART_DMA_INT_t* Settings = TM_USART_DMA_INT_GetSettings(USARTx);
/* Disable DMA interrupts */
TM_DMA_DisableInterrupts(Settings->DMA_Stream);
}
void TM_USART_DMA_InitWithStreamAndChannel(USART_TypeDef* USARTx, DMA_Stream_TypeDef* DMA_Stream, uint32_t DMA_Channel) {
/* Get USART settings */
TM_USART_DMA_INT_t* Settings = TM_USART_DMA_INT_GetSettings(USARTx);
/* Set DMA stream and channel */
Settings->DMA_Stream = DMA_Stream;
Settings->DMA_Channel = DMA_Channel;
/* Init DMA TX */
TM_USART_DMA_Init(USARTx);
}
uint16_t TM_USART_DMA_Sending(USART_TypeDef* USARTx) {
/* Get USART settings */
TM_USART_DMA_INT_t* Settings = TM_USART_DMA_INT_GetSettings(USARTx);
/* DMA has work to do still */
if (Settings->DMA_Stream->NDTR) {
return 1;
}
/* Check DMA Stream register of remaining data bytes */
return !USART_TXEMPTY(USARTx);
}
void TM_USART_DMA_Init(USART_TypeDef* USARTx) {
/* Init DMA TX mode */
/* Assuming USART is already initialized and clock is enabled */
/* Get USART settings */
TM_USART_DMA_INT_t* Settings = TM_USART_DMA_INT_GetSettings(USARTx);
/* Init stream */
TM_DMA_Init(Settings->DMA_Stream, NULL);
/* Clear flags */
TM_DMA_ClearFlags(Settings->DMA_Stream);
/* Disable stream */
Settings->DMA_Stream->CR &= ~DMA_SxCR_EN;
/* Reset NDTR register */
Settings->DMA_Stream->NDTR = 0;
}
uint8_t TM_USART_DMA_Send(USART_TypeDef* USARTx, uint8_t* DataArray, uint16_t count) {
DMA_HandleTypeDef DMA_InitStruct;
/* Get USART settings */
TM_USART_DMA_INT_t* Settings = TM_USART_DMA_INT_GetSettings(USARTx);
/* Check if DMA is working now */
if (Settings->DMA_Stream->NDTR) {
/* DMA works right now */
return 0;
}
/* Set DMA options */
DMA_InitStruct.Instance = Settings->DMA_Stream;
DMA_InitStruct.Init.Channel = Settings->DMA_Channel;
DMA_InitStruct.Init.Direction = DMA_MEMORY_TO_PERIPH;
DMA_InitStruct.Init.PeriphInc = DMA_PINC_DISABLE;
DMA_InitStruct.Init.MemInc = DMA_MINC_ENABLE;
DMA_InitStruct.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
DMA_InitStruct.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
DMA_InitStruct.Init.Mode = DMA_NORMAL;
DMA_InitStruct.Init.Priority = DMA_PRIORITY_LOW;
DMA_InitStruct.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
DMA_InitStruct.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
DMA_InitStruct.Init.MemBurst = DMA_MBURST_SINGLE;
DMA_InitStruct.Init.PeriphBurst = DMA_PBURST_SINGLE;
/* Deinit first, clear all flags */
TM_DMA_ClearFlags(Settings->DMA_Stream);
/* Init HAL */
TM_DMA_Init(Settings->DMA_Stream, &DMA_InitStruct);
/* Start transfer */
TM_DMA_Start(&DMA_InitStruct, (uint32_t) &DataArray[0], (uint32_t) &USART_TX_REG(USARTx), count);
/* Enable USART TX DMA */
USARTx->CR3 |= USART_CR3_DMAT;
/* DMA has started */
return 1;
}
DMA_Stream_TypeDef* TM_USART_DMA_GetStream(USART_TypeDef* USARTx) {
/* Get USART settings */
return TM_USART_DMA_INT_GetSettings(USARTx)->DMA_Stream;
}
