void RequestSGXFreq(SYS_DATA *psSysData, IMG_BOOL bMaxFreq)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
struct gpu_platform_data *pdata;
IMG_UINT32 freq_index;
int res;
pdata = (struct gpu_platform_data *)gpsPVRLDMDev->dev.platform_data;
freq_index = bMaxFreq ? psSysSpecData->ui32SGXFreqListSize - 2 : 0;
TRAPZ_DESCRIBE(TRAPZ_KERN_DISP_PVR, PVRRequestSGXFreq, "RequestSGXFreq: toggling frequency. SwitchFreq = 1 means SGX switched to high frequency / SwitchFreq = 0 means SGX switched to low frequency");
TRAPZ_LOG_PRINTF(TRAPZ_LOG_DEBUG, 0, TRAPZ_KERN_DISP_PVR, PVRRequestSGXFreq, "SwitchFreq = %d", bMaxFreq, 0);
if (psSysSpecData->ui32SGXFreqListIndex != freq_index)
{
PVR_ASSERT(pdata->device_scale != IMG_NULL);
res = pdata->device_scale(&gpsPVRLDMDev->dev,
&gpsPVRLDMDev->dev,
psSysSpecData->pui32SGXFreqList[freq_index]);
if (res == 0)
psSysSpecData->ui32SGXFreqListIndex = freq_index;
else if (res == -EBUSY)
{
PVR_DPF((PVR_DBG_WARNING, "EnableSGXClocks: Unable to scale SGX frequency (EBUSY)"));
psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1;
}
else if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Unable to scale SGX frequency (%d)", res));
psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1;
}
}
}
static void mdss_mdp_video_vsync_intr_done(void *arg)
{
struct mdss_mdp_video_ctx *ctx;
ctx = (struct mdss_mdp_video_ctx *) arg;
/* ACOS_MOD_BEGIN */
TRAPZ_DESCRIBE(TRAPZ_KERN_DISP, Vsyncirq, "Primary VSYNC interrupt");
TRAPZ_LOG(TRAPZ_LOG_DEBUG, TRAPZ_CAT_KERNEL, TRAPZ_KERN_DISP,
Vsyncirq, 0, 0, 0, 0);
/* ACOS_MOD_END */
if (!ctx) {
pr_err("invalid ctx\n");
return;
}
pr_debug("intr ctl=%d\n", ctx->ctl_num);
complete(&ctx->vsync_comp);
}
