TVE_STATUS TVE_Init(void)
{
TV_INFO("Init Start\n");
// TVE controller would NOT reset register as default values
// Do it by SW here
//
_ResetBackupedTVERegisterValues();
#if 0
if (request_irq(MT6575_TVE_IRQ_ID,
(irq_handler_t)_TVE_InterruptHandler,
0, "mt6575-tve", NULL) < 0)
{
printk("[TVE][ERROR] fail to request TVE irq\n");
return TVE_STATUS_ERROR;
}
#endif
// Disable TVDAC defaultly
//OUTREG32(VTV_CON0, 0x0);
//OUTREG32(MIXEDSYS0_BASE + 0xBC0, 0x0);
//OUTREG32(MIXEDSYS0_BASE + 0xBC4, 0x0);
OUTREG32(0xF0007600,0x1012);//Disable TV DAC
TV_INFO("Init End\n");
return TVE_STATUS_OK;
}
TVC_STATUS TVC_Disable(void)
{
TV_INFO("\n");
if (_tvcContext.isTvcEnabled == false)
{
TV_WARNING("TVC is disabled, but disable again\n");
return TVC_STATUS_OK;
}
_tvcContext.isTvcEnabled = false;
OUTREG32(&TVC_REG->ENABLE, 0);
{
TVC_REG_UPDATE update = TVC_REG->REG_UPDATE;
update.REG_RDY = 1;
OUTREG32(&TVC_REG->REG_UPDATE, AS_UINT32(&update));
}
_WaitForRegUpdated();
_FreeInternalSRAM();
return TVC_STATUS_OK;
}
void TVC_ConfigSize(unsigned int src_width, unsigned int src_height, unsigned int tar_width, unsigned int tar_height)
{
_SIZE tarSize = {0};
TV_INFO("src %d, %d, tar %d, %d\n", src_width, src_height, tar_width, tar_height);
//src size
if (_tvcContext.srcSize.width != src_width ||
_tvcContext.srcSize.height != src_height)
{
_tvcContext.srcSize.width = src_width;
_tvcContext.srcSize.height = src_height;
_tvcContext.srcFormatSizeDirty = TRUE;
}
// Config Source Size
OUTREG32(&TVC_REG->SRC_WIDTH, _tvcContext.srcSize.width);
OUTREG32(&TVC_REG->SRC_HEIGHT, _tvcContext.srcSize.height);
// Config Line Pitch
{
TVC_REG_LINE_OFFSET OFFSET = TVC_REG->LINE_OFFSET;
OFFSET.LINE_OFFSET = (TVC_YUV420_BLK == _tvcContext.srcFormat ||
TVC_YUV420_PLANAR == _tvcContext.srcFormat) ?
(_tvcContext.srcSize.width * 1) :
(_tvcContext.srcSize.width * 2);
OUTREG32(&TVC_REG->LINE_OFFSET, AS_UINT32(&OFFSET));
}
//tar size
tarSize.width = tar_width;
tarSize.height = tar_height;
_SetTarSize(tar_width, tar_height);
_tvcContext.tarSize = tarSize;
_SetResizCoeff(_tvcContext.srcSize, tarSize);
_ConfigFullDisplayRegion();
{
TVC_REG_UPDATE update = TVC_REG->REG_UPDATE;
update.REG_RDY = 1;
OUTREG32(&TVC_REG->REG_UPDATE, AS_UINT32(&update));
}
}
TVC_STATUS TVC_Init(void)
{
TV_INFO("Init Start\n");
memset(&_tvcContext, 0, sizeof(_tvcContext));
// TVC controller would NOT reset register as default values
// Do it by SW here
//
_ResetBackupedTVCRegisterValues();
#if ENABLE_TVC_INTERRUPT
if (request_irq(MT6575_TVC_IRQ_ID,
(irq_handler_t)_TVC_InterruptHandler,
IRQF_TRIGGER_LOW, "mt6575-tvc", NULL) < 0)
{
printk("[TVC][ERROR] fail to request TVC irq\n");
return TVC_STATUS_ERROR;
}
init_waitqueue_head(&_tvcContext.tvc_checkline);
TVC_PowerOn();
// Enable Interrupt
{
TVC_REG_CON CON = TVC_REG->CONTROL;
CON.CHECK_IRQ = 1;
CON.OVRUN_IRQ = 1;
OUTREG32(&TVC_REG->CONTROL, AS_UINT32(&CON));
TVC_REG->CHECK_LINE = 1;
}
TVC_PowerOff();
#endif
TV_INFO("Init End\n");
return TVC_STATUS_OK;
}
TVC_STATUS TVC_Enable(void)
{
TV_INFO("\n");
if (_tvcContext.isTvcEnabled) {
printk("[TVC]TVC already enabled\n");
return TVC_STATUS_OK;
}
if (TVC_STATUS_OK != _AllocateInternalSRAM()) {
return TVC_STATUS_ERROR;
}
OUTREG32(&TVC_REG->PFH_DMA_ADDR, _tvcContext.pfhDmaBufPA);
OUTREG32(&TVC_REG->PFH_DMA_FIFO_LEN, TVC_PFH_DMA_FIFO_LEN);
OUTREG32(&TVC_REG->RESZ_ADDR, _tvcContext.reszLineBufPA);
{
TVC_REG_FRCFG frcfg = TVC_REG->FINE_RSZ_CFG;
frcfg.WMSZ = TVC_RSZ_WORK_MEM_SZ;
OUTREG32(&TVC_REG->FINE_RSZ_CFG, AS_UINT32(&frcfg));
}
{
TVC_REG_CON CON = TVC_REG->CONTROL;
CON.FAST_MODE = 1;
CON.DMAIF_GULTRA = 1;
CON.BURST_TYPE = 0;
CON.PFH = 1;
CON.RESZ_GULTRA = 1;
CON.PFH_GULTRA = 1;
CON.DMAIF_GPROT = 1;
OUTREG32(&TVC_REG->CONTROL, AS_UINT32(&CON));
}
OUTREG32(&TVC_REG->ENABLE, 1);
_tvcContext.isTvcEnabled = true;
return TVC_STATUS_OK;
}
TVC_STATUS TVC_CommitChanges(BOOL blocking)
{
if (_tvcContext.srcFormatSizeDirty)
{
_WaitForRegUpdated();
// Config Source Format
{
TVC_REG_CON CON = TVC_REG->CONTROL;
CON.DATA_FMT = _tvcContext.srcFormat;
OUTREG32(&TVC_REG->CONTROL, AS_UINT32(&CON));
}
// Config Source Size
OUTREG32(&TVC_REG->SRC_WIDTH, _tvcContext.srcSize.width);
OUTREG32(&TVC_REG->SRC_HEIGHT, _tvcContext.srcSize.height);
// Config Line Pitch
{
TVC_REG_LINE_OFFSET OFFSET = TVC_REG->LINE_OFFSET;
OFFSET.LINE_OFFSET = (TVC_YUV420_BLK == _tvcContext.srcFormat ||
TVC_YUV420_PLANAR == _tvcContext.srcFormat) ?
(_tvcContext.srcSize.width * 1) :
(_tvcContext.srcSize.width * 2);
OUTREG32(&TVC_REG->LINE_OFFSET, AS_UINT32(&OFFSET));
}
// Config Target Size
_ConfigTarSize();
// Config Full Display Region
_ConfigFullDisplayRegion();
// Config check line num, for MTKYUV the min is 4, for others the min is 1
#if 0
if (_tvcContext.srcFormat == TVC_YUV420_BLK) {
TVC_REG->CHECK_LINE = 4;
} else {
TVC_REG->CHECK_LINE = 1;
}
#endif
#if defined ENABLE_TVC_INTERRUPT
//_tvcContext.tvc_checkline_cnt = _tvcContext.srcSize.height - check_line_offset;
_tvcContext.tvc_checkline_cnt = 1 + check_line_offset;
if (_tvcContext.srcFormat == TVC_YUV420_BLK)
{
_tvcContext.tvc_checkline_cnt += 0x3;
_tvcContext.tvc_checkline_cnt &= ~0x3;
}
ASSERT(_tvcContext.tvc_checkline_cnt != 0);
TV_INFO("check line: %d\n", _tvcContext.tvc_checkline_cnt);
TVC_REG->CHECK_LINE = _tvcContext.tvc_checkline_cnt;
#endif
_tvcContext.srcFormatSizeDirty = FALSE;
}
OUTREG32(&TVC_REG->SRC_Y_ADDR, _tvcContext.srcAddrY);
if (_tvcContext.srcFormat == TVC_YUV420_BLK || _tvcContext.srcFormat == TVC_YUV420_PLANAR)
{
OUTREG32(&TVC_REG->SRC_U_ADDR, _tvcContext.srcAddrU);
OUTREG32(&TVC_REG->SRC_V_ADDR, _tvcContext.srcAddrV);
}
// Commit the Register Changes
{
TVC_REG_UPDATE update = TVC_REG->REG_UPDATE;
update.REG_RDY = 1;
OUTREG32(&TVC_REG->REG_UPDATE, AS_UINT32(&update));
}
if (blocking) {
_WaitForRegUpdated();
}
return TVC_STATUS_OK;
}
void TVC_SetCheckLineOffset(UINT32 offset)
{
check_line_offset = offset;
_tvcContext.srcFormatSizeDirty = TRUE;
TV_INFO("%d\n", check_line_offset);
}
